| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| */ |
| |
| #ifndef QCOM_PHY_QMP_QSERDES_PLL_H_ |
| #define QCOM_PHY_QMP_QSERDES_PLL_H_ |
| |
| /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ |
| #define QSERDES_PLL_BG_TIMER 0x00c |
| #define QSERDES_PLL_SSC_EN_CENTER 0x010 |
| #define QSERDES_PLL_SSC_ADJ_PER1 0x014 |
| #define QSERDES_PLL_SSC_ADJ_PER2 0x018 |
| #define QSERDES_PLL_SSC_PER1 0x01c |
| #define QSERDES_PLL_SSC_PER2 0x020 |
| #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 |
| #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 |
| #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c |
| #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 |
| #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c |
| #define QSERDES_PLL_CLK_ENABLE1 0x040 |
| #define QSERDES_PLL_SYS_CLK_CTRL 0x044 |
| #define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 |
| #define QSERDES_PLL_PLL_IVCO 0x050 |
| #define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 |
| #define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 |
| #define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 |
| #define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 |
| #define QSERDES_PLL_BG_TRIM 0x074 |
| #define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 |
| #define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c |
| #define QSERDES_PLL_CP_CTRL_MODE0 0x080 |
| #define QSERDES_PLL_CP_CTRL_MODE1 0x084 |
| #define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 |
| #define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c |
| #define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 |
| #define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 |
| #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 |
| #define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 |
| #define QSERDES_PLL_RESETSM_CNTRL 0x0b0 |
| #define QSERDES_PLL_LOCK_CMP_EN 0x0c4 |
| #define QSERDES_PLL_DEC_START_MODE0 0x0cc |
| #define QSERDES_PLL_DEC_START_MODE1 0x0d0 |
| #define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 |
| #define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc |
| #define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 |
| #define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 |
| #define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 |
| #define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec |
| #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 |
| #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 |
| #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 |
| #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c |
| #define QSERDES_PLL_VCO_TUNE_MAP 0x120 |
| #define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 |
| #define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 |
| #define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c |
| #define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 |
| #define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c |
| #define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 |
| #define QSERDES_PLL_CLK_SELECT 0x16c |
| #define QSERDES_PLL_HSCLK_SEL 0x170 |
| #define QSERDES_PLL_CORECLK_DIV 0x17c |
| #define QSERDES_PLL_CORE_CLK_EN 0x184 |
| #define QSERDES_PLL_CMN_CONFIG 0x18c |
| #define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 |
| #define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 |
| |
| #endif |
