| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| */ |
| |
| #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_ |
| #define QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_ |
| |
| /* Only for QMP V5_20 PHY - TX registers */ |
| #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 |
| #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 |
| #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 |
| #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c |
| |
| /* Only for QMP V5_20 PHY - RX registers */ |
| #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 |
| #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c |
| #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 |
| #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c |
| #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 |
| #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c |
| #define QSERDES_V5_20_RX_DFE_3 0x090 |
| #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 |
| #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 |
| #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 |
| #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc |
| #define QSERDES_V5_20_RX_GM_CAL 0x0ec |
| #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 |
| #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 |
| #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 |
| #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c |
| #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 |
| #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 |
| #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c |
| #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 |
| #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 |
| #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 |
| #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c |
| #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 |
| #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 |
| #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 |
| #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c |
| #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 |
| #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 |
| #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 |
| #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac |
| #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 |
| #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 |
| #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 |
| #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 |
| #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 |
| #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc |
| #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 |
| #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 |
| #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 |
| #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 |
| #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 |
| #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 |
| |
| #endif |
