drivers/net/ethernet/microchip/sparx5/sparx5_regs.c - linux - Git at Google

 // SPDX-License-Identifier: GPL-2.0+
 /* Microchip Sparx5 Switch driver
  *
  * Copyright (c) 2024 Microchip Technology Inc.
  */

 /* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200.
  * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b
  */

 #include "sparx5_regs.h"

 const unsigned int sparx5_tsize[TSIZE_LAST] = {
 	[TC_DEV10G] = 12,
 	[TC_DEV2G5] = 65,
 	[TC_DEV5G] = 13,
 	[TC_PCS10G_BR] = 12,
 	[TC_PCS5G_BR] = 13,
 };

 const unsigned int sparx5_raddr[RADDR_LAST] = {
 	[RA_CPU_PROC_CTRL] = 176,
 	[RA_GCB_SOFT_RST] = 8,
 	[RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 24,
 };

 const unsigned int sparx5_rcnt[RCNT_LAST] = {
 	[RC_ANA_AC_OWN_UPSID] = 3,
 	[RC_ANA_ACL_VCAP_S2_CFG] = 70,
 	[RC_ANA_ACL_OWN_UPSID] = 3,
 	[RC_ANA_CL_OWN_UPSID] = 3,
 	[RC_ANA_L2_OWN_UPSID] = 3,
 	[RC_ASM_PORT_CFG] = 67,
 	[RC_DSM_BUF_CFG] = 67,
 	[RC_DSM_DEV_TX_STOP_WM_CFG] = 67,
 	[RC_DSM_RX_PAUSE_CFG] = 67,
 	[RC_DSM_MAC_CFG] = 67,
 	[RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 65,
 	[RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 65,
 	[RC_DSM_TAXI_CAL_CFG] = 9,
 	[RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 65,
 	[RC_HSCH_PORT_MODE] = 70,
 	[RC_QFWD_SWITCH_PORT_MODE] = 70,
 	[RC_QSYS_PAUSE_CFG] = 70,
 	[RC_QSYS_ATOP] = 70,
 	[RC_QSYS_FWD_PRESSURE] = 70,
 	[RC_QSYS_CAL_AUTO] = 7,
 	[RC_REW_OWN_UPSID] = 3,
 	[RC_REW_RTAG_ETAG_CTRL] = 70,
 };

 const unsigned int sparx5_gaddr[GADDR_LAST] = {
 	[GA_ANA_AC_RAM_CTRL] = 839108,
 	[GA_ANA_AC_PS_COMMON] = 894472,
 	[GA_ANA_AC_MIRROR_PROBE] = 893696,
 	[GA_ANA_AC_SRC] = 849920,
 	[GA_ANA_AC_PGID] = 786432,
 	[GA_ANA_AC_TSN_SF] = 839136,
 	[GA_ANA_AC_TSN_SF_CFG] = 839680,
 	[GA_ANA_AC_TSN_SF_STATUS] = 839072,
 	[GA_ANA_AC_SG_ACCESS] = 839140,
 	[GA_ANA_AC_SG_CONFIG] = 851584,
 	[GA_ANA_AC_SG_STATUS] = 839088,
 	[GA_ANA_AC_SG_STATUS_STICKY] = 839152,
 	[GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 851552,
 	[GA_ANA_AC_STAT_CNT_CFG_PORT] = 843776,
 	[GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 893792,
 	[GA_ANA_ACL_COMMON] = 32768,
 	[GA_ANA_ACL_KEY_SEL] = 34200,
 	[GA_ANA_ACL_CNT_B] = 16384,
 	[GA_ANA_ACL_STICKY] = 36408,
 	[GA_ANA_AC_POL_POL_ALL_CFG] = 75968,
 	[GA_ANA_AC_POL_COMMON_BDLB] = 79048,
 	[GA_ANA_AC_POL_COMMON_BUM_SLB] = 79056,
 	[GA_ANA_AC_SDLB_LBGRP_TBL] = 295468,
 	[GA_ANA_CL_PORT] = 131072,
 	[GA_ANA_CL_COMMON] = 166912,
 	[GA_ANA_L2_COMMON] = 566024,
 	[GA_ANA_L3_COMMON] = 493632,
 	[GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 491460,
 	[GA_ASM_CFG] = 33280,
 	[GA_ASM_PFC_TIMER_CFG] = 34716,
 	[GA_ASM_LBK_WM_CFG] = 34744,
 	[GA_ASM_LBK_MISC_CFG] = 34756,
 	[GA_ASM_RAM_CTRL] = 34832,
 	[GA_EACL_ES2_KEY_SELECT_PROFILE] = 149504,
 	[GA_EACL_CNT_TBL] = 122880,
 	[GA_EACL_POL_CFG] = 150608,
 	[GA_EACL_ES2_STICKY] = 118696,
 	[GA_EACL_RAM_CTRL] = 118736,
 	[GA_GCB_SIO_CTRL] = 876,
 	[GA_HSCH_HSCH_DWRR] = 162816,
 	[GA_HSCH_HSCH_MISC] = 163104,
 	[GA_HSCH_HSCH_LEAK_LISTS] = 161664,
 	[GA_HSCH_SYSTEM] = 184000,
 	[GA_HSCH_MMGT] = 162368,
 	[GA_HSCH_TAS_CONFIG] = 162384,
 	[GA_PTP_PTP_CFG] = 320,
 	[GA_PTP_PTP_TOD_DOMAINS] = 336,
 	[GA_PTP_PHASE_DETECTOR_CTRL] = 420,
 	[GA_QSYS_CALCFG] = 2304,
 	[GA_QSYS_RAM_CTRL] = 2344,
 	[GA_REW_COMMON] = 387264,
 	[GA_REW_PORT] = 360448,
 	[GA_REW_VOE_PORT_LM_CNT] = 393216,
 	[GA_REW_RAM_CTRL] = 378696,
 	[GA_VOP_RAM_CTRL] = 279176,
 	[GA_XQS_SYSTEM] = 6768,
 	[GA_XQS_QLIMIT_SHR] = 7936,
 };

 const unsigned int sparx5_gcnt[GCNT_LAST] = {
 	[GC_ANA_AC_SRC] = 102,
 	[GC_ANA_AC_PGID] = 3290,
 	[GC_ANA_AC_TSN_SF_CFG] = 1024,
 	[GC_ANA_AC_STAT_CNT_CFG_PORT] = 70,
 	[GC_ANA_ACL_KEY_SEL] = 134,
 	[GC_ANA_ACL_CNT_A] = 4096,
 	[GC_ANA_ACL_CNT_B] = 4096,
 	[GC_ANA_AC_SDLB_LBGRP_TBL] = 10,
 	[GC_ANA_AC_SDLB_LBSET_TBL] = 4616,
 	[GC_ANA_CL_PORT] = 70,
 	[GC_ANA_L2_ISDX_LIMIT] = 1536,
 	[GC_ANA_L2_ISDX] = 4096,
 	[GC_ANA_L3_VLAN] = 5120,
 	[GC_ASM_DEV_STATISTICS] = 65,
 	[GC_EACL_ES2_KEY_SELECT_PROFILE] = 138,
 	[GC_EACL_CNT_TBL] = 2048,
 	[GC_GCB_SIO_CTRL] = 3,
 	[GC_HSCH_HSCH_CFG] = 5040,
 	[GC_HSCH_HSCH_DWRR] = 72,
 	[GC_PTP_PTP_PINS] = 5,
 	[GC_PTP_PHASE_DETECTOR_CTRL] = 5,
 	[GC_REW_PORT] = 70,
 	[GC_REW_VOE_PORT_LM_CNT] = 520,
 };

 const unsigned int sparx5_gsize[GSIZE_LAST] = {
 	[GW_ANA_AC_SRC] = 16,
 	[GW_ANA_L2_COMMON] = 700,
 	[GW_ASM_CFG] = 1088,
 	[GW_CPU_CPU_REGS] = 204,
 	[GW_DEV2G5_PHASE_DETECTOR_CTRL] = 8,
 	[GW_FDMA_FDMA] = 428,
 	[GW_GCB_CHIP_REGS] = 424,
 	[GW_HSCH_TAS_CONFIG] = 12,
 	[GW_PTP_PHASE_DETECTOR_CTRL] = 8,
 	[GW_QSYS_PAUSE_CFG] = 1128,
 };

 const unsigned int sparx5_fpos[FPOS_LAST] = {
 	[FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 12,
 	[FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 11,
 	[FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 10,
 	[FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 9,
 	[FP_CPU_PROC_CTRL_VINITHI] = 8,
 	[FP_CPU_PROC_CTRL_CFGTE] = 7,
 	[FP_CPU_PROC_CTRL_CP15S_DISABLE] = 6,
 	[FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 5,
 	[FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 1,
 	[FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 7,
 	[FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 6,
 	[FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 7,
 	[FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 6,
 	[FP_FDMA_CH_CFG_CH_INJ_PORT] = 5,
 	[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 26,
 	[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 24,
 	[FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 23,
 	[FP_PTP_PHAD_CTRL_PHAD_ENA] = 7,
 	[FP_PTP_PHAD_CTRL_PHAD_FAILED] = 6,
 };

 const unsigned int sparx5_fsize[FSIZE_LAST] = {
 	[FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 32,
 	[FW_ANA_AC_SRC_CFG_PORT_MASK] = 32,
 	[FW_ANA_AC_PGID_CFG_PORT_MASK] = 32,
 	[FW_ANA_AC_TSN_SF_PORT_NUM] = 9,
 	[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 10,
 	[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 10,
 	[FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 10,
 	[FW_ANA_AC_PORT_SGE_CFG_MASK] = 16,
 	[FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 13,
 	[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 5,
 	[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 13,
 	[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 13,
 	[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 4,
 	[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 13,
 	[FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 32,
 	[FW_ANA_L2_DLB_CFG_DLB_IDX] = 13,
 	[FW_ANA_L2_TSN_CFG_TSN_SFID] = 10,
 	[FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 32,
 	[FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 4,
 	[FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 9,
 	[FW_HSCH_SE_CFG_SE_DWRR_CNT] = 7,
 	[FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 16,
 	[FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 7,
 	[FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 13,
 	[FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 16,
 	[FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 7,
 	[FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 16,
 	[FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 14,
 	[FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 11,
 	[FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 14,
 	[FW_PTP_PTP_PIN_INTR_INTR_PTP] = 5,
 	[FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 5,
 	[FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 5,
 	[FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 2,
 	[FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 7,
 	[FW_QRES_RES_CFG_WM_HIGH] = 12,
 	[FW_QRES_RES_STAT_MAXUSE] = 21,
 	[FW_QRES_RES_STAT_CUR_INUSE] = 21,
 	[FW_QSYS_PAUSE_CFG_PAUSE_START] = 12,
 	[FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 12,
 	[FW_QSYS_ATOP_ATOP] = 12,
 	[FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 12,
 	[FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 7,
 	[FW_XQS_STAT_CFG_STAT_VIEW] = 13,
 	[FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 15,
 	[FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 15,
 	[FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 15,
 	[FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 15,
 };
	// SPDX-License-Identifier: GPL-2.0+
	/* Microchip Sparx5 Switch driver
	*
	* Copyright (c) 2024 Microchip Technology Inc.
	*/

	/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200.
	* Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b
	*/

	#include "sparx5_regs.h"

	const unsigned int sparx5_tsize[TSIZE_LAST] = {
	[TC_DEV10G] = 12,
	[TC_DEV2G5] = 65,
	[TC_DEV5G] = 13,
	[TC_PCS10G_BR] = 12,
	[TC_PCS5G_BR] = 13,
	};

	const unsigned int sparx5_raddr[RADDR_LAST] = {
	[RA_CPU_PROC_CTRL] = 176,
	[RA_GCB_SOFT_RST] = 8,
	[RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 24,
	};

	const unsigned int sparx5_rcnt[RCNT_LAST] = {
	[RC_ANA_AC_OWN_UPSID] = 3,
	[RC_ANA_ACL_VCAP_S2_CFG] = 70,
	[RC_ANA_ACL_OWN_UPSID] = 3,
	[RC_ANA_CL_OWN_UPSID] = 3,
	[RC_ANA_L2_OWN_UPSID] = 3,
	[RC_ASM_PORT_CFG] = 67,
	[RC_DSM_BUF_CFG] = 67,
	[RC_DSM_DEV_TX_STOP_WM_CFG] = 67,
	[RC_DSM_RX_PAUSE_CFG] = 67,
	[RC_DSM_MAC_CFG] = 67,
	[RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 65,
	[RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 65,
	[RC_DSM_TAXI_CAL_CFG] = 9,
	[RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 65,
	[RC_HSCH_PORT_MODE] = 70,
	[RC_QFWD_SWITCH_PORT_MODE] = 70,
	[RC_QSYS_PAUSE_CFG] = 70,
	[RC_QSYS_ATOP] = 70,
	[RC_QSYS_FWD_PRESSURE] = 70,
	[RC_QSYS_CAL_AUTO] = 7,
	[RC_REW_OWN_UPSID] = 3,
	[RC_REW_RTAG_ETAG_CTRL] = 70,
	};

	const unsigned int sparx5_gaddr[GADDR_LAST] = {
	[GA_ANA_AC_RAM_CTRL] = 839108,
	[GA_ANA_AC_PS_COMMON] = 894472,
	[GA_ANA_AC_MIRROR_PROBE] = 893696,
	[GA_ANA_AC_SRC] = 849920,
	[GA_ANA_AC_PGID] = 786432,
	[GA_ANA_AC_TSN_SF] = 839136,
	[GA_ANA_AC_TSN_SF_CFG] = 839680,
	[GA_ANA_AC_TSN_SF_STATUS] = 839072,
	[GA_ANA_AC_SG_ACCESS] = 839140,
	[GA_ANA_AC_SG_CONFIG] = 851584,
	[GA_ANA_AC_SG_STATUS] = 839088,
	[GA_ANA_AC_SG_STATUS_STICKY] = 839152,
	[GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 851552,
	[GA_ANA_AC_STAT_CNT_CFG_PORT] = 843776,
	[GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 893792,
	[GA_ANA_ACL_COMMON] = 32768,
	[GA_ANA_ACL_KEY_SEL] = 34200,
	[GA_ANA_ACL_CNT_B] = 16384,
	[GA_ANA_ACL_STICKY] = 36408,
	[GA_ANA_AC_POL_POL_ALL_CFG] = 75968,
	[GA_ANA_AC_POL_COMMON_BDLB] = 79048,
	[GA_ANA_AC_POL_COMMON_BUM_SLB] = 79056,
	[GA_ANA_AC_SDLB_LBGRP_TBL] = 295468,
	[GA_ANA_CL_PORT] = 131072,
	[GA_ANA_CL_COMMON] = 166912,
	[GA_ANA_L2_COMMON] = 566024,
	[GA_ANA_L3_COMMON] = 493632,
	[GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 491460,
	[GA_ASM_CFG] = 33280,
	[GA_ASM_PFC_TIMER_CFG] = 34716,
	[GA_ASM_LBK_WM_CFG] = 34744,
	[GA_ASM_LBK_MISC_CFG] = 34756,
	[GA_ASM_RAM_CTRL] = 34832,
	[GA_EACL_ES2_KEY_SELECT_PROFILE] = 149504,
	[GA_EACL_CNT_TBL] = 122880,
	[GA_EACL_POL_CFG] = 150608,
	[GA_EACL_ES2_STICKY] = 118696,
	[GA_EACL_RAM_CTRL] = 118736,
	[GA_GCB_SIO_CTRL] = 876,
	[GA_HSCH_HSCH_DWRR] = 162816,
	[GA_HSCH_HSCH_MISC] = 163104,
	[GA_HSCH_HSCH_LEAK_LISTS] = 161664,
	[GA_HSCH_SYSTEM] = 184000,
	[GA_HSCH_MMGT] = 162368,
	[GA_HSCH_TAS_CONFIG] = 162384,
	[GA_PTP_PTP_CFG] = 320,
	[GA_PTP_PTP_TOD_DOMAINS] = 336,
	[GA_PTP_PHASE_DETECTOR_CTRL] = 420,
	[GA_QSYS_CALCFG] = 2304,
	[GA_QSYS_RAM_CTRL] = 2344,
	[GA_REW_COMMON] = 387264,
	[GA_REW_PORT] = 360448,
	[GA_REW_VOE_PORT_LM_CNT] = 393216,
	[GA_REW_RAM_CTRL] = 378696,
	[GA_VOP_RAM_CTRL] = 279176,
	[GA_XQS_SYSTEM] = 6768,
	[GA_XQS_QLIMIT_SHR] = 7936,
	};

	const unsigned int sparx5_gcnt[GCNT_LAST] = {
	[GC_ANA_AC_SRC] = 102,
	[GC_ANA_AC_PGID] = 3290,
	[GC_ANA_AC_TSN_SF_CFG] = 1024,
	[GC_ANA_AC_STAT_CNT_CFG_PORT] = 70,
	[GC_ANA_ACL_KEY_SEL] = 134,
	[GC_ANA_ACL_CNT_A] = 4096,
	[GC_ANA_ACL_CNT_B] = 4096,
	[GC_ANA_AC_SDLB_LBGRP_TBL] = 10,
	[GC_ANA_AC_SDLB_LBSET_TBL] = 4616,
	[GC_ANA_CL_PORT] = 70,
	[GC_ANA_L2_ISDX_LIMIT] = 1536,
	[GC_ANA_L2_ISDX] = 4096,
	[GC_ANA_L3_VLAN] = 5120,
	[GC_ASM_DEV_STATISTICS] = 65,
	[GC_EACL_ES2_KEY_SELECT_PROFILE] = 138,
	[GC_EACL_CNT_TBL] = 2048,
	[GC_GCB_SIO_CTRL] = 3,
	[GC_HSCH_HSCH_CFG] = 5040,
	[GC_HSCH_HSCH_DWRR] = 72,
	[GC_PTP_PTP_PINS] = 5,
	[GC_PTP_PHASE_DETECTOR_CTRL] = 5,
	[GC_REW_PORT] = 70,
	[GC_REW_VOE_PORT_LM_CNT] = 520,
	};

	const unsigned int sparx5_gsize[GSIZE_LAST] = {
	[GW_ANA_AC_SRC] = 16,
	[GW_ANA_L2_COMMON] = 700,
	[GW_ASM_CFG] = 1088,
	[GW_CPU_CPU_REGS] = 204,
	[GW_DEV2G5_PHASE_DETECTOR_CTRL] = 8,
	[GW_FDMA_FDMA] = 428,
	[GW_GCB_CHIP_REGS] = 424,
	[GW_HSCH_TAS_CONFIG] = 12,
	[GW_PTP_PHASE_DETECTOR_CTRL] = 8,
	[GW_QSYS_PAUSE_CFG] = 1128,
	};

	const unsigned int sparx5_fpos[FPOS_LAST] = {
	[FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 12,
	[FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 11,
	[FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 10,
	[FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 9,
	[FP_CPU_PROC_CTRL_VINITHI] = 8,
	[FP_CPU_PROC_CTRL_CFGTE] = 7,
	[FP_CPU_PROC_CTRL_CP15S_DISABLE] = 6,
	[FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 5,
	[FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 1,
	[FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 7,
	[FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 6,
	[FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 7,
	[FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 6,
	[FP_FDMA_CH_CFG_CH_INJ_PORT] = 5,
	[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 26,
	[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 24,
	[FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 23,
	[FP_PTP_PHAD_CTRL_PHAD_ENA] = 7,
	[FP_PTP_PHAD_CTRL_PHAD_FAILED] = 6,
	};

	const unsigned int sparx5_fsize[FSIZE_LAST] = {
	[FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 32,
	[FW_ANA_AC_SRC_CFG_PORT_MASK] = 32,
	[FW_ANA_AC_PGID_CFG_PORT_MASK] = 32,
	[FW_ANA_AC_TSN_SF_PORT_NUM] = 9,
	[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 10,
	[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 10,
	[FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 10,
	[FW_ANA_AC_PORT_SGE_CFG_MASK] = 16,
	[FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 13,
	[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 5,
	[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 13,
	[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 13,
	[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 4,
	[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 13,
	[FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 32,
	[FW_ANA_L2_DLB_CFG_DLB_IDX] = 13,
	[FW_ANA_L2_TSN_CFG_TSN_SFID] = 10,
	[FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 32,
	[FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 4,
	[FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 9,
	[FW_HSCH_SE_CFG_SE_DWRR_CNT] = 7,
	[FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 16,
	[FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 7,
	[FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 13,
	[FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 16,
	[FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 7,
	[FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 16,
	[FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 14,
	[FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 11,
	[FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 14,
	[FW_PTP_PTP_PIN_INTR_INTR_PTP] = 5,
	[FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 5,
	[FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 5,
	[FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 2,
	[FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 7,
	[FW_QRES_RES_CFG_WM_HIGH] = 12,
	[FW_QRES_RES_STAT_MAXUSE] = 21,
	[FW_QRES_RES_STAT_CUR_INUSE] = 21,
	[FW_QSYS_PAUSE_CFG_PAUSE_START] = 12,
	[FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 12,
	[FW_QSYS_ATOP_ATOP] = 12,
	[FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 12,
	[FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 7,
	[FW_XQS_STAT_CFG_STAT_VIEW] = 13,
	[FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 15,
	[FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 15,
	[FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 15,
	[FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 15,
	};