Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G2L USBPHY Control

maintainers:
  - Biju Das <biju.das.jz@bp.renesas.com>

description:
  The RZ/G2L USBPHY Control mainly controls reset and power down of the
  USB/PHY.

properties:
  compatible:
    items:
      - enum:
          - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
      - const: renesas,rzg2l-usbphy-ctrl

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  power-domains:
    maxItems: 1

  '#reset-cells':
    const: 1
    description: |
      The phandle's argument in the reset specifier is the PHY reset associated
      with the USB port.
      0 = Port 1 Phy reset
      1 = Port 2 Phy reset

required:
  - compatible
  - reg
  - clocks
  - resets
  - power-domains
  - '#reset-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r9a07g044-cpg.h>

    phyrst: usbphy-ctrl@11c40000 {
        compatible = "renesas,r9a07g044-usbphy-ctrl",
                     "renesas,rzg2l-usbphy-ctrl";
        reg = <0x11c40000 0x10000>;
        clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
        resets = <&cpg R9A07G044_USB_PRESETN>;
        power-domains = <&cpg>;
        #reset-cells = <1>;
    };