| High-Frequency PLL (HFPLL) | |
| PROPERTIES | |
| - compatible: | |
| Usage: required | |
| Value type: <string>: | |
| shall contain only one of the following. The generic | |
| compatible "qcom,hfpll" should be also included. | |
| "qcom,hfpll-ipq8064", "qcom,hfpll" | |
| "qcom,hfpll-apq8064", "qcom,hfpll" | |
| "qcom,hfpll-msm8974", "qcom,hfpll" | |
| "qcom,hfpll-msm8960", "qcom,hfpll" | |
| - reg: | |
| Usage: required | |
| Value type: <prop-encoded-array> | |
| Definition: address and size of HPLL registers. An optional second | |
| element specifies the address and size of the alias | |
| register region. | |
| - clocks: | |
| Usage: required | |
| Value type: <prop-encoded-array> | |
| Definition: reference to the xo clock. | |
| - clock-names: | |
| Usage: required | |
| Value type: <stringlist> | |
| Definition: must be "xo". | |
| - clock-output-names: | |
| Usage: required | |
| Value type: <string> | |
| Definition: Name of the PLL. Typically hfpllX where X is a CPU number | |
| starting at 0. Otherwise hfpll_Y where Y is more specific | |
| such as "l2". | |
| Example: | |
| 1) An HFPLL for the L2 cache. | |
| clock-controller@f9016000 { | |
| compatible = "qcom,hfpll-ipq8064", "qcom,hfpll"; | |
| reg = <0xf9016000 0x30>; | |
| clocks = <&xo_board>; | |
| clock-names = "xo"; | |
| clock-output-names = "hfpll_l2"; | |
| }; | |
| 2) An HFPLL for CPU0. This HFPLL has the alias register region. | |
| clock-controller@f908a000 { | |
| compatible = "qcom,hfpll-ipq8064", "qcom,hfpll"; | |
| reg = <0xf908a000 0x30>, <0xf900a000 0x30>; | |
| clocks = <&xo_board>; | |
| clock-names = "xo"; | |
| clock-output-names = "hfpll0"; | |
| }; |