| /* |
| * Copyright 2016 ZTE Corporation. |
| * Copyright 2016 Linaro Ltd. |
| * |
| * This file is dual-licensed: you can use it either under the terms |
| * of the GPL or the X11 license, at your option. Note that this dual |
| * licensing only applies to this file, and not this project as a |
| * whole. |
| * |
| * a) This library is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of the |
| * License, or (at your option) any later version. |
| * |
| * This library is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * Or, alternatively, |
| * |
| * b) Permission is hereby granted, free of charge, to any person |
| * obtaining a copy of this software and associated documentation |
| * files (the "Software"), to deal in the Software without |
| * restriction, including without limitation the rights to use, |
| * copy, modify, merge, publish, distribute, sublicense, and/or |
| * sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following |
| * conditions: |
| * |
| * The above copyright notice and this permission notice shall be |
| * included in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| |
| #include <dt-bindings/input/input.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/clock/zx296718-clock.h> |
| |
| / { |
| compatible = "zte,zx296718"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| interrupt-parent = <&gic>; |
| |
| aliases { |
| serial0 = &uart0; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| }; |
| }; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53","arm,armv8"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| clocks = <&topcrm A53_GATE>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53","arm,armv8"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| clocks = <&topcrm A53_GATE>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53","arm,armv8"; |
| reg = <0x0 0x2>; |
| enable-method = "psci"; |
| clocks = <&topcrm A53_GATE>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53","arm,armv8"; |
| reg = <0x0 0x3>; |
| enable-method = "psci"; |
| clocks = <&topcrm A53_GATE>; |
| operating-points-v2 = <&cluster0_opp>; |
| }; |
| }; |
| |
| cluster0_opp: opp-table0 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp-500000000 { |
| opp-hz = /bits/ 64 <500000000>; |
| clock-latency-ns = <500000>; |
| }; |
| |
| opp-648000000 { |
| opp-hz = /bits/ 64 <648000000>; |
| clock-latency-ns = <500000>; |
| }; |
| |
| opp-800000000 { |
| opp-hz = /bits/ 64 <800000000>; |
| clock-latency-ns = <500000>; |
| }; |
| |
| opp-1000000000 { |
| opp-hz = /bits/ 64 <1000000000>; |
| clock-latency-ns = <500000>; |
| }; |
| |
| opp-1188000000 { |
| opp-hz = /bits/ 64 <1188000000>; |
| clock-latency-ns = <500000>; |
| }; |
| }; |
| |
| clk24k: clk-24k { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <24000>; |
| clock-output-names = "rtcclk"; |
| }; |
| |
| osc32k: clk-osc32k { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32000>; |
| clock-output-names = "osc32k"; |
| }; |
| |
| osc12m: clk-osc12m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <12000000>; |
| clock-output-names = "osc12m"; |
| }; |
| |
| osc24m: clk-osc24m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <24000000>; |
| clock-output-names = "osc24m"; |
| }; |
| |
| osc25m: clk-osc25m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <25000000>; |
| clock-output-names = "osc25m"; |
| }; |
| |
| osc60m: clk-osc60m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <60000000>; |
| clock-output-names = "osc60m"; |
| }; |
| |
| osc99m: clk-osc99m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <99000000>; |
| clock-output-names = "osc99m"; |
| }; |
| |
| osc125m: clk-osc125m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <125000000>; |
| clock-output-names = "osc125m"; |
| }; |
| |
| osc198m: clk-osc198m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <198000000>; |
| clock-output-names = "osc198m"; |
| }; |
| |
| pll_audio: clk-pll-884m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <884000000>; |
| clock-output-names = "pll_audio"; |
| }; |
| |
| pll_ddr: clk-pll-932m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <932000000>; |
| clock-output-names = "pll_ddr"; |
| }; |
| |
| pll_hsic: clk-pll-960m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <960000000>; |
| clock-output-names = "pll_hsic"; |
| }; |
| |
| pll_mac: clk-pll-1000m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <1000000000>; |
| clock-output-names = "pll_mac"; |
| }; |
| |
| pll_mm0: clk-pll-1188m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <1188000000>; |
| clock-output-names = "pll_mm0"; |
| }; |
| |
| pll_mm1: clk-pll-1296m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <1296000000>; |
| clock-output-names = "pll_mm1"; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| gic: interrupt-controller@2a00000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| reg = <0x02a00000 0x10000>, |
| <0x02b00000 0xc0000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "simple-bus"; |
| ranges; |
| |
| aon_sysctrl: aon-sysctrl@116000 { |
| compatible = "zte,zx296718-aon-sysctrl", "syscon"; |
| reg = <0x116000 0x1000>; |
| }; |
| |
| uart0: uart@11f000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| arm,primecell-periphid = <0x001feffe>; |
| reg = <0x11f000 0x1000>; |
| interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&osc24m>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| sd0: mmc@1110000 { |
| compatible = "zte,zx296718-dw-mshc"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x01110000 0x1000>; |
| interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| fifo-depth = <32>; |
| data-addr = <0x200>; |
| fifo-watermark-aligned; |
| bus-width = <4>; |
| clock-frequency = <50000000>; |
| clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>; |
| clock-names = "biu", "ciu"; |
| num-slots = <1>; |
| max-frequency = <50000000>; |
| cap-sdio-irq; |
| cap-sd-highspeed; |
| sd-uhs-sdr12; |
| sd-uhs-sdr25; |
| sd-uhs-sdr50; |
| sd-uhs-sdr104; |
| sd-uhs-ddr50; |
| status = "disabled"; |
| }; |
| |
| sd1: mmc@1111000 { |
| compatible = "zte,zx296718-dw-mshc"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x01111000 0x1000>; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| fifo-depth = <32>; |
| data-addr = <0x200>; |
| fifo-watermark-aligned; |
| bus-width = <4>; |
| clock-frequency = <167000000>; |
| clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>; |
| clock-names = "biu", "ciu"; |
| num-slots = <1>; |
| max-frequency = <167000000>; |
| cap-sdio-irq; |
| cap-sd-highspeed; |
| status = "disabled"; |
| }; |
| |
| dma: dma-controller@1460000 { |
| compatible = "zte,zx296702-dma"; |
| reg = <0x01460000 0x1000>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&osc24m>; |
| clock-names = "dmaclk"; |
| #dma-cells = <1>; |
| dma-channels = <32>; |
| dma-requests = <32>; |
| }; |
| |
| lsp0crm: clock-controller@1420000 { |
| compatible = "zte,zx296718-lsp0crm"; |
| reg = <0x01420000 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| lsp1crm: clock-controller@1430000 { |
| compatible = "zte,zx296718-lsp1crm"; |
| reg = <0x01430000 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| vou: vou@1440000 { |
| compatible = "zte,zx296718-vou"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x1440000 0x10000>; |
| |
| dpc: dpc@0 { |
| compatible = "zte,zx296718-dpc"; |
| reg = <0x0000 0x1000>, <0x1000 0x1000>, |
| <0x5000 0x1000>, <0x6000 0x1000>, |
| <0xa000 0x1000>; |
| reg-names = "osd", "timing_ctrl", |
| "dtrc", "vou_ctrl", |
| "otfppu"; |
| interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>, |
| <&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>; |
| clock-names = "aclk", "ppu_wclk", |
| "main_wclk", "aux_wclk"; |
| }; |
| |
| hdmi: hdmi@c000 { |
| compatible = "zte,zx296718-hdmi"; |
| reg = <0xc000 0x4000>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&topcrm HDMI_OSC_CEC>, |
| <&topcrm HDMI_OSC_CLK>, |
| <&topcrm HDMI_XCLK>; |
| clock-names = "osc_cec", "osc_clk", "xclk"; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| tvenc: tvenc@2000 { |
| compatible = "zte,zx296718-tvenc"; |
| reg = <0x2000 0x1000>; |
| zte,tvenc-power-control = <&sysctrl 0x170 0x10>; |
| status = "disabled"; |
| }; |
| }; |
| |
| topcrm: clock-controller@1461000 { |
| compatible = "zte,zx296718-topcrm"; |
| reg = <0x01461000 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| sysctrl: sysctrl@1463000 { |
| compatible = "zte,zx296718-sysctrl", "syscon"; |
| reg = <0x1463000 0x1000>; |
| }; |
| |
| emmc: mmc@1470000{ |
| compatible = "zte,zx296718-dw-mshc"; |
| reg = <0x01470000 0x1000>; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| zte,aon-syscon = <&aon_sysctrl>; |
| bus-width = <8>; |
| fifo-depth = <128>; |
| data-addr = <0x200>; |
| fifo-watermark-aligned; |
| clock-frequency = <167000000>; |
| clocks = <&topcrm EMMC_NAND_AHB>, <&topcrm EMMC_WCLK>; |
| clock-names = "biu", "ciu"; |
| max-frequency = <167000000>; |
| cap-mmc-highspeed; |
| mmc-ddr-1_8v; |
| mmc-hs200-1_8v; |
| non-removable; |
| disable-wp; |
| status = "disabled"; |
| }; |
| |
| audiocrm: clock-controller@1480000 { |
| compatible = "zte,zx296718-audiocrm"; |
| reg = <0x01480000 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| spdif0: spdif@1488000 { |
| compatible = "zte,zx296702-spdif"; |
| reg = <0x1488000 0x1000>; |
| clocks = <&audiocrm AUDIO_SPDIF0_WCLK>; |
| clock-names = "tx"; |
| interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| #sound-dai-cells = <0>; |
| dmas = <&dma 30>; |
| dma-names = "tx"; |
| status = "disabled"; |
| }; |
| }; |
| }; |
