| /* |
| * Device Tree Source for the r8a7792 SoC |
| * |
| * Copyright (C) 2016 Cogent Embedded Inc. |
| * |
| * This file is licensed under the terms of the GNU General Public License |
| * version 2. This program is licensed "as is" without any warranty of any |
| * kind, whether express or implied. |
| */ |
| |
| #include <dt-bindings/clock/r8a7792-clock.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/power/r8a7792-sysc.h> |
| |
| / { |
| compatible = "renesas,r8a7792"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| enable-method = "renesas,apmu"; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0>; |
| clock-frequency = <1000000000>; |
| clocks = <&cpg_clocks R8A7792_CLK_Z>; |
| power-domains = <&sysc R8A7792_PD_CA15_CPU0>; |
| next-level-cache = <&L2_CA15>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <1>; |
| clock-frequency = <1000000000>; |
| power-domains = <&sysc R8A7792_PD_CA15_CPU1>; |
| next-level-cache = <&L2_CA15>; |
| }; |
| |
| L2_CA15: cache-controller@0 { |
| compatible = "cache"; |
| reg = <0>; |
| cache-unified; |
| cache-level = <2>; |
| power-domains = <&sysc R8A7792_PD_CA15_SCU>; |
| }; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| interrupt-parent = <&gic>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| apmu@e6152000 { |
| compatible = "renesas,r8a7792-apmu", "renesas,apmu"; |
| reg = <0 0xe6152000 0 0x188>; |
| cpus = <&cpu0 &cpu1>; |
| }; |
| |
| gic: interrupt-controller@f1001000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0 0xf1001000 0 0x1000>, |
| <0 0xf1002000 0 0x1000>, |
| <0 0xf1004000 0 0x2000>, |
| <0 0xf1006000 0 0x2000>; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| irqc: interrupt-controller@e61c0000 { |
| compatible = "renesas,irqc-r8a7792", "renesas,irqc"; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| reg = <0 0xe61c0000 0 0x200>; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp4_clks R8A7792_CLK_IRQC>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| sysc: system-controller@e6180000 { |
| compatible = "renesas,r8a7792-sysc"; |
| reg = <0 0xe6180000 0 0x0200>; |
| #power-domain-cells = <1>; |
| }; |
| |
| dmac0: dma-controller@e6700000 { |
| compatible = "renesas,dmac-r8a7792", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe6700000 0 0x20000>; |
| interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14"; |
| clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| #dma-cells = <1>; |
| dma-channels = <15>; |
| }; |
| |
| dmac1: dma-controller@e6720000 { |
| compatible = "renesas,dmac-r8a7792", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe6720000 0 0x20000>; |
| interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14"; |
| clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| #dma-cells = <1>; |
| dma-channels = <15>; |
| }; |
| |
| scif0: serial@e6e60000 { |
| compatible = "renesas,scif-r8a7792", |
| "renesas,rcar-gen2-scif", "renesas,scif"; |
| reg = <0 0xe6e60000 0 64>; |
| interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x29>, <&dmac0 0x2a>, |
| <&dmac1 0x29>, <&dmac1 0x2a>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| scif1: serial@e6e68000 { |
| compatible = "renesas,scif-r8a7792", |
| "renesas,rcar-gen2-scif", "renesas,scif"; |
| reg = <0 0xe6e68000 0 64>; |
| interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, |
| <&dmac1 0x2d>, <&dmac1 0x2e>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| scif2: serial@e6e58000 { |
| compatible = "renesas,scif-r8a7792", |
| "renesas,rcar-gen2-scif", "renesas,scif"; |
| reg = <0 0xe6e58000 0 64>; |
| interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, |
| <&dmac1 0x2b>, <&dmac1 0x2c>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| scif3: serial@e6ea8000 { |
| compatible = "renesas,scif-r8a7792", |
| "renesas,rcar-gen2-scif", "renesas,scif"; |
| reg = <0 0xe6ea8000 0 64>; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x2f>, <&dmac0 0x30>, |
| <&dmac1 0x2f>, <&dmac1 0x30>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| hscif0: serial@e62c0000 { |
| compatible = "renesas,hscif-r8a7792", |
| "renesas,rcar-gen2-hscif", "renesas,hscif"; |
| reg = <0 0xe62c0000 0 96>; |
| interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x39>, <&dmac0 0x3a>, |
| <&dmac1 0x39>, <&dmac1 0x3a>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| hscif1: serial@e62c8000 { |
| compatible = "renesas,hscif-r8a7792", |
| "renesas,rcar-gen2-hscif", "renesas,hscif"; |
| reg = <0 0xe62c8000 0 96>; |
| interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, |
| <&dmac1 0x4d>, <&dmac1 0x4e>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| jpu: jpeg-codec@fe980000 { |
| compatible = "renesas,jpu-r8a7792", |
| "renesas,rcar-gen2-jpu"; |
| reg = <0 0xfe980000 0 0x10300>; |
| interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp1_clks R8A7792_CLK_JPU>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| /* Special CPG clocks */ |
| cpg_clocks: cpg_clocks@e6150000 { |
| compatible = "renesas,r8a7792-cpg-clocks", |
| "renesas,rcar-gen2-cpg-clocks"; |
| reg = <0 0xe6150000 0 0x1000>; |
| clocks = <&extal_clk>; |
| #clock-cells = <1>; |
| clock-output-names = "main", "pll0", "pll1", "pll3", |
| "lb", "qspi", "z"; |
| #power-domain-cells = <0>; |
| }; |
| |
| /* Fixed factor clocks */ |
| pll1_div2_clk: pll1_div2 { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |
| #clock-cells = <0>; |
| clock-div = <2>; |
| clock-mult = <1>; |
| }; |
| zs_clk: zs { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |
| #clock-cells = <0>; |
| clock-div = <6>; |
| clock-mult = <1>; |
| }; |
| p_clk: p { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |
| #clock-cells = <0>; |
| clock-div = <24>; |
| clock-mult = <1>; |
| }; |
| cp_clk: cp { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |
| #clock-cells = <0>; |
| clock-div = <48>; |
| clock-mult = <1>; |
| }; |
| m2_clk: m2 { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |
| #clock-cells = <0>; |
| clock-div = <8>; |
| clock-mult = <1>; |
| }; |
| |
| /* Gate clocks */ |
| mstp1_clks: mstp1_clks@e6150134 { |
| compatible = "renesas,r8a7792-mstp-clocks", |
| "renesas,cpg-mstp-clocks"; |
| reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; |
| clocks = <&m2_clk>; |
| #clock-cells = <1>; |
| clock-indices = <R8A7792_CLK_JPU>; |
| clock-output-names = "jpu"; |
| }; |
| mstp2_clks: mstp2_clks@e6150138 { |
| compatible = "renesas,r8a7792-mstp-clocks", |
| "renesas,cpg-mstp-clocks"; |
| reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; |
| clocks = <&zs_clk>, <&zs_clk>; |
| #clock-cells = <1>; |
| clock-indices = < |
| R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0 |
| >; |
| clock-output-names = "sys-dmac1", "sys-dmac0"; |
| }; |
| mstp4_clks: mstp4_clks@e6150140 { |
| compatible = "renesas,r8a7792-mstp-clocks", |
| "renesas,cpg-mstp-clocks"; |
| reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; |
| clocks = <&cp_clk>; |
| #clock-cells = <1>; |
| clock-indices = <R8A7792_CLK_IRQC>; |
| clock-output-names = "irqc"; |
| }; |
| mstp7_clks: mstp7_clks@e615014c { |
| compatible = "renesas,r8a7792-mstp-clocks", |
| "renesas,cpg-mstp-clocks"; |
| reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; |
| clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, |
| <&p_clk>, <&p_clk>; |
| #clock-cells = <1>; |
| clock-indices = < |
| R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0 |
| R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2 |
| R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0 |
| >; |
| clock-output-names = "hscif1", "hscif0", "scif3", |
| "scif2", "scif1", "scif0"; |
| }; |
| }; |
| |
| /* External root clock */ |
| extal_clk: extal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board. */ |
| clock-frequency = <0>; |
| }; |
| |
| /* External SCIF clock */ |
| scif_clk: scif { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board. */ |
| clock-frequency = <0>; |
| }; |
| }; |
