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android-kvm / linux / 00f178e15095fbcf04db00486378a6fa416a125e / . / arch / arm64 / include / asm / asm-uaccess.h
blob: 0557af834e036958e1555097beafe55042b1d7b4 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]2#ifndef __ASM_ASM_UACCESS_H
3#define __ASM_ASM_UACCESS_H
4
Will Deacon7cda23d2020-06-30 13:55:59 +0100[diff] [blame]5#include <asm/alternative-macros.h>
Mark Rutland819771c2021-10-19 17:02:13 +0100[diff] [blame]6#include <asm/asm-extable.h>
7#include <asm/assembler.h>
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]8#include <asm/kernel-pgtable.h>
Will Deaconb5195382017-12-01 17:33:48 +0000[diff] [blame]9#include <asm/mmu.h>
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]10#include <asm/sysreg.h>
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]11
12/*
13 * User access enabling/disabling macros.
14 */
15#ifdef CONFIG_ARM64_SW_TTBR0_PAN
16 .macro __uaccess_ttbr0_disable, tmp1
Steve Capper9dfe4822018-01-11 10:11:57 +0000[diff] [blame]17 mrs \tmp1, ttbr1_el1 // swapper_pg_dir
Catalin Marinas6b88a322018-01-10 13:18:30 +0000[diff] [blame]18 bic \tmp1, \tmp1, #TTBR_ASID_MASK
Joey Gouly00ef5432021-02-02 12:36:57 +0000[diff] [blame]19 sub \tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET // reserved_pg_dir
Steve Capper9dfe4822018-01-11 10:11:57 +0000[diff] [blame]20 msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]21 isb
Joey Gouly00ef5432021-02-02 12:36:57 +0000[diff] [blame]22 add \tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET
Will Deacon27a921e2017-08-10 13:58:16 +0100[diff] [blame]23 msr ttbr1_el1, \tmp1 // set reserved ASID
24 isb
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]25 .endm
26
Will Deacon27a921e2017-08-10 13:58:16 +0100[diff] [blame]27 .macro __uaccess_ttbr0_enable, tmp1, tmp2
Julien Thierry4caf8752019-02-22 09:32:50 +0000[diff] [blame]28 get_current_task \tmp1
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]29 ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1
Will Deacon27a921e2017-08-10 13:58:16 +0100[diff] [blame]30 mrs \tmp2, ttbr1_el1
31 extr \tmp2, \tmp2, \tmp1, #48
32 ror \tmp2, \tmp2, #16
33 msr ttbr1_el1, \tmp2 // set the active ASID
34 isb
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]35 msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1
36 isb
37 .endm
38
Catalin Marinas6b88a322018-01-10 13:18:30 +0000[diff] [blame]39 .macro uaccess_ttbr0_disable, tmp1, tmp2
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]40alternative_if_not ARM64_HAS_PAN
Catalin Marinas6b88a322018-01-10 13:18:30 +0000[diff] [blame]41 save_and_disable_irq \tmp2 // avoid preemption
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]42 __uaccess_ttbr0_disable \tmp1
Catalin Marinas6b88a322018-01-10 13:18:30 +0000[diff] [blame]43 restore_irq \tmp2
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]44alternative_else_nop_endif
45 .endm
46
Will Deacon27a921e2017-08-10 13:58:16 +0100[diff] [blame]47 .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]48alternative_if_not ARM64_HAS_PAN
Will Deacon27a921e2017-08-10 13:58:16 +0100[diff] [blame]49 save_and_disable_irq \tmp3 // avoid preemption
50 __uaccess_ttbr0_enable \tmp1, \tmp2
51 restore_irq \tmp3
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]52alternative_else_nop_endif
53 .endm
54#else
Catalin Marinas6b88a322018-01-10 13:18:30 +0000[diff] [blame]55 .macro uaccess_ttbr0_disable, tmp1, tmp2
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]56 .endm
57
Will Deacon27a921e2017-08-10 13:58:16 +0100[diff] [blame]58 .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]59 .endm
60#endif
61
Mark Rutland819771c2021-10-19 17:02:13 +0100[diff] [blame]62#define USER(l, x...) \
639999: x; \
64 _asm_extable 9999b, l
65
Mark Rutlande2a21902020-10-26 13:31:47 +0000[diff] [blame]66/*
Mark Rutlandfc703d82020-12-02 13:15:53 +0000[diff] [blame]67 * Generate the assembly for LDTR/STTR with exception table entries.
Mark Rutlande2a21902020-10-26 13:31:47 +0000[diff] [blame]68 * This is complicated as there is no post-increment or pair versions of the
69 * unprivileged instructions, and USER() only works for single instructions.
70 */
Mark Rutland7b90dc42020-12-02 13:15:54 +0000[diff] [blame]71 .macro user_ldp l, reg1, reg2, addr, post_inc
Mark Rutlandfc703d82020-12-02 13:15:53 +0000[diff] [blame]728888: ldtr \reg1, [\addr];
738889: ldtr \reg2, [\addr, #8];
74 add \addr, \addr, \post_inc;
Mark Rutlande2a21902020-10-26 13:31:47 +0000[diff] [blame]75
76 _asm_extable 8888b,\l;
77 _asm_extable 8889b,\l;
78 .endm
79
Mark Rutland7b90dc42020-12-02 13:15:54 +0000[diff] [blame]80 .macro user_stp l, reg1, reg2, addr, post_inc
Mark Rutlandfc703d82020-12-02 13:15:53 +0000[diff] [blame]818888: sttr \reg1, [\addr];
828889: sttr \reg2, [\addr, #8];
83 add \addr, \addr, \post_inc;
Mark Rutlande2a21902020-10-26 13:31:47 +0000[diff] [blame]84
85 _asm_extable 8888b,\l;
86 _asm_extable 8889b,\l;
87 .endm
88
Mark Rutland7b90dc42020-12-02 13:15:54 +0000[diff] [blame]89 .macro user_ldst l, inst, reg, addr, post_inc
908888: \inst \reg, [\addr];
Mark Rutlandfc703d82020-12-02 13:15:53 +0000[diff] [blame]91 add \addr, \addr, \post_inc;
Mark Rutlande2a21902020-10-26 13:31:47 +0000[diff] [blame]92
93 _asm_extable 8888b,\l;
94 .endm
Al Virob4b86642016-12-26 04:10:19 -0500[diff] [blame]95#endif