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Loc Ho938cc3a2013-06-26 11:56:11 -06001Device Tree Clock bindings for APM X-Gene
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-device-clock" - for a X-Gene device clock
12
13Required properties for SoC or PCP PLL clocks:
14- reg : shall be the physical PLL register address for the pll clock.
15- clocks : shall be the input parent clock phandle for the clock. This should
16 be the reference clock.
17- #clock-cells : shall be set to 1.
18- clock-output-names : shall be the name of the PLL referenced by derive
19 clock.
20Optional properties for PLL clocks:
21- clock-names : shall be the name of the PLL. If missing, use the device name.
22
23Required properties for device clocks:
24- reg : shall be a list of address and length pairs describing the CSR
25 reset and/or the divider. Either may be omitted, but at least
26 one must be present.
27 - reg-names : shall be a string list describing the reg resource. This
28 may include "csr-reg" and/or "div-reg". If this property
29 is not present, the reg property is assumed to describe
30 only "csr-reg".
31- clocks : shall be the input parent clock phandle for the clock.
32- #clock-cells : shall be set to 1.
33- clock-output-names : shall be the name of the device referenced.
34Optional properties for device clocks:
35- clock-names : shall be the name of the device clock. If missing, use the
36 device name.
37- csr-offset : Offset to the CSR reset register from the reset address base.
38 Default is 0.
39- csr-mask : CSR reset mask bit. Default is 0xF.
40- enable-offset : Offset to the enable register from the reset address base.
41 Default is 0x8.
42- enable-mask : CSR enable mask bit. Default is 0xF.
43- divider-offset : Offset to the divider CSR register from the divider base.
44 Default is 0x0.
45- divider-width : Width of the divider register. Default is 0.
46- divider-shift : Bit shift of the divider register. Default is 0.
47
48For example:
49
50 pcppll: pcppll@17000100 {
51 compatible = "apm,xgene-pcppll-clock";
52 #clock-cells = <1>;
53 clocks = <&refclk 0>;
54 clock-names = "pcppll";
55 reg = <0x0 0x17000100 0x0 0x1000>;
56 clock-output-names = "pcppll";
57 type = <0>;
58 };
59
60 socpll: socpll@17000120 {
61 compatible = "apm,xgene-socpll-clock";
62 #clock-cells = <1>;
63 clocks = <&refclk 0>;
64 clock-names = "socpll";
65 reg = <0x0 0x17000120 0x0 0x1000>;
66 clock-output-names = "socpll";
67 type = <1>;
68 };
69
70 qmlclk: qmlclk {
71 compatible = "apm,xgene-device-clock";
72 #clock-cells = <1>;
73 clocks = <&socplldiv2 0>;
74 clock-names = "qmlclk";
75 reg = <0x0 0x1703C000 0x0 0x1000>;
76 reg-name = "csr-reg";
77 clock-output-names = "qmlclk";
78 };
79
80 ethclk: ethclk {
81 compatible = "apm,xgene-device-clock";
82 #clock-cells = <1>;
83 clocks = <&socplldiv2 0>;
84 clock-names = "ethclk";
85 reg = <0x0 0x17000000 0x0 0x1000>;
86 reg-names = "div-reg";
87 divider-offset = <0x238>;
88 divider-width = <0x9>;
89 divider-shift = <0x0>;
90 clock-output-names = "ethclk";
91 };
92
93 apbclk: apbclk {
94 compatible = "apm,xgene-device-clock";
95 #clock-cells = <1>;
96 clocks = <&ahbclk 0>;
97 clock-names = "apbclk";
98 reg = <0x0 0x1F2AC000 0x0 0x1000
99 0x0 0x1F2AC000 0x0 0x1000>;
100 reg-names = "csr-reg", "div-reg";
101 csr-offset = <0x0>;
102 csr-mask = <0x200>;
103 enable-offset = <0x8>;
104 enable-mask = <0x200>;
105 divider-offset = <0x10>;
106 divider-width = <0x2>;
107 divider-shift = <0x0>;
108 flags = <0x8>;
109 clock-output-names = "apbclk";
110 };
111