blob: 7c0b03f67b056d32ecd73d774f71d158638b5e9a [file] [log] [blame]
Shawn Guo69c31b72011-09-06 14:59:40 +08001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <linux/smp.h>
Rob Herring520f7bd2012-12-27 13:10:24 -060015#include <linux/irqchip/arm-gic.h>
Shawn Guo69c31b72011-09-06 14:59:40 +080016#include <asm/page.h>
17#include <asm/smp_scu.h>
Shawn Guo69c31b72011-09-06 14:59:40 +080018#include <asm/mach/map.h>
Shawn Guo69c31b72011-09-06 14:59:40 +080019
Shawn Guoe3372472012-09-13 21:01:00 +080020#include "common.h"
Shawn Guo50f2de62012-09-14 14:14:45 +080021#include "hardware.h"
Shawn Guoe3372472012-09-13 21:01:00 +080022
Shawn Guoe5f9dec2012-12-04 22:55:15 +080023#define SCU_STANDBY_ENABLE (1 << 5)
24
Shawn Guo69c31b72011-09-06 14:59:40 +080025static void __iomem *scu_base;
26
27static struct map_desc scu_io_desc __initdata = {
28 /* .virtual and .pfn are run-time assigned */
29 .length = SZ_4K,
30 .type = MT_DEVICE,
31};
32
33void __init imx_scu_map_io(void)
34{
35 unsigned long base;
36
37 /* Get SCU base */
38 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
39
40 scu_io_desc.virtual = IMX_IO_P2V(base);
41 scu_io_desc.pfn = __phys_to_pfn(base);
42 iotable_init(&scu_io_desc, 1);
43
44 scu_base = IMX_IO_ADDRESS(base);
45}
46
Shawn Guoe5f9dec2012-12-04 22:55:15 +080047void imx_scu_standby_enable(void)
48{
49 u32 val = readl_relaxed(scu_base);
50
51 val |= SCU_STANDBY_ENABLE;
52 writel_relaxed(val, scu_base);
53}
54
Marc Zyngiere4f2d972011-09-08 13:15:22 +010055static void __cpuinit imx_secondary_init(unsigned int cpu)
Shawn Guo69c31b72011-09-06 14:59:40 +080056{
57 /*
58 * if any interrupts are already enabled for the primary
59 * core (e.g. timer irq), then they will not have been enabled
60 * for us: do so
61 */
62 gic_secondary_init(0);
63}
64
Marc Zyngiere4f2d972011-09-08 13:15:22 +010065static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
Shawn Guo69c31b72011-09-06 14:59:40 +080066{
67 imx_set_cpu_jump(cpu, v7_secondary_startup);
68 imx_enable_cpu(cpu, true);
69 return 0;
70}
71
72/*
73 * Initialise the CPU possible map early - this describes the CPUs
74 * which may be present or become present in the system.
75 */
Marc Zyngiere4f2d972011-09-08 13:15:22 +010076static void __init imx_smp_init_cpus(void)
Shawn Guo69c31b72011-09-06 14:59:40 +080077{
78 int i, ncores;
79
80 ncores = scu_get_core_count(scu_base);
81
82 for (i = 0; i < ncores; i++)
83 set_cpu_possible(i, true);
Shawn Guo69c31b72011-09-06 14:59:40 +080084}
85
86void imx_smp_prepare(void)
87{
88 scu_enable(scu_base);
89}
90
Marc Zyngiere4f2d972011-09-08 13:15:22 +010091static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
Shawn Guo69c31b72011-09-06 14:59:40 +080092{
93 imx_smp_prepare();
94}
Marc Zyngiere4f2d972011-09-08 13:15:22 +010095
96struct smp_operations imx_smp_ops __initdata = {
97 .smp_init_cpus = imx_smp_init_cpus,
98 .smp_prepare_cpus = imx_smp_prepare_cpus,
99 .smp_secondary_init = imx_secondary_init,
100 .smp_boot_secondary = imx_boot_secondary,
101#ifdef CONFIG_HOTPLUG_CPU
102 .cpu_die = imx_cpu_die,
Shawn Guo83757662013-01-14 14:08:50 +0800103 .cpu_kill = imx_cpu_kill,
Marc Zyngiere4f2d972011-09-08 13:15:22 +0100104#endif
105};