| Sudeep Dutt | 9ad8b64 | 2015-04-29 05:32:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Intel MIC Platform Software Stack (MPSS) |
| 3 | * |
| 4 | * This file is provided under a dual BSD/GPLv2 license. When using or |
| 5 | * redistributing this file, you may do so under either license. |
| 6 | * |
| 7 | * GPL LICENSE SUMMARY |
| 8 | * |
| 9 | * Copyright(c) 2014 Intel Corporation. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of version 2 of the GNU General Public License as |
| 13 | * published by the Free Software Foundation. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, but |
| 16 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 18 | * General Public License for more details. |
| 19 | * |
| 20 | * BSD LICENSE |
| 21 | * |
| 22 | * Copyright(c) 2014 Intel Corporation. |
| 23 | * |
| 24 | * Redistribution and use in source and binary forms, with or without |
| 25 | * modification, are permitted provided that the following conditions |
| 26 | * are met: |
| 27 | * |
| 28 | * * Redistributions of source code must retain the above copyright |
| 29 | * notice, this list of conditions and the following disclaimer. |
| 30 | * * Redistributions in binary form must reproduce the above copyright |
| 31 | * notice, this list of conditions and the following disclaimer in |
| 32 | * the documentation and/or other materials provided with the |
| 33 | * distribution. |
| 34 | * * Neither the name of Intel Corporation nor the names of its |
| 35 | * contributors may be used to endorse or promote products derived |
| 36 | * from this software without specific prior written permission. |
| 37 | * |
| 38 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 39 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 40 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 41 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 42 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 43 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 44 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 45 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 46 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 47 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 48 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 49 | * |
| 50 | * Intel SCIF driver. |
| 51 | */ |
| 52 | #ifndef SCIF_RB_H |
| 53 | #define SCIF_RB_H |
| 54 | /* |
| 55 | * This file describes a general purpose, byte based ring buffer. Writers to the |
| 56 | * ring buffer need to synchronize using a lock. The same is true for readers, |
| 57 | * although in practice, the ring buffer has a single reader. It is lockless |
| 58 | * between producer and consumer so it can handle being used across the PCIe |
| 59 | * bus. The ring buffer ensures that there are no reads across the PCIe bus for |
| 60 | * performance reasons. Two of these are used to form a single bidirectional |
| 61 | * queue-pair across PCIe. |
| 62 | */ |
| 63 | /* |
| 64 | * struct scif_rb - SCIF Ring Buffer |
| 65 | * |
| 66 | * @rb_base: The base of the memory used for storing RB messages |
| 67 | * @read_ptr: Pointer to the read offset |
| 68 | * @write_ptr: Pointer to the write offset |
| 69 | * @size: Size of the memory in rb_base |
| 70 | * @current_read_offset: Cached read offset for performance |
| 71 | * @current_write_offset: Cached write offset for performance |
| 72 | */ |
| 73 | struct scif_rb { |
| 74 | void *rb_base; |
| 75 | u32 *read_ptr; |
| 76 | u32 *write_ptr; |
| 77 | u32 size; |
| 78 | u32 current_read_offset; |
| 79 | u32 current_write_offset; |
| 80 | }; |
| 81 | |
| 82 | /* methods used by both */ |
| 83 | void scif_rb_init(struct scif_rb *rb, u32 *read_ptr, u32 *write_ptr, |
| 84 | void *rb_base, u8 size); |
| 85 | /* writer only methods */ |
| 86 | /* write a new command, then scif_rb_commit() */ |
| 87 | int scif_rb_write(struct scif_rb *rb, void *msg, u32 size); |
| 88 | /* after write(), then scif_rb_commit() */ |
| 89 | void scif_rb_commit(struct scif_rb *rb); |
| 90 | /* query space available for writing to a RB. */ |
| 91 | u32 scif_rb_space(struct scif_rb *rb); |
| 92 | |
| 93 | /* reader only methods */ |
| 94 | /* read a new message from the ring buffer of size bytes */ |
| 95 | u32 scif_rb_get_next(struct scif_rb *rb, void *msg, u32 size); |
| 96 | /* update the read pointer so that the space can be reused */ |
| 97 | void scif_rb_update_read_ptr(struct scif_rb *rb); |
| 98 | /* count the number of bytes that can be read */ |
| 99 | u32 scif_rb_count(struct scif_rb *rb, u32 size); |
| 100 | #endif |
