Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1 | /* |
| 2 | * EMIF driver |
| 3 | * |
| 4 | * Copyright (C) 2012 Texas Instruments, Inc. |
| 5 | * |
| 6 | * Aneesh V <aneesh@ti.com> |
| 7 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
Thierry Reding | 06303c2 | 2013-01-21 11:09:08 +0100 | [diff] [blame] | 13 | #include <linux/err.h> |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 14 | #include <linux/kernel.h> |
| 15 | #include <linux/reboot.h> |
| 16 | #include <linux/platform_data/emif_plat.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/device.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/slab.h> |
Aneesh V | e6b42eb | 2012-08-17 14:05:15 +0530 | [diff] [blame] | 22 | #include <linux/of.h> |
Aneesh V | aac10aa | 2012-04-27 17:54:09 +0530 | [diff] [blame] | 23 | #include <linux/debugfs.h> |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 24 | #include <linux/seq_file.h> |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/list.h> |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 27 | #include <linux/spinlock.h> |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 28 | #include <memory/jedec_ddr.h> |
| 29 | #include "emif.h" |
Aneesh V | e6b42eb | 2012-08-17 14:05:15 +0530 | [diff] [blame] | 30 | #include "of_memory.h" |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 31 | |
| 32 | /** |
| 33 | * struct emif_data - Per device static data for driver's use |
| 34 | * @duplicate: Whether the DDR devices attached to this EMIF |
| 35 | * instance are exactly same as that on EMIF1. In |
| 36 | * this case we can save some memory and processing |
| 37 | * @temperature_level: Maximum temperature of LPDDR2 devices attached |
| 38 | * to this EMIF - read from MR4 register. If there |
| 39 | * are two devices attached to this EMIF, this |
| 40 | * value is the maximum of the two temperature |
| 41 | * levels. |
| 42 | * @node: node in the device list |
| 43 | * @base: base address of memory-mapped IO registers. |
| 44 | * @dev: device pointer. |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 45 | * @addressing table with addressing information from the spec |
| 46 | * @regs_cache: An array of 'struct emif_regs' that stores |
| 47 | * calculated register values for different |
| 48 | * frequencies, to avoid re-calculating them on |
| 49 | * each DVFS transition. |
| 50 | * @curr_regs: The set of register values used in the last |
| 51 | * frequency change (i.e. corresponding to the |
| 52 | * frequency in effect at the moment) |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 53 | * @plat_data: Pointer to saved platform data. |
Aneesh V | aac10aa | 2012-04-27 17:54:09 +0530 | [diff] [blame] | 54 | * @debugfs_root: dentry to the root folder for EMIF in debugfs |
Aneesh V | e6b42eb | 2012-08-17 14:05:15 +0530 | [diff] [blame] | 55 | * @np_ddr: Pointer to ddr device tree node |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 56 | */ |
| 57 | struct emif_data { |
| 58 | u8 duplicate; |
| 59 | u8 temperature_level; |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 60 | u8 lpmode; |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 61 | struct list_head node; |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 62 | unsigned long irq_state; |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 63 | void __iomem *base; |
| 64 | struct device *dev; |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 65 | const struct lpddr2_addressing *addressing; |
| 66 | struct emif_regs *regs_cache[EMIF_MAX_NUM_FREQUENCIES]; |
| 67 | struct emif_regs *curr_regs; |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 68 | struct emif_platform_data *plat_data; |
Aneesh V | aac10aa | 2012-04-27 17:54:09 +0530 | [diff] [blame] | 69 | struct dentry *debugfs_root; |
Aneesh V | e6b42eb | 2012-08-17 14:05:15 +0530 | [diff] [blame] | 70 | struct device_node *np_ddr; |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 71 | }; |
| 72 | |
| 73 | static struct emif_data *emif1; |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 74 | static spinlock_t emif_lock; |
| 75 | static unsigned long irq_state; |
| 76 | static u32 t_ck; /* DDR clock period in ps */ |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 77 | static LIST_HEAD(device_list); |
| 78 | |
Axel Lin | e5445ee | 2012-09-25 11:54:36 +0800 | [diff] [blame] | 79 | #ifdef CONFIG_DEBUG_FS |
Aneesh V | aac10aa | 2012-04-27 17:54:09 +0530 | [diff] [blame] | 80 | static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif, |
| 81 | struct emif_regs *regs) |
| 82 | { |
| 83 | u32 type = emif->plat_data->device_info->type; |
| 84 | u32 ip_rev = emif->plat_data->ip_rev; |
| 85 | |
| 86 | seq_printf(s, "EMIF register cache dump for %dMHz\n", |
| 87 | regs->freq/1000000); |
| 88 | |
| 89 | seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw); |
| 90 | seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw); |
| 91 | seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw); |
| 92 | seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw); |
| 93 | |
| 94 | if (ip_rev == EMIF_4D) { |
| 95 | seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n", |
| 96 | regs->read_idle_ctrl_shdw_normal); |
| 97 | seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n", |
| 98 | regs->read_idle_ctrl_shdw_volt_ramp); |
| 99 | } else if (ip_rev == EMIF_4D5) { |
| 100 | seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n", |
| 101 | regs->dll_calib_ctrl_shdw_normal); |
| 102 | seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n", |
| 103 | regs->dll_calib_ctrl_shdw_volt_ramp); |
| 104 | } |
| 105 | |
| 106 | if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) { |
| 107 | seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n", |
| 108 | regs->ref_ctrl_shdw_derated); |
| 109 | seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n", |
| 110 | regs->sdram_tim1_shdw_derated); |
| 111 | seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n", |
| 112 | regs->sdram_tim3_shdw_derated); |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | static int emif_regdump_show(struct seq_file *s, void *unused) |
| 117 | { |
| 118 | struct emif_data *emif = s->private; |
| 119 | struct emif_regs **regs_cache; |
| 120 | int i; |
| 121 | |
| 122 | if (emif->duplicate) |
| 123 | regs_cache = emif1->regs_cache; |
| 124 | else |
| 125 | regs_cache = emif->regs_cache; |
| 126 | |
| 127 | for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) { |
| 128 | do_emif_regdump_show(s, emif, regs_cache[i]); |
| 129 | seq_printf(s, "\n"); |
| 130 | } |
| 131 | |
| 132 | return 0; |
| 133 | } |
| 134 | |
| 135 | static int emif_regdump_open(struct inode *inode, struct file *file) |
| 136 | { |
| 137 | return single_open(file, emif_regdump_show, inode->i_private); |
| 138 | } |
| 139 | |
| 140 | static const struct file_operations emif_regdump_fops = { |
| 141 | .open = emif_regdump_open, |
| 142 | .read = seq_read, |
| 143 | .release = single_release, |
| 144 | }; |
| 145 | |
| 146 | static int emif_mr4_show(struct seq_file *s, void *unused) |
| 147 | { |
| 148 | struct emif_data *emif = s->private; |
| 149 | |
| 150 | seq_printf(s, "MR4=%d\n", emif->temperature_level); |
| 151 | return 0; |
| 152 | } |
| 153 | |
| 154 | static int emif_mr4_open(struct inode *inode, struct file *file) |
| 155 | { |
| 156 | return single_open(file, emif_mr4_show, inode->i_private); |
| 157 | } |
| 158 | |
| 159 | static const struct file_operations emif_mr4_fops = { |
| 160 | .open = emif_mr4_open, |
| 161 | .read = seq_read, |
| 162 | .release = single_release, |
| 163 | }; |
| 164 | |
| 165 | static int __init_or_module emif_debugfs_init(struct emif_data *emif) |
| 166 | { |
| 167 | struct dentry *dentry; |
| 168 | int ret; |
| 169 | |
| 170 | dentry = debugfs_create_dir(dev_name(emif->dev), NULL); |
Axel Lin | e5445ee | 2012-09-25 11:54:36 +0800 | [diff] [blame] | 171 | if (!dentry) { |
| 172 | ret = -ENOMEM; |
Aneesh V | aac10aa | 2012-04-27 17:54:09 +0530 | [diff] [blame] | 173 | goto err0; |
| 174 | } |
| 175 | emif->debugfs_root = dentry; |
| 176 | |
| 177 | dentry = debugfs_create_file("regcache_dump", S_IRUGO, |
| 178 | emif->debugfs_root, emif, &emif_regdump_fops); |
Axel Lin | e5445ee | 2012-09-25 11:54:36 +0800 | [diff] [blame] | 179 | if (!dentry) { |
| 180 | ret = -ENOMEM; |
Aneesh V | aac10aa | 2012-04-27 17:54:09 +0530 | [diff] [blame] | 181 | goto err1; |
| 182 | } |
| 183 | |
| 184 | dentry = debugfs_create_file("mr4", S_IRUGO, |
| 185 | emif->debugfs_root, emif, &emif_mr4_fops); |
Axel Lin | e5445ee | 2012-09-25 11:54:36 +0800 | [diff] [blame] | 186 | if (!dentry) { |
| 187 | ret = -ENOMEM; |
Aneesh V | aac10aa | 2012-04-27 17:54:09 +0530 | [diff] [blame] | 188 | goto err1; |
| 189 | } |
| 190 | |
| 191 | return 0; |
| 192 | err1: |
| 193 | debugfs_remove_recursive(emif->debugfs_root); |
| 194 | err0: |
| 195 | return ret; |
| 196 | } |
| 197 | |
| 198 | static void __exit emif_debugfs_exit(struct emif_data *emif) |
| 199 | { |
| 200 | debugfs_remove_recursive(emif->debugfs_root); |
| 201 | emif->debugfs_root = NULL; |
| 202 | } |
Axel Lin | e5445ee | 2012-09-25 11:54:36 +0800 | [diff] [blame] | 203 | #else |
| 204 | static inline int __init_or_module emif_debugfs_init(struct emif_data *emif) |
| 205 | { |
| 206 | return 0; |
| 207 | } |
| 208 | |
| 209 | static inline void __exit emif_debugfs_exit(struct emif_data *emif) |
| 210 | { |
| 211 | } |
| 212 | #endif |
Aneesh V | aac10aa | 2012-04-27 17:54:09 +0530 | [diff] [blame] | 213 | |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 214 | /* |
| 215 | * Calculate the period of DDR clock from frequency value |
| 216 | */ |
| 217 | static void set_ddr_clk_period(u32 freq) |
| 218 | { |
| 219 | /* Divide 10^12 by frequency to get period in ps */ |
| 220 | t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq); |
| 221 | } |
| 222 | |
| 223 | /* |
Aneesh V | 98231c4f | 2012-04-27 17:54:08 +0530 | [diff] [blame] | 224 | * Get bus width used by EMIF. Note that this may be different from the |
| 225 | * bus width of the DDR devices used. For instance two 16-bit DDR devices |
| 226 | * may be connected to a given CS of EMIF. In this case bus width as far |
| 227 | * as EMIF is concerned is 32, where as the DDR bus width is 16 bits. |
| 228 | */ |
| 229 | static u32 get_emif_bus_width(struct emif_data *emif) |
| 230 | { |
| 231 | u32 width; |
| 232 | void __iomem *base = emif->base; |
| 233 | |
| 234 | width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK) |
| 235 | >> NARROW_MODE_SHIFT; |
| 236 | width = width == 0 ? 32 : 16; |
| 237 | |
| 238 | return width; |
| 239 | } |
| 240 | |
| 241 | /* |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 242 | * Get the CL from SDRAM_CONFIG register |
| 243 | */ |
| 244 | static u32 get_cl(struct emif_data *emif) |
| 245 | { |
| 246 | u32 cl; |
| 247 | void __iomem *base = emif->base; |
| 248 | |
| 249 | cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT; |
| 250 | |
| 251 | return cl; |
| 252 | } |
| 253 | |
| 254 | static void set_lpmode(struct emif_data *emif, u8 lpmode) |
| 255 | { |
| 256 | u32 temp; |
| 257 | void __iomem *base = emif->base; |
| 258 | |
| 259 | temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL); |
| 260 | temp &= ~LP_MODE_MASK; |
| 261 | temp |= (lpmode << LP_MODE_SHIFT); |
| 262 | writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL); |
| 263 | } |
| 264 | |
| 265 | static void do_freq_update(void) |
| 266 | { |
| 267 | struct emif_data *emif; |
| 268 | |
| 269 | /* |
| 270 | * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE |
| 271 | * |
| 272 | * i728 DESCRIPTION: |
| 273 | * The EMIF automatically puts the SDRAM into self-refresh mode |
| 274 | * after the EMIF has not performed accesses during |
| 275 | * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles |
| 276 | * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set |
| 277 | * to 0x2. If during a small window the following three events |
| 278 | * occur: |
| 279 | * - The SR_TIMING counter expires |
| 280 | * - And frequency change is requested |
| 281 | * - And OCP access is requested |
| 282 | * Then it causes instable clock on the DDR interface. |
| 283 | * |
| 284 | * WORKAROUND |
| 285 | * To avoid the occurrence of the three events, the workaround |
| 286 | * is to disable the self-refresh when requesting a frequency |
| 287 | * change. Before requesting a frequency change the software must |
| 288 | * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the |
| 289 | * frequency change has been done, the software can reprogram |
| 290 | * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2 |
| 291 | */ |
| 292 | list_for_each_entry(emif, &device_list, node) { |
| 293 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) |
| 294 | set_lpmode(emif, EMIF_LP_MODE_DISABLE); |
| 295 | } |
| 296 | |
| 297 | /* |
| 298 | * TODO: Do FREQ_UPDATE here when an API |
| 299 | * is available for this as part of the new |
| 300 | * clock framework |
| 301 | */ |
| 302 | |
| 303 | list_for_each_entry(emif, &device_list, node) { |
| 304 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) |
| 305 | set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH); |
| 306 | } |
| 307 | } |
| 308 | |
| 309 | /* Find addressing table entry based on the device's type and density */ |
| 310 | static const struct lpddr2_addressing *get_addressing_table( |
| 311 | const struct ddr_device_info *device_info) |
| 312 | { |
| 313 | u32 index, type, density; |
| 314 | |
| 315 | type = device_info->type; |
| 316 | density = device_info->density; |
| 317 | |
| 318 | switch (type) { |
| 319 | case DDR_TYPE_LPDDR2_S4: |
| 320 | index = density - 1; |
| 321 | break; |
| 322 | case DDR_TYPE_LPDDR2_S2: |
| 323 | switch (density) { |
| 324 | case DDR_DENSITY_1Gb: |
| 325 | case DDR_DENSITY_2Gb: |
| 326 | index = density + 3; |
| 327 | break; |
| 328 | default: |
| 329 | index = density - 1; |
| 330 | } |
| 331 | break; |
| 332 | default: |
| 333 | return NULL; |
| 334 | } |
| 335 | |
| 336 | return &lpddr2_jedec_addressing_table[index]; |
| 337 | } |
| 338 | |
| 339 | /* |
| 340 | * Find the the right timing table from the array of timing |
| 341 | * tables of the device using DDR clock frequency |
| 342 | */ |
| 343 | static const struct lpddr2_timings *get_timings_table(struct emif_data *emif, |
| 344 | u32 freq) |
| 345 | { |
| 346 | u32 i, min, max, freq_nearest; |
| 347 | const struct lpddr2_timings *timings = NULL; |
| 348 | const struct lpddr2_timings *timings_arr = emif->plat_data->timings; |
| 349 | struct device *dev = emif->dev; |
| 350 | |
| 351 | /* Start with a very high frequency - 1GHz */ |
| 352 | freq_nearest = 1000000000; |
| 353 | |
| 354 | /* |
| 355 | * Find the timings table such that: |
| 356 | * 1. the frequency range covers the required frequency(safe) AND |
| 357 | * 2. the max_freq is closest to the required frequency(optimal) |
| 358 | */ |
| 359 | for (i = 0; i < emif->plat_data->timings_arr_size; i++) { |
| 360 | max = timings_arr[i].max_freq; |
| 361 | min = timings_arr[i].min_freq; |
| 362 | if ((freq >= min) && (freq <= max) && (max < freq_nearest)) { |
| 363 | freq_nearest = max; |
| 364 | timings = &timings_arr[i]; |
| 365 | } |
| 366 | } |
| 367 | |
| 368 | if (!timings) |
| 369 | dev_err(dev, "%s: couldn't find timings for - %dHz\n", |
| 370 | __func__, freq); |
| 371 | |
| 372 | dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n", |
| 373 | __func__, freq, freq_nearest); |
| 374 | |
| 375 | return timings; |
| 376 | } |
| 377 | |
| 378 | static u32 get_sdram_ref_ctrl_shdw(u32 freq, |
| 379 | const struct lpddr2_addressing *addressing) |
| 380 | { |
| 381 | u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi; |
| 382 | |
| 383 | /* Scale down frequency and t_refi to avoid overflow */ |
| 384 | freq_khz = freq / 1000; |
| 385 | t_refi = addressing->tREFI_ns / 100; |
| 386 | |
| 387 | /* |
| 388 | * refresh rate to be set is 'tREFI(in us) * freq in MHz |
| 389 | * division by 10000 to account for change in units |
| 390 | */ |
| 391 | val = t_refi * freq_khz / 10000; |
| 392 | ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT; |
| 393 | |
| 394 | return ref_ctrl_shdw; |
| 395 | } |
| 396 | |
| 397 | static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings, |
| 398 | const struct lpddr2_min_tck *min_tck, |
| 399 | const struct lpddr2_addressing *addressing) |
| 400 | { |
| 401 | u32 tim1 = 0, val = 0; |
| 402 | |
| 403 | val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; |
| 404 | tim1 |= val << T_WTR_SHIFT; |
| 405 | |
| 406 | if (addressing->num_banks == B8) |
| 407 | val = DIV_ROUND_UP(timings->tFAW, t_ck*4); |
| 408 | else |
| 409 | val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck)); |
| 410 | tim1 |= (val - 1) << T_RRD_SHIFT; |
| 411 | |
| 412 | val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1; |
| 413 | tim1 |= val << T_RC_SHIFT; |
| 414 | |
| 415 | val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck)); |
| 416 | tim1 |= (val - 1) << T_RAS_SHIFT; |
| 417 | |
| 418 | val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; |
| 419 | tim1 |= val << T_WR_SHIFT; |
| 420 | |
| 421 | val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1; |
| 422 | tim1 |= val << T_RCD_SHIFT; |
| 423 | |
| 424 | val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1; |
| 425 | tim1 |= val << T_RP_SHIFT; |
| 426 | |
| 427 | return tim1; |
| 428 | } |
| 429 | |
| 430 | static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings, |
| 431 | const struct lpddr2_min_tck *min_tck, |
| 432 | const struct lpddr2_addressing *addressing) |
| 433 | { |
| 434 | u32 tim1 = 0, val = 0; |
| 435 | |
| 436 | val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; |
| 437 | tim1 = val << T_WTR_SHIFT; |
| 438 | |
| 439 | /* |
| 440 | * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps |
| 441 | * to tFAW for de-rating |
| 442 | */ |
| 443 | if (addressing->num_banks == B8) { |
| 444 | val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1; |
| 445 | } else { |
| 446 | val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck); |
| 447 | val = max(min_tck->tRRD, val) - 1; |
| 448 | } |
| 449 | tim1 |= val << T_RRD_SHIFT; |
| 450 | |
| 451 | val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck); |
| 452 | tim1 |= (val - 1) << T_RC_SHIFT; |
| 453 | |
| 454 | val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck); |
| 455 | val = max(min_tck->tRASmin, val) - 1; |
| 456 | tim1 |= val << T_RAS_SHIFT; |
| 457 | |
| 458 | val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; |
| 459 | tim1 |= val << T_WR_SHIFT; |
| 460 | |
| 461 | val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck)); |
| 462 | tim1 |= (val - 1) << T_RCD_SHIFT; |
| 463 | |
| 464 | val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck)); |
| 465 | tim1 |= (val - 1) << T_RP_SHIFT; |
| 466 | |
| 467 | return tim1; |
| 468 | } |
| 469 | |
| 470 | static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings, |
| 471 | const struct lpddr2_min_tck *min_tck, |
| 472 | const struct lpddr2_addressing *addressing, |
| 473 | u32 type) |
| 474 | { |
| 475 | u32 tim2 = 0, val = 0; |
| 476 | |
| 477 | val = min_tck->tCKE - 1; |
| 478 | tim2 |= val << T_CKE_SHIFT; |
| 479 | |
| 480 | val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1; |
| 481 | tim2 |= val << T_RTP_SHIFT; |
| 482 | |
| 483 | /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */ |
| 484 | val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1; |
| 485 | tim2 |= val << T_XSNR_SHIFT; |
| 486 | |
| 487 | /* XSRD same as XSNR for LPDDR2 */ |
| 488 | tim2 |= val << T_XSRD_SHIFT; |
| 489 | |
| 490 | val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1; |
| 491 | tim2 |= val << T_XP_SHIFT; |
| 492 | |
| 493 | return tim2; |
| 494 | } |
| 495 | |
| 496 | static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings, |
| 497 | const struct lpddr2_min_tck *min_tck, |
| 498 | const struct lpddr2_addressing *addressing, |
| 499 | u32 type, u32 ip_rev, u32 derated) |
| 500 | { |
| 501 | u32 tim3 = 0, val = 0, t_dqsck; |
| 502 | |
| 503 | val = timings->tRAS_max_ns / addressing->tREFI_ns - 1; |
| 504 | val = val > 0xF ? 0xF : val; |
| 505 | tim3 |= val << T_RAS_MAX_SHIFT; |
| 506 | |
| 507 | val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1; |
| 508 | tim3 |= val << T_RFC_SHIFT; |
| 509 | |
| 510 | t_dqsck = (derated == EMIF_DERATED_TIMINGS) ? |
| 511 | timings->tDQSCK_max_derated : timings->tDQSCK_max; |
| 512 | if (ip_rev == EMIF_4D5) |
| 513 | val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1; |
| 514 | else |
| 515 | val = DIV_ROUND_UP(t_dqsck, t_ck) - 1; |
| 516 | |
| 517 | tim3 |= val << T_TDQSCKMAX_SHIFT; |
| 518 | |
| 519 | val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1; |
| 520 | tim3 |= val << ZQ_ZQCS_SHIFT; |
| 521 | |
| 522 | val = DIV_ROUND_UP(timings->tCKESR, t_ck); |
| 523 | val = max(min_tck->tCKESR, val) - 1; |
| 524 | tim3 |= val << T_CKESR_SHIFT; |
| 525 | |
| 526 | if (ip_rev == EMIF_4D5) { |
| 527 | tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT; |
| 528 | |
| 529 | val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1; |
| 530 | tim3 |= val << T_PDLL_UL_SHIFT; |
| 531 | } |
| 532 | |
| 533 | return tim3; |
| 534 | } |
| 535 | |
Aneesh V | 98231c4f | 2012-04-27 17:54:08 +0530 | [diff] [blame] | 536 | static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing, |
| 537 | bool cs1_used, bool cal_resistors_per_cs) |
| 538 | { |
| 539 | u32 zq = 0, val = 0; |
| 540 | |
| 541 | val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns; |
| 542 | zq |= val << ZQ_REFINTERVAL_SHIFT; |
| 543 | |
| 544 | val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1; |
| 545 | zq |= val << ZQ_ZQCL_MULT_SHIFT; |
| 546 | |
| 547 | val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1; |
| 548 | zq |= val << ZQ_ZQINIT_MULT_SHIFT; |
| 549 | |
| 550 | zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT; |
| 551 | |
| 552 | if (cal_resistors_per_cs) |
| 553 | zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT; |
| 554 | else |
| 555 | zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT; |
| 556 | |
| 557 | zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */ |
| 558 | |
| 559 | val = cs1_used ? 1 : 0; |
| 560 | zq |= val << ZQ_CS1EN_SHIFT; |
| 561 | |
| 562 | return zq; |
| 563 | } |
| 564 | |
| 565 | static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing, |
| 566 | const struct emif_custom_configs *custom_configs, bool cs1_used, |
| 567 | u32 sdram_io_width, u32 emif_bus_width) |
| 568 | { |
| 569 | u32 alert = 0, interval, devcnt; |
| 570 | |
| 571 | if (custom_configs && (custom_configs->mask & |
| 572 | EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)) |
| 573 | interval = custom_configs->temp_alert_poll_interval_ms; |
| 574 | else |
| 575 | interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS; |
| 576 | |
| 577 | interval *= 1000000; /* Convert to ns */ |
| 578 | interval /= addressing->tREFI_ns; /* Convert to refresh cycles */ |
| 579 | alert |= (interval << TA_REFINTERVAL_SHIFT); |
| 580 | |
| 581 | /* |
| 582 | * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width |
| 583 | * also to this form and subtract to get TA_DEVCNT, which is |
| 584 | * in log2(x) form. |
| 585 | */ |
| 586 | emif_bus_width = __fls(emif_bus_width) - 1; |
| 587 | devcnt = emif_bus_width - sdram_io_width; |
| 588 | alert |= devcnt << TA_DEVCNT_SHIFT; |
| 589 | |
| 590 | /* DEVWDT is in 'log2(x) - 3' form */ |
| 591 | alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT; |
| 592 | |
| 593 | alert |= 1 << TA_SFEXITEN_SHIFT; |
| 594 | alert |= 1 << TA_CS0EN_SHIFT; |
| 595 | alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT; |
| 596 | |
| 597 | return alert; |
| 598 | } |
| 599 | |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 600 | static u32 get_read_idle_ctrl_shdw(u8 volt_ramp) |
| 601 | { |
| 602 | u32 idle = 0, val = 0; |
| 603 | |
| 604 | /* |
| 605 | * Maximum value in normal conditions and increased frequency |
| 606 | * when voltage is ramping |
| 607 | */ |
| 608 | if (volt_ramp) |
| 609 | val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1; |
| 610 | else |
| 611 | val = 0x1FF; |
| 612 | |
| 613 | /* |
| 614 | * READ_IDLE_CTRL register in EMIF4D has same offset and fields |
| 615 | * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts |
| 616 | */ |
| 617 | idle |= val << DLL_CALIB_INTERVAL_SHIFT; |
| 618 | idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT; |
| 619 | |
| 620 | return idle; |
| 621 | } |
| 622 | |
| 623 | static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp) |
| 624 | { |
| 625 | u32 calib = 0, val = 0; |
| 626 | |
| 627 | if (volt_ramp == DDR_VOLTAGE_RAMPING) |
| 628 | val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1; |
| 629 | else |
| 630 | val = 0; /* Disabled when voltage is stable */ |
| 631 | |
| 632 | calib |= val << DLL_CALIB_INTERVAL_SHIFT; |
| 633 | calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT; |
| 634 | |
| 635 | return calib; |
| 636 | } |
| 637 | |
| 638 | static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings, |
| 639 | u32 freq, u8 RL) |
| 640 | { |
| 641 | u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0; |
| 642 | |
| 643 | val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1; |
| 644 | phy |= val << READ_LATENCY_SHIFT_4D; |
| 645 | |
| 646 | if (freq <= 100000000) |
| 647 | val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY; |
| 648 | else if (freq <= 200000000) |
| 649 | val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY; |
| 650 | else |
| 651 | val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY; |
| 652 | |
| 653 | phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D; |
| 654 | |
| 655 | return phy; |
| 656 | } |
| 657 | |
| 658 | static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl) |
| 659 | { |
| 660 | u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay; |
| 661 | |
| 662 | /* |
| 663 | * DLL operates at 266 MHz. If DDR frequency is near 266 MHz, |
| 664 | * half-delay is not needed else set half-delay |
| 665 | */ |
| 666 | if (freq >= 265000000 && freq < 267000000) |
| 667 | half_delay = 0; |
| 668 | else |
| 669 | half_delay = 1; |
| 670 | |
| 671 | phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5; |
| 672 | phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS, |
| 673 | t_ck) - 1) << READ_LATENCY_SHIFT_4D5); |
| 674 | |
| 675 | return phy; |
| 676 | } |
| 677 | |
| 678 | static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void) |
| 679 | { |
| 680 | u32 fifo_we_slave_ratio; |
| 681 | |
| 682 | fifo_we_slave_ratio = DIV_ROUND_CLOSEST( |
| 683 | EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); |
| 684 | |
| 685 | return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 | |
| 686 | fifo_we_slave_ratio << 22; |
| 687 | } |
| 688 | |
| 689 | static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void) |
| 690 | { |
| 691 | u32 fifo_we_slave_ratio; |
| 692 | |
| 693 | fifo_we_slave_ratio = DIV_ROUND_CLOSEST( |
| 694 | EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); |
| 695 | |
| 696 | return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 | |
| 697 | fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23; |
| 698 | } |
| 699 | |
| 700 | static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void) |
| 701 | { |
| 702 | u32 fifo_we_slave_ratio; |
| 703 | |
| 704 | fifo_we_slave_ratio = DIV_ROUND_CLOSEST( |
| 705 | EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck); |
| 706 | |
| 707 | return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 | |
| 708 | fifo_we_slave_ratio << 13; |
| 709 | } |
| 710 | |
| 711 | static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev) |
| 712 | { |
| 713 | u32 pwr_mgmt_ctrl = 0, timeout; |
| 714 | u32 lpmode = EMIF_LP_MODE_SELF_REFRESH; |
| 715 | u32 timeout_perf = EMIF_LP_MODE_TIMEOUT_PERFORMANCE; |
| 716 | u32 timeout_pwr = EMIF_LP_MODE_TIMEOUT_POWER; |
| 717 | u32 freq_threshold = EMIF_LP_MODE_FREQ_THRESHOLD; |
| 718 | |
| 719 | struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs; |
| 720 | |
| 721 | if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) { |
| 722 | lpmode = cust_cfgs->lpmode; |
| 723 | timeout_perf = cust_cfgs->lpmode_timeout_performance; |
| 724 | timeout_pwr = cust_cfgs->lpmode_timeout_power; |
| 725 | freq_threshold = cust_cfgs->lpmode_freq_threshold; |
| 726 | } |
| 727 | |
| 728 | /* Timeout based on DDR frequency */ |
| 729 | timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr; |
| 730 | |
Lokesh Vutla | 0a5f19c | 2013-03-16 11:46:41 +0530 | [diff] [blame^] | 731 | /* |
| 732 | * The value to be set in register is "log2(timeout) - 3" |
| 733 | * if timeout < 16 load 0 in register |
| 734 | * if timeout is not a power of 2, round to next highest power of 2 |
| 735 | */ |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 736 | if (timeout < 16) { |
| 737 | timeout = 0; |
| 738 | } else { |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 739 | if (timeout & (timeout - 1)) |
Lokesh Vutla | 0a5f19c | 2013-03-16 11:46:41 +0530 | [diff] [blame^] | 740 | timeout <<= 1; |
| 741 | timeout = __fls(timeout) - 3; |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 742 | } |
| 743 | |
| 744 | switch (lpmode) { |
| 745 | case EMIF_LP_MODE_CLOCK_STOP: |
| 746 | pwr_mgmt_ctrl = (timeout << CS_TIM_SHIFT) | |
| 747 | SR_TIM_MASK | PD_TIM_MASK; |
| 748 | break; |
| 749 | case EMIF_LP_MODE_SELF_REFRESH: |
| 750 | /* Workaround for errata i735 */ |
| 751 | if (timeout < 6) |
| 752 | timeout = 6; |
| 753 | |
| 754 | pwr_mgmt_ctrl = (timeout << SR_TIM_SHIFT) | |
| 755 | CS_TIM_MASK | PD_TIM_MASK; |
| 756 | break; |
| 757 | case EMIF_LP_MODE_PWR_DN: |
| 758 | pwr_mgmt_ctrl = (timeout << PD_TIM_SHIFT) | |
| 759 | CS_TIM_MASK | SR_TIM_MASK; |
| 760 | break; |
| 761 | case EMIF_LP_MODE_DISABLE: |
| 762 | default: |
| 763 | pwr_mgmt_ctrl = CS_TIM_MASK | |
| 764 | PD_TIM_MASK | SR_TIM_MASK; |
| 765 | } |
| 766 | |
| 767 | /* No CS_TIM in EMIF_4D5 */ |
| 768 | if (ip_rev == EMIF_4D5) |
| 769 | pwr_mgmt_ctrl &= ~CS_TIM_MASK; |
| 770 | |
| 771 | pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT; |
| 772 | |
| 773 | return pwr_mgmt_ctrl; |
| 774 | } |
| 775 | |
| 776 | /* |
Aneesh V | 68b4aee | 2012-04-27 17:54:07 +0530 | [diff] [blame] | 777 | * Get the temperature level of the EMIF instance: |
| 778 | * Reads the MR4 register of attached SDRAM parts to find out the temperature |
| 779 | * level. If there are two parts attached(one on each CS), then the temperature |
| 780 | * level for the EMIF instance is the higher of the two temperatures. |
| 781 | */ |
| 782 | static void get_temperature_level(struct emif_data *emif) |
| 783 | { |
| 784 | u32 temp, temperature_level; |
| 785 | void __iomem *base; |
| 786 | |
| 787 | base = emif->base; |
| 788 | |
| 789 | /* Read mode register 4 */ |
| 790 | writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG); |
| 791 | temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA); |
| 792 | temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >> |
| 793 | MR4_SDRAM_REF_RATE_SHIFT; |
| 794 | |
| 795 | if (emif->plat_data->device_info->cs1_used) { |
| 796 | writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG); |
| 797 | temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA); |
| 798 | temp = (temp & MR4_SDRAM_REF_RATE_MASK) |
| 799 | >> MR4_SDRAM_REF_RATE_SHIFT; |
| 800 | temperature_level = max(temp, temperature_level); |
| 801 | } |
| 802 | |
| 803 | /* treat everything less than nominal(3) in MR4 as nominal */ |
| 804 | if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL)) |
| 805 | temperature_level = SDRAM_TEMP_NOMINAL; |
| 806 | |
| 807 | /* if we get reserved value in MR4 persist with the existing value */ |
| 808 | if (likely(temperature_level != SDRAM_TEMP_RESERVED_4)) |
| 809 | emif->temperature_level = temperature_level; |
| 810 | } |
| 811 | |
| 812 | /* |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 813 | * Program EMIF shadow registers that are not dependent on temperature |
| 814 | * or voltage |
| 815 | */ |
| 816 | static void setup_registers(struct emif_data *emif, struct emif_regs *regs) |
| 817 | { |
| 818 | void __iomem *base = emif->base; |
| 819 | |
| 820 | writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW); |
| 821 | writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW); |
| 822 | |
| 823 | /* Settings specific for EMIF4D5 */ |
| 824 | if (emif->plat_data->ip_rev != EMIF_4D5) |
| 825 | return; |
| 826 | writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW); |
| 827 | writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW); |
| 828 | writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW); |
| 829 | } |
| 830 | |
| 831 | /* |
| 832 | * When voltage ramps dll calibration and forced read idle should |
| 833 | * happen more often |
| 834 | */ |
| 835 | static void setup_volt_sensitive_regs(struct emif_data *emif, |
| 836 | struct emif_regs *regs, u32 volt_state) |
| 837 | { |
| 838 | u32 calib_ctrl; |
| 839 | void __iomem *base = emif->base; |
| 840 | |
| 841 | /* |
| 842 | * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as |
| 843 | * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_* |
| 844 | * is an alias of the respective read_idle_ctrl_shdw_* (members of |
| 845 | * a union). So, the below code takes care of both cases |
| 846 | */ |
| 847 | if (volt_state == DDR_VOLTAGE_RAMPING) |
| 848 | calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp; |
| 849 | else |
| 850 | calib_ctrl = regs->dll_calib_ctrl_shdw_normal; |
| 851 | |
| 852 | writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW); |
| 853 | } |
| 854 | |
| 855 | /* |
| 856 | * setup_temperature_sensitive_regs() - set the timings for temperature |
| 857 | * sensitive registers. This happens once at initialisation time based |
| 858 | * on the temperature at boot time and subsequently based on the temperature |
| 859 | * alert interrupt. Temperature alert can happen when the temperature |
| 860 | * increases or drops. So this function can have the effect of either |
| 861 | * derating the timings or going back to nominal values. |
| 862 | */ |
| 863 | static void setup_temperature_sensitive_regs(struct emif_data *emif, |
| 864 | struct emif_regs *regs) |
| 865 | { |
| 866 | u32 tim1, tim3, ref_ctrl, type; |
| 867 | void __iomem *base = emif->base; |
| 868 | u32 temperature; |
| 869 | |
| 870 | type = emif->plat_data->device_info->type; |
| 871 | |
| 872 | tim1 = regs->sdram_tim1_shdw; |
| 873 | tim3 = regs->sdram_tim3_shdw; |
| 874 | ref_ctrl = regs->ref_ctrl_shdw; |
| 875 | |
| 876 | /* No de-rating for non-lpddr2 devices */ |
| 877 | if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4) |
| 878 | goto out; |
| 879 | |
| 880 | temperature = emif->temperature_level; |
| 881 | if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) { |
| 882 | ref_ctrl = regs->ref_ctrl_shdw_derated; |
| 883 | } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) { |
| 884 | tim1 = regs->sdram_tim1_shdw_derated; |
| 885 | tim3 = regs->sdram_tim3_shdw_derated; |
| 886 | ref_ctrl = regs->ref_ctrl_shdw_derated; |
| 887 | } |
| 888 | |
| 889 | out: |
| 890 | writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW); |
| 891 | writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW); |
| 892 | writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW); |
| 893 | } |
| 894 | |
Aneesh V | 68b4aee | 2012-04-27 17:54:07 +0530 | [diff] [blame] | 895 | static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif) |
| 896 | { |
| 897 | u32 old_temp_level; |
| 898 | irqreturn_t ret = IRQ_HANDLED; |
| 899 | |
| 900 | spin_lock_irqsave(&emif_lock, irq_state); |
| 901 | old_temp_level = emif->temperature_level; |
| 902 | get_temperature_level(emif); |
| 903 | |
| 904 | if (unlikely(emif->temperature_level == old_temp_level)) { |
| 905 | goto out; |
| 906 | } else if (!emif->curr_regs) { |
| 907 | dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n"); |
| 908 | goto out; |
| 909 | } |
| 910 | |
| 911 | if (emif->temperature_level < old_temp_level || |
| 912 | emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) { |
| 913 | /* |
| 914 | * Temperature coming down - defer handling to thread OR |
| 915 | * Temperature far too high - do kernel_power_off() from |
| 916 | * thread context |
| 917 | */ |
| 918 | ret = IRQ_WAKE_THREAD; |
| 919 | } else { |
| 920 | /* Temperature is going up - handle immediately */ |
| 921 | setup_temperature_sensitive_regs(emif, emif->curr_regs); |
| 922 | do_freq_update(); |
| 923 | } |
| 924 | |
| 925 | out: |
| 926 | spin_unlock_irqrestore(&emif_lock, irq_state); |
| 927 | return ret; |
| 928 | } |
| 929 | |
| 930 | static irqreturn_t emif_interrupt_handler(int irq, void *dev_id) |
| 931 | { |
| 932 | u32 interrupts; |
| 933 | struct emif_data *emif = dev_id; |
| 934 | void __iomem *base = emif->base; |
| 935 | struct device *dev = emif->dev; |
| 936 | irqreturn_t ret = IRQ_HANDLED; |
| 937 | |
| 938 | /* Save the status and clear it */ |
| 939 | interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); |
| 940 | writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); |
| 941 | |
| 942 | /* |
| 943 | * Handle temperature alert |
| 944 | * Temperature alert should be same for all ports |
| 945 | * So, it's enough to process it only for one of the ports |
| 946 | */ |
| 947 | if (interrupts & TA_SYS_MASK) |
| 948 | ret = handle_temp_alert(base, emif); |
| 949 | |
| 950 | if (interrupts & ERR_SYS_MASK) |
| 951 | dev_err(dev, "Access error from SYS port - %x\n", interrupts); |
| 952 | |
| 953 | if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) { |
| 954 | /* Save the status and clear it */ |
| 955 | interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS); |
| 956 | writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS); |
| 957 | |
| 958 | if (interrupts & ERR_LL_MASK) |
| 959 | dev_err(dev, "Access error from LL port - %x\n", |
| 960 | interrupts); |
| 961 | } |
| 962 | |
| 963 | return ret; |
| 964 | } |
| 965 | |
| 966 | static irqreturn_t emif_threaded_isr(int irq, void *dev_id) |
| 967 | { |
| 968 | struct emif_data *emif = dev_id; |
| 969 | |
| 970 | if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) { |
| 971 | dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n"); |
| 972 | kernel_power_off(); |
| 973 | return IRQ_HANDLED; |
| 974 | } |
| 975 | |
| 976 | spin_lock_irqsave(&emif_lock, irq_state); |
| 977 | |
| 978 | if (emif->curr_regs) { |
| 979 | setup_temperature_sensitive_regs(emif, emif->curr_regs); |
| 980 | do_freq_update(); |
| 981 | } else { |
| 982 | dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n"); |
| 983 | } |
| 984 | |
| 985 | spin_unlock_irqrestore(&emif_lock, irq_state); |
| 986 | |
| 987 | return IRQ_HANDLED; |
| 988 | } |
| 989 | |
| 990 | static void clear_all_interrupts(struct emif_data *emif) |
| 991 | { |
| 992 | void __iomem *base = emif->base; |
| 993 | |
| 994 | writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS), |
| 995 | base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); |
| 996 | if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) |
| 997 | writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS), |
| 998 | base + EMIF_LL_OCP_INTERRUPT_STATUS); |
| 999 | } |
| 1000 | |
| 1001 | static void disable_and_clear_all_interrupts(struct emif_data *emif) |
| 1002 | { |
| 1003 | void __iomem *base = emif->base; |
| 1004 | |
| 1005 | /* Disable all interrupts */ |
| 1006 | writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET), |
| 1007 | base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR); |
| 1008 | if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) |
| 1009 | writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET), |
| 1010 | base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR); |
| 1011 | |
| 1012 | /* Clear all interrupts */ |
| 1013 | clear_all_interrupts(emif); |
| 1014 | } |
| 1015 | |
| 1016 | static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq) |
| 1017 | { |
| 1018 | u32 interrupts, type; |
| 1019 | void __iomem *base = emif->base; |
| 1020 | |
| 1021 | type = emif->plat_data->device_info->type; |
| 1022 | |
| 1023 | clear_all_interrupts(emif); |
| 1024 | |
| 1025 | /* Enable interrupts for SYS interface */ |
| 1026 | interrupts = EN_ERR_SYS_MASK; |
| 1027 | if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) |
| 1028 | interrupts |= EN_TA_SYS_MASK; |
| 1029 | writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET); |
| 1030 | |
| 1031 | /* Enable interrupts for LL interface */ |
| 1032 | if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) { |
| 1033 | /* TA need not be enabled for LL */ |
| 1034 | interrupts = EN_ERR_LL_MASK; |
| 1035 | writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET); |
| 1036 | } |
| 1037 | |
| 1038 | /* setup IRQ handlers */ |
| 1039 | return devm_request_threaded_irq(emif->dev, irq, |
| 1040 | emif_interrupt_handler, |
| 1041 | emif_threaded_isr, |
| 1042 | 0, dev_name(emif->dev), |
| 1043 | emif); |
| 1044 | |
| 1045 | } |
| 1046 | |
Aneesh V | 98231c4f | 2012-04-27 17:54:08 +0530 | [diff] [blame] | 1047 | static void __init_or_module emif_onetime_settings(struct emif_data *emif) |
| 1048 | { |
| 1049 | u32 pwr_mgmt_ctrl, zq, temp_alert_cfg; |
| 1050 | void __iomem *base = emif->base; |
| 1051 | const struct lpddr2_addressing *addressing; |
| 1052 | const struct ddr_device_info *device_info; |
| 1053 | |
| 1054 | device_info = emif->plat_data->device_info; |
| 1055 | addressing = get_addressing_table(device_info); |
| 1056 | |
| 1057 | /* |
| 1058 | * Init power management settings |
| 1059 | * We don't know the frequency yet. Use a high frequency |
| 1060 | * value for a conservative timeout setting |
| 1061 | */ |
| 1062 | pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif, |
| 1063 | emif->plat_data->ip_rev); |
| 1064 | emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT; |
| 1065 | writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL); |
| 1066 | |
| 1067 | /* Init ZQ calibration settings */ |
| 1068 | zq = get_zq_config_reg(addressing, device_info->cs1_used, |
| 1069 | device_info->cal_resistors_per_cs); |
| 1070 | writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG); |
| 1071 | |
| 1072 | /* Check temperature level temperature level*/ |
| 1073 | get_temperature_level(emif); |
| 1074 | if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) |
| 1075 | dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n"); |
| 1076 | |
| 1077 | /* Init temperature polling */ |
| 1078 | temp_alert_cfg = get_temp_alert_config(addressing, |
| 1079 | emif->plat_data->custom_configs, device_info->cs1_used, |
| 1080 | device_info->io_width, get_emif_bus_width(emif)); |
| 1081 | writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG); |
| 1082 | |
| 1083 | /* |
| 1084 | * Program external PHY control registers that are not frequency |
| 1085 | * dependent |
| 1086 | */ |
| 1087 | if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY) |
| 1088 | return; |
| 1089 | writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW); |
| 1090 | writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW); |
| 1091 | writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW); |
| 1092 | writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW); |
| 1093 | writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW); |
| 1094 | writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW); |
| 1095 | writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW); |
| 1096 | writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW); |
| 1097 | writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW); |
| 1098 | writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW); |
| 1099 | writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW); |
| 1100 | writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW); |
| 1101 | writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW); |
| 1102 | writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW); |
| 1103 | writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW); |
| 1104 | writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW); |
| 1105 | writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW); |
| 1106 | writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW); |
| 1107 | writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW); |
| 1108 | writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW); |
| 1109 | writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW); |
| 1110 | } |
| 1111 | |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1112 | static void get_default_timings(struct emif_data *emif) |
| 1113 | { |
| 1114 | struct emif_platform_data *pd = emif->plat_data; |
| 1115 | |
| 1116 | pd->timings = lpddr2_jedec_timings; |
| 1117 | pd->timings_arr_size = ARRAY_SIZE(lpddr2_jedec_timings); |
| 1118 | |
| 1119 | dev_warn(emif->dev, "%s: using default timings\n", __func__); |
| 1120 | } |
| 1121 | |
| 1122 | static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type, |
| 1123 | u32 ip_rev, struct device *dev) |
| 1124 | { |
| 1125 | int valid; |
| 1126 | |
| 1127 | valid = (type == DDR_TYPE_LPDDR2_S4 || |
| 1128 | type == DDR_TYPE_LPDDR2_S2) |
| 1129 | && (density >= DDR_DENSITY_64Mb |
| 1130 | && density <= DDR_DENSITY_8Gb) |
| 1131 | && (io_width >= DDR_IO_WIDTH_8 |
| 1132 | && io_width <= DDR_IO_WIDTH_32); |
| 1133 | |
| 1134 | /* Combinations of EMIF and PHY revisions that we support today */ |
| 1135 | switch (ip_rev) { |
| 1136 | case EMIF_4D: |
| 1137 | valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY); |
| 1138 | break; |
| 1139 | case EMIF_4D5: |
| 1140 | valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY); |
| 1141 | break; |
| 1142 | default: |
| 1143 | valid = 0; |
| 1144 | } |
| 1145 | |
| 1146 | if (!valid) |
| 1147 | dev_err(dev, "%s: invalid DDR details\n", __func__); |
| 1148 | return valid; |
| 1149 | } |
| 1150 | |
| 1151 | static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs, |
| 1152 | struct device *dev) |
| 1153 | { |
| 1154 | int valid = 1; |
| 1155 | |
| 1156 | if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) && |
| 1157 | (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE)) |
| 1158 | valid = cust_cfgs->lpmode_freq_threshold && |
| 1159 | cust_cfgs->lpmode_timeout_performance && |
| 1160 | cust_cfgs->lpmode_timeout_power; |
| 1161 | |
| 1162 | if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL) |
| 1163 | valid = valid && cust_cfgs->temp_alert_poll_interval_ms; |
| 1164 | |
| 1165 | if (!valid) |
| 1166 | dev_warn(dev, "%s: invalid custom configs\n", __func__); |
| 1167 | |
| 1168 | return valid; |
| 1169 | } |
| 1170 | |
Aneesh V | e6b42eb | 2012-08-17 14:05:15 +0530 | [diff] [blame] | 1171 | #if defined(CONFIG_OF) |
| 1172 | static void __init_or_module of_get_custom_configs(struct device_node *np_emif, |
| 1173 | struct emif_data *emif) |
| 1174 | { |
| 1175 | struct emif_custom_configs *cust_cfgs = NULL; |
| 1176 | int len; |
| 1177 | const int *lpmode, *poll_intvl; |
| 1178 | |
| 1179 | lpmode = of_get_property(np_emif, "low-power-mode", &len); |
| 1180 | poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len); |
| 1181 | |
| 1182 | if (lpmode || poll_intvl) |
| 1183 | cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs), |
| 1184 | GFP_KERNEL); |
| 1185 | |
| 1186 | if (!cust_cfgs) |
| 1187 | return; |
| 1188 | |
| 1189 | if (lpmode) { |
| 1190 | cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE; |
| 1191 | cust_cfgs->lpmode = *lpmode; |
| 1192 | of_property_read_u32(np_emif, |
| 1193 | "low-power-mode-timeout-performance", |
| 1194 | &cust_cfgs->lpmode_timeout_performance); |
| 1195 | of_property_read_u32(np_emif, |
| 1196 | "low-power-mode-timeout-power", |
| 1197 | &cust_cfgs->lpmode_timeout_power); |
| 1198 | of_property_read_u32(np_emif, |
| 1199 | "low-power-mode-freq-threshold", |
| 1200 | &cust_cfgs->lpmode_freq_threshold); |
| 1201 | } |
| 1202 | |
| 1203 | if (poll_intvl) { |
| 1204 | cust_cfgs->mask |= |
| 1205 | EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL; |
| 1206 | cust_cfgs->temp_alert_poll_interval_ms = *poll_intvl; |
| 1207 | } |
| 1208 | |
| 1209 | if (!is_custom_config_valid(cust_cfgs, emif->dev)) { |
| 1210 | devm_kfree(emif->dev, cust_cfgs); |
| 1211 | return; |
| 1212 | } |
| 1213 | |
| 1214 | emif->plat_data->custom_configs = cust_cfgs; |
| 1215 | } |
| 1216 | |
| 1217 | static void __init_or_module of_get_ddr_info(struct device_node *np_emif, |
| 1218 | struct device_node *np_ddr, |
| 1219 | struct ddr_device_info *dev_info) |
| 1220 | { |
| 1221 | u32 density = 0, io_width = 0; |
| 1222 | int len; |
| 1223 | |
| 1224 | if (of_find_property(np_emif, "cs1-used", &len)) |
| 1225 | dev_info->cs1_used = true; |
| 1226 | |
| 1227 | if (of_find_property(np_emif, "cal-resistor-per-cs", &len)) |
| 1228 | dev_info->cal_resistors_per_cs = true; |
| 1229 | |
| 1230 | if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s4")) |
| 1231 | dev_info->type = DDR_TYPE_LPDDR2_S4; |
| 1232 | else if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s2")) |
| 1233 | dev_info->type = DDR_TYPE_LPDDR2_S2; |
| 1234 | |
| 1235 | of_property_read_u32(np_ddr, "density", &density); |
| 1236 | of_property_read_u32(np_ddr, "io-width", &io_width); |
| 1237 | |
| 1238 | /* Convert from density in Mb to the density encoding in jedc_ddr.h */ |
| 1239 | if (density & (density - 1)) |
| 1240 | dev_info->density = 0; |
| 1241 | else |
| 1242 | dev_info->density = __fls(density) - 5; |
| 1243 | |
| 1244 | /* Convert from io_width in bits to io_width encoding in jedc_ddr.h */ |
| 1245 | if (io_width & (io_width - 1)) |
| 1246 | dev_info->io_width = 0; |
| 1247 | else |
| 1248 | dev_info->io_width = __fls(io_width) - 1; |
| 1249 | } |
| 1250 | |
| 1251 | static struct emif_data * __init_or_module of_get_memory_device_details( |
| 1252 | struct device_node *np_emif, struct device *dev) |
| 1253 | { |
| 1254 | struct emif_data *emif = NULL; |
| 1255 | struct ddr_device_info *dev_info = NULL; |
| 1256 | struct emif_platform_data *pd = NULL; |
| 1257 | struct device_node *np_ddr; |
| 1258 | int len; |
| 1259 | |
| 1260 | np_ddr = of_parse_phandle(np_emif, "device-handle", 0); |
| 1261 | if (!np_ddr) |
| 1262 | goto error; |
| 1263 | emif = devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL); |
| 1264 | pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); |
| 1265 | dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL); |
| 1266 | |
| 1267 | if (!emif || !pd || !dev_info) { |
| 1268 | dev_err(dev, "%s: Out of memory!!\n", |
| 1269 | __func__); |
| 1270 | goto error; |
| 1271 | } |
| 1272 | |
| 1273 | emif->plat_data = pd; |
| 1274 | pd->device_info = dev_info; |
| 1275 | emif->dev = dev; |
| 1276 | emif->np_ddr = np_ddr; |
| 1277 | emif->temperature_level = SDRAM_TEMP_NOMINAL; |
| 1278 | |
| 1279 | if (of_device_is_compatible(np_emif, "ti,emif-4d")) |
| 1280 | emif->plat_data->ip_rev = EMIF_4D; |
| 1281 | else if (of_device_is_compatible(np_emif, "ti,emif-4d5")) |
| 1282 | emif->plat_data->ip_rev = EMIF_4D5; |
| 1283 | |
| 1284 | of_property_read_u32(np_emif, "phy-type", &pd->phy_type); |
| 1285 | |
| 1286 | if (of_find_property(np_emif, "hw-caps-ll-interface", &len)) |
| 1287 | pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE; |
| 1288 | |
| 1289 | of_get_ddr_info(np_emif, np_ddr, dev_info); |
| 1290 | if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density, |
| 1291 | pd->device_info->io_width, pd->phy_type, pd->ip_rev, |
| 1292 | emif->dev)) { |
| 1293 | dev_err(dev, "%s: invalid device data!!\n", __func__); |
| 1294 | goto error; |
| 1295 | } |
| 1296 | /* |
| 1297 | * For EMIF instances other than EMIF1 see if the devices connected |
| 1298 | * are exactly same as on EMIF1(which is typically the case). If so, |
| 1299 | * mark it as a duplicate of EMIF1. This will save some memory and |
| 1300 | * computation. |
| 1301 | */ |
| 1302 | if (emif1 && emif1->np_ddr == np_ddr) { |
| 1303 | emif->duplicate = true; |
| 1304 | goto out; |
| 1305 | } else if (emif1) { |
| 1306 | dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n", |
| 1307 | __func__); |
| 1308 | } |
| 1309 | |
| 1310 | of_get_custom_configs(np_emif, emif); |
| 1311 | emif->plat_data->timings = of_get_ddr_timings(np_ddr, emif->dev, |
| 1312 | emif->plat_data->device_info->type, |
| 1313 | &emif->plat_data->timings_arr_size); |
| 1314 | |
| 1315 | emif->plat_data->min_tck = of_get_min_tck(np_ddr, emif->dev); |
| 1316 | goto out; |
| 1317 | |
| 1318 | error: |
| 1319 | return NULL; |
| 1320 | out: |
| 1321 | return emif; |
| 1322 | } |
| 1323 | |
| 1324 | #else |
| 1325 | |
| 1326 | static struct emif_data * __init_or_module of_get_memory_device_details( |
| 1327 | struct device_node *np_emif, struct device *dev) |
| 1328 | { |
| 1329 | return NULL; |
| 1330 | } |
| 1331 | #endif |
| 1332 | |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1333 | static struct emif_data *__init_or_module get_device_details( |
| 1334 | struct platform_device *pdev) |
| 1335 | { |
| 1336 | u32 size; |
| 1337 | struct emif_data *emif = NULL; |
| 1338 | struct ddr_device_info *dev_info; |
| 1339 | struct emif_custom_configs *cust_cfgs; |
| 1340 | struct emif_platform_data *pd; |
| 1341 | struct device *dev; |
| 1342 | void *temp; |
| 1343 | |
| 1344 | pd = pdev->dev.platform_data; |
| 1345 | dev = &pdev->dev; |
| 1346 | |
| 1347 | if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type, |
| 1348 | pd->device_info->density, pd->device_info->io_width, |
| 1349 | pd->phy_type, pd->ip_rev, dev))) { |
| 1350 | dev_err(dev, "%s: invalid device data\n", __func__); |
| 1351 | goto error; |
| 1352 | } |
| 1353 | |
| 1354 | emif = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL); |
| 1355 | temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); |
| 1356 | dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL); |
| 1357 | |
| 1358 | if (!emif || !pd || !dev_info) { |
| 1359 | dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__); |
| 1360 | goto error; |
| 1361 | } |
| 1362 | |
| 1363 | memcpy(temp, pd, sizeof(*pd)); |
| 1364 | pd = temp; |
| 1365 | memcpy(dev_info, pd->device_info, sizeof(*dev_info)); |
| 1366 | |
| 1367 | pd->device_info = dev_info; |
| 1368 | emif->plat_data = pd; |
| 1369 | emif->dev = dev; |
| 1370 | emif->temperature_level = SDRAM_TEMP_NOMINAL; |
| 1371 | |
| 1372 | /* |
| 1373 | * For EMIF instances other than EMIF1 see if the devices connected |
| 1374 | * are exactly same as on EMIF1(which is typically the case). If so, |
| 1375 | * mark it as a duplicate of EMIF1 and skip copying timings data. |
| 1376 | * This will save some memory and some computation later. |
| 1377 | */ |
| 1378 | emif->duplicate = emif1 && (memcmp(dev_info, |
| 1379 | emif1->plat_data->device_info, |
| 1380 | sizeof(struct ddr_device_info)) == 0); |
| 1381 | |
| 1382 | if (emif->duplicate) { |
| 1383 | pd->timings = NULL; |
| 1384 | pd->min_tck = NULL; |
| 1385 | goto out; |
| 1386 | } else if (emif1) { |
| 1387 | dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n", |
| 1388 | __func__); |
| 1389 | } |
| 1390 | |
| 1391 | /* |
| 1392 | * Copy custom configs - ignore allocation error, if any, as |
| 1393 | * custom_configs is not very critical |
| 1394 | */ |
| 1395 | cust_cfgs = pd->custom_configs; |
| 1396 | if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) { |
| 1397 | temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL); |
| 1398 | if (temp) |
| 1399 | memcpy(temp, cust_cfgs, sizeof(*cust_cfgs)); |
| 1400 | else |
| 1401 | dev_warn(dev, "%s:%d: allocation error\n", __func__, |
| 1402 | __LINE__); |
| 1403 | pd->custom_configs = temp; |
| 1404 | } |
| 1405 | |
| 1406 | /* |
| 1407 | * Copy timings and min-tck values from platform data. If it is not |
| 1408 | * available or if memory allocation fails, use JEDEC defaults |
| 1409 | */ |
| 1410 | size = sizeof(struct lpddr2_timings) * pd->timings_arr_size; |
| 1411 | if (pd->timings) { |
| 1412 | temp = devm_kzalloc(dev, size, GFP_KERNEL); |
| 1413 | if (temp) { |
| 1414 | memcpy(temp, pd->timings, sizeof(*pd->timings)); |
| 1415 | pd->timings = temp; |
| 1416 | } else { |
| 1417 | dev_warn(dev, "%s:%d: allocation error\n", __func__, |
| 1418 | __LINE__); |
| 1419 | get_default_timings(emif); |
| 1420 | } |
| 1421 | } else { |
| 1422 | get_default_timings(emif); |
| 1423 | } |
| 1424 | |
| 1425 | if (pd->min_tck) { |
| 1426 | temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL); |
| 1427 | if (temp) { |
| 1428 | memcpy(temp, pd->min_tck, sizeof(*pd->min_tck)); |
| 1429 | pd->min_tck = temp; |
| 1430 | } else { |
| 1431 | dev_warn(dev, "%s:%d: allocation error\n", __func__, |
| 1432 | __LINE__); |
| 1433 | pd->min_tck = &lpddr2_jedec_min_tck; |
| 1434 | } |
| 1435 | } else { |
| 1436 | pd->min_tck = &lpddr2_jedec_min_tck; |
| 1437 | } |
| 1438 | |
| 1439 | out: |
| 1440 | return emif; |
| 1441 | |
| 1442 | error: |
| 1443 | return NULL; |
| 1444 | } |
| 1445 | |
| 1446 | static int __init_or_module emif_probe(struct platform_device *pdev) |
| 1447 | { |
| 1448 | struct emif_data *emif; |
| 1449 | struct resource *res; |
Aneesh V | 68b4aee | 2012-04-27 17:54:07 +0530 | [diff] [blame] | 1450 | int irq; |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1451 | |
Aneesh V | e6b42eb | 2012-08-17 14:05:15 +0530 | [diff] [blame] | 1452 | if (pdev->dev.of_node) |
| 1453 | emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev); |
| 1454 | else |
| 1455 | emif = get_device_details(pdev); |
| 1456 | |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1457 | if (!emif) { |
| 1458 | pr_err("%s: error getting device data\n", __func__); |
| 1459 | goto error; |
| 1460 | } |
| 1461 | |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1462 | list_add(&emif->node, &device_list); |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 1463 | emif->addressing = get_addressing_table(emif->plat_data->device_info); |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1464 | |
| 1465 | /* Save pointers to each other in emif and device structures */ |
| 1466 | emif->dev = &pdev->dev; |
| 1467 | platform_set_drvdata(pdev, emif); |
| 1468 | |
| 1469 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1470 | if (!res) { |
| 1471 | dev_err(emif->dev, "%s: error getting memory resource\n", |
| 1472 | __func__); |
| 1473 | goto error; |
| 1474 | } |
| 1475 | |
Thierry Reding | 06303c2 | 2013-01-21 11:09:08 +0100 | [diff] [blame] | 1476 | emif->base = devm_ioremap_resource(emif->dev, res); |
| 1477 | if (IS_ERR(emif->base)) |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1478 | goto error; |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1479 | |
Aneesh V | 68b4aee | 2012-04-27 17:54:07 +0530 | [diff] [blame] | 1480 | irq = platform_get_irq(pdev, 0); |
| 1481 | if (irq < 0) { |
| 1482 | dev_err(emif->dev, "%s: error getting IRQ resource - %d\n", |
| 1483 | __func__, irq); |
| 1484 | goto error; |
| 1485 | } |
| 1486 | |
Aneesh V | 98231c4f | 2012-04-27 17:54:08 +0530 | [diff] [blame] | 1487 | emif_onetime_settings(emif); |
Aneesh V | aac10aa | 2012-04-27 17:54:09 +0530 | [diff] [blame] | 1488 | emif_debugfs_init(emif); |
Aneesh V | 68b4aee | 2012-04-27 17:54:07 +0530 | [diff] [blame] | 1489 | disable_and_clear_all_interrupts(emif); |
| 1490 | setup_interrupts(emif, irq); |
| 1491 | |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 1492 | /* One-time actions taken on probing the first device */ |
| 1493 | if (!emif1) { |
| 1494 | emif1 = emif; |
| 1495 | spin_lock_init(&emif_lock); |
| 1496 | |
| 1497 | /* |
| 1498 | * TODO: register notifiers for frequency and voltage |
| 1499 | * change here once the respective frameworks are |
| 1500 | * available |
| 1501 | */ |
| 1502 | } |
| 1503 | |
Aneesh V | 68b4aee | 2012-04-27 17:54:07 +0530 | [diff] [blame] | 1504 | dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n", |
| 1505 | __func__, emif->base, irq); |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1506 | |
| 1507 | return 0; |
| 1508 | error: |
| 1509 | return -ENODEV; |
| 1510 | } |
| 1511 | |
Aneesh V | aac10aa | 2012-04-27 17:54:09 +0530 | [diff] [blame] | 1512 | static int __exit emif_remove(struct platform_device *pdev) |
| 1513 | { |
| 1514 | struct emif_data *emif = platform_get_drvdata(pdev); |
| 1515 | |
| 1516 | emif_debugfs_exit(emif); |
| 1517 | |
| 1518 | return 0; |
| 1519 | } |
| 1520 | |
Aneesh V | 68b4aee | 2012-04-27 17:54:07 +0530 | [diff] [blame] | 1521 | static void emif_shutdown(struct platform_device *pdev) |
| 1522 | { |
| 1523 | struct emif_data *emif = platform_get_drvdata(pdev); |
| 1524 | |
| 1525 | disable_and_clear_all_interrupts(emif); |
| 1526 | } |
| 1527 | |
Aneesh V | a93de28 | 2012-04-27 17:54:06 +0530 | [diff] [blame] | 1528 | static int get_emif_reg_values(struct emif_data *emif, u32 freq, |
| 1529 | struct emif_regs *regs) |
| 1530 | { |
| 1531 | u32 cs1_used, ip_rev, phy_type; |
| 1532 | u32 cl, type; |
| 1533 | const struct lpddr2_timings *timings; |
| 1534 | const struct lpddr2_min_tck *min_tck; |
| 1535 | const struct ddr_device_info *device_info; |
| 1536 | const struct lpddr2_addressing *addressing; |
| 1537 | struct emif_data *emif_for_calc; |
| 1538 | struct device *dev; |
| 1539 | const struct emif_custom_configs *custom_configs; |
| 1540 | |
| 1541 | dev = emif->dev; |
| 1542 | /* |
| 1543 | * If the devices on this EMIF instance is duplicate of EMIF1, |
| 1544 | * use EMIF1 details for the calculation |
| 1545 | */ |
| 1546 | emif_for_calc = emif->duplicate ? emif1 : emif; |
| 1547 | timings = get_timings_table(emif_for_calc, freq); |
| 1548 | addressing = emif_for_calc->addressing; |
| 1549 | if (!timings || !addressing) { |
| 1550 | dev_err(dev, "%s: not enough data available for %dHz", |
| 1551 | __func__, freq); |
| 1552 | return -1; |
| 1553 | } |
| 1554 | |
| 1555 | device_info = emif_for_calc->plat_data->device_info; |
| 1556 | type = device_info->type; |
| 1557 | cs1_used = device_info->cs1_used; |
| 1558 | ip_rev = emif_for_calc->plat_data->ip_rev; |
| 1559 | phy_type = emif_for_calc->plat_data->phy_type; |
| 1560 | |
| 1561 | min_tck = emif_for_calc->plat_data->min_tck; |
| 1562 | custom_configs = emif_for_calc->plat_data->custom_configs; |
| 1563 | |
| 1564 | set_ddr_clk_period(freq); |
| 1565 | |
| 1566 | regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing); |
| 1567 | regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck, |
| 1568 | addressing); |
| 1569 | regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck, |
| 1570 | addressing, type); |
| 1571 | regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck, |
| 1572 | addressing, type, ip_rev, EMIF_NORMAL_TIMINGS); |
| 1573 | |
| 1574 | cl = get_cl(emif); |
| 1575 | |
| 1576 | if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) { |
| 1577 | regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d( |
| 1578 | timings, freq, cl); |
| 1579 | } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) { |
| 1580 | regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl); |
| 1581 | regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5(); |
| 1582 | regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5(); |
| 1583 | regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5(); |
| 1584 | } else { |
| 1585 | return -1; |
| 1586 | } |
| 1587 | |
| 1588 | /* Only timeout values in pwr_mgmt_ctrl_shdw register */ |
| 1589 | regs->pwr_mgmt_ctrl_shdw = |
| 1590 | get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) & |
| 1591 | (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK); |
| 1592 | |
| 1593 | if (ip_rev & EMIF_4D) { |
| 1594 | regs->read_idle_ctrl_shdw_normal = |
| 1595 | get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE); |
| 1596 | |
| 1597 | regs->read_idle_ctrl_shdw_volt_ramp = |
| 1598 | get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING); |
| 1599 | } else if (ip_rev & EMIF_4D5) { |
| 1600 | regs->dll_calib_ctrl_shdw_normal = |
| 1601 | get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE); |
| 1602 | |
| 1603 | regs->dll_calib_ctrl_shdw_volt_ramp = |
| 1604 | get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING); |
| 1605 | } |
| 1606 | |
| 1607 | if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) { |
| 1608 | regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4, |
| 1609 | addressing); |
| 1610 | |
| 1611 | regs->sdram_tim1_shdw_derated = |
| 1612 | get_sdram_tim_1_shdw_derated(timings, min_tck, |
| 1613 | addressing); |
| 1614 | |
| 1615 | regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings, |
| 1616 | min_tck, addressing, type, ip_rev, |
| 1617 | EMIF_DERATED_TIMINGS); |
| 1618 | } |
| 1619 | |
| 1620 | regs->freq = freq; |
| 1621 | |
| 1622 | return 0; |
| 1623 | } |
| 1624 | |
| 1625 | /* |
| 1626 | * get_regs() - gets the cached emif_regs structure for a given EMIF instance |
| 1627 | * given frequency(freq): |
| 1628 | * |
| 1629 | * As an optimisation, every EMIF instance other than EMIF1 shares the |
| 1630 | * register cache with EMIF1 if the devices connected on this instance |
| 1631 | * are same as that on EMIF1(indicated by the duplicate flag) |
| 1632 | * |
| 1633 | * If we do not have an entry corresponding to the frequency given, we |
| 1634 | * allocate a new entry and calculate the values |
| 1635 | * |
| 1636 | * Upon finding the right reg dump, save it in curr_regs. It can be |
| 1637 | * directly used for thermal de-rating and voltage ramping changes. |
| 1638 | */ |
| 1639 | static struct emif_regs *get_regs(struct emif_data *emif, u32 freq) |
| 1640 | { |
| 1641 | int i; |
| 1642 | struct emif_regs **regs_cache; |
| 1643 | struct emif_regs *regs = NULL; |
| 1644 | struct device *dev; |
| 1645 | |
| 1646 | dev = emif->dev; |
| 1647 | if (emif->curr_regs && emif->curr_regs->freq == freq) { |
| 1648 | dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq); |
| 1649 | return emif->curr_regs; |
| 1650 | } |
| 1651 | |
| 1652 | if (emif->duplicate) |
| 1653 | regs_cache = emif1->regs_cache; |
| 1654 | else |
| 1655 | regs_cache = emif->regs_cache; |
| 1656 | |
| 1657 | for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) { |
| 1658 | if (regs_cache[i]->freq == freq) { |
| 1659 | regs = regs_cache[i]; |
| 1660 | dev_dbg(dev, |
| 1661 | "%s: reg dump found in reg cache for %u Hz\n", |
| 1662 | __func__, freq); |
| 1663 | break; |
| 1664 | } |
| 1665 | } |
| 1666 | |
| 1667 | /* |
| 1668 | * If we don't have an entry for this frequency in the cache create one |
| 1669 | * and calculate the values |
| 1670 | */ |
| 1671 | if (!regs) { |
| 1672 | regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC); |
| 1673 | if (!regs) |
| 1674 | return NULL; |
| 1675 | |
| 1676 | if (get_emif_reg_values(emif, freq, regs)) { |
| 1677 | devm_kfree(emif->dev, regs); |
| 1678 | return NULL; |
| 1679 | } |
| 1680 | |
| 1681 | /* |
| 1682 | * Now look for an un-used entry in the cache and save the |
| 1683 | * newly created struct. If there are no free entries |
| 1684 | * over-write the last entry |
| 1685 | */ |
| 1686 | for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) |
| 1687 | ; |
| 1688 | |
| 1689 | if (i >= EMIF_MAX_NUM_FREQUENCIES) { |
| 1690 | dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n", |
| 1691 | __func__); |
| 1692 | i = EMIF_MAX_NUM_FREQUENCIES - 1; |
| 1693 | devm_kfree(emif->dev, regs_cache[i]); |
| 1694 | } |
| 1695 | regs_cache[i] = regs; |
| 1696 | } |
| 1697 | |
| 1698 | return regs; |
| 1699 | } |
| 1700 | |
| 1701 | static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state) |
| 1702 | { |
| 1703 | dev_dbg(emif->dev, "%s: voltage notification : %d", __func__, |
| 1704 | volt_state); |
| 1705 | |
| 1706 | if (!emif->curr_regs) { |
| 1707 | dev_err(emif->dev, |
| 1708 | "%s: volt-notify before registers are ready: %d\n", |
| 1709 | __func__, volt_state); |
| 1710 | return; |
| 1711 | } |
| 1712 | |
| 1713 | setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state); |
| 1714 | } |
| 1715 | |
| 1716 | /* |
| 1717 | * TODO: voltage notify handling should be hooked up to |
| 1718 | * regulator framework as soon as the necessary support |
| 1719 | * is available in mainline kernel. This function is un-used |
| 1720 | * right now. |
| 1721 | */ |
| 1722 | static void __attribute__((unused)) volt_notify_handling(u32 volt_state) |
| 1723 | { |
| 1724 | struct emif_data *emif; |
| 1725 | |
| 1726 | spin_lock_irqsave(&emif_lock, irq_state); |
| 1727 | |
| 1728 | list_for_each_entry(emif, &device_list, node) |
| 1729 | do_volt_notify_handling(emif, volt_state); |
| 1730 | do_freq_update(); |
| 1731 | |
| 1732 | spin_unlock_irqrestore(&emif_lock, irq_state); |
| 1733 | } |
| 1734 | |
| 1735 | static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq) |
| 1736 | { |
| 1737 | struct emif_regs *regs; |
| 1738 | |
| 1739 | regs = get_regs(emif, new_freq); |
| 1740 | if (!regs) |
| 1741 | return; |
| 1742 | |
| 1743 | emif->curr_regs = regs; |
| 1744 | |
| 1745 | /* |
| 1746 | * Update the shadow registers: |
| 1747 | * Temperature and voltage-ramp sensitive settings are also configured |
| 1748 | * in terms of DDR cycles. So, we need to update them too when there |
| 1749 | * is a freq change |
| 1750 | */ |
| 1751 | dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz", |
| 1752 | __func__, new_freq); |
| 1753 | setup_registers(emif, regs); |
| 1754 | setup_temperature_sensitive_regs(emif, regs); |
| 1755 | setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE); |
| 1756 | |
| 1757 | /* |
| 1758 | * Part of workaround for errata i728. See do_freq_update() |
| 1759 | * for more details |
| 1760 | */ |
| 1761 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) |
| 1762 | set_lpmode(emif, EMIF_LP_MODE_DISABLE); |
| 1763 | } |
| 1764 | |
| 1765 | /* |
| 1766 | * TODO: frequency notify handling should be hooked up to |
| 1767 | * clock framework as soon as the necessary support is |
| 1768 | * available in mainline kernel. This function is un-used |
| 1769 | * right now. |
| 1770 | */ |
| 1771 | static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq) |
| 1772 | { |
| 1773 | struct emif_data *emif; |
| 1774 | |
| 1775 | /* |
| 1776 | * NOTE: we are taking the spin-lock here and releases it |
| 1777 | * only in post-notifier. This doesn't look good and |
| 1778 | * Sparse complains about it, but this seems to be |
| 1779 | * un-avoidable. We need to lock a sequence of events |
| 1780 | * that is split between EMIF and clock framework. |
| 1781 | * |
| 1782 | * 1. EMIF driver updates EMIF timings in shadow registers in the |
| 1783 | * frequency pre-notify callback from clock framework |
| 1784 | * 2. clock framework sets up the registers for the new frequency |
| 1785 | * 3. clock framework initiates a hw-sequence that updates |
| 1786 | * the frequency EMIF timings synchronously. |
| 1787 | * |
| 1788 | * All these 3 steps should be performed as an atomic operation |
| 1789 | * vis-a-vis similar sequence in the EMIF interrupt handler |
| 1790 | * for temperature events. Otherwise, there could be race |
| 1791 | * conditions that could result in incorrect EMIF timings for |
| 1792 | * a given frequency |
| 1793 | */ |
| 1794 | spin_lock_irqsave(&emif_lock, irq_state); |
| 1795 | |
| 1796 | list_for_each_entry(emif, &device_list, node) |
| 1797 | do_freq_pre_notify_handling(emif, new_freq); |
| 1798 | } |
| 1799 | |
| 1800 | static void do_freq_post_notify_handling(struct emif_data *emif) |
| 1801 | { |
| 1802 | /* |
| 1803 | * Part of workaround for errata i728. See do_freq_update() |
| 1804 | * for more details |
| 1805 | */ |
| 1806 | if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH) |
| 1807 | set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH); |
| 1808 | } |
| 1809 | |
| 1810 | /* |
| 1811 | * TODO: frequency notify handling should be hooked up to |
| 1812 | * clock framework as soon as the necessary support is |
| 1813 | * available in mainline kernel. This function is un-used |
| 1814 | * right now. |
| 1815 | */ |
| 1816 | static void __attribute__((unused)) freq_post_notify_handling(void) |
| 1817 | { |
| 1818 | struct emif_data *emif; |
| 1819 | |
| 1820 | list_for_each_entry(emif, &device_list, node) |
| 1821 | do_freq_post_notify_handling(emif); |
| 1822 | |
| 1823 | /* |
| 1824 | * Lock is done in pre-notify handler. See freq_pre_notify_handling() |
| 1825 | * for more details |
| 1826 | */ |
| 1827 | spin_unlock_irqrestore(&emif_lock, irq_state); |
| 1828 | } |
| 1829 | |
Aneesh V | e6b42eb | 2012-08-17 14:05:15 +0530 | [diff] [blame] | 1830 | #if defined(CONFIG_OF) |
| 1831 | static const struct of_device_id emif_of_match[] = { |
| 1832 | { .compatible = "ti,emif-4d" }, |
| 1833 | { .compatible = "ti,emif-4d5" }, |
| 1834 | {}, |
| 1835 | }; |
| 1836 | MODULE_DEVICE_TABLE(of, emif_of_match); |
| 1837 | #endif |
| 1838 | |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1839 | static struct platform_driver emif_driver = { |
Aneesh V | aac10aa | 2012-04-27 17:54:09 +0530 | [diff] [blame] | 1840 | .remove = __exit_p(emif_remove), |
Aneesh V | 68b4aee | 2012-04-27 17:54:07 +0530 | [diff] [blame] | 1841 | .shutdown = emif_shutdown, |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1842 | .driver = { |
| 1843 | .name = "emif", |
Aneesh V | e6b42eb | 2012-08-17 14:05:15 +0530 | [diff] [blame] | 1844 | .of_match_table = of_match_ptr(emif_of_match), |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1845 | }, |
| 1846 | }; |
| 1847 | |
Fabio Porcedda | 7a4541a | 2013-03-14 18:09:35 +0100 | [diff] [blame] | 1848 | module_platform_driver_probe(emif_driver, emif_probe); |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1849 | |
Aneesh V | 7ec9445 | 2012-04-27 17:54:05 +0530 | [diff] [blame] | 1850 | MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver"); |
| 1851 | MODULE_LICENSE("GPL"); |
| 1852 | MODULE_ALIAS("platform:emif"); |
| 1853 | MODULE_AUTHOR("Texas Instruments Inc"); |