Teresa Remmet | 52b0dcb | 2015-07-16 10:30:48 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Phytec Messtechnik GmbH |
| 3 | * Author: Teresa Remmet <t.remmet@phytec.de> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | |
| 10 | #include "am33xx.dtsi" |
| 11 | |
| 12 | / { |
| 13 | model = "Phytec AM335x phyCORE"; |
| 14 | compatible = "phytec,am335x-phycore-som", "ti,am33xx"; |
| 15 | |
| 16 | aliases { |
| 17 | rtc0 = &i2c_rtc; |
| 18 | rtc1 = &rtc; |
| 19 | }; |
| 20 | |
| 21 | cpus { |
| 22 | cpu@0 { |
| 23 | cpu0-supply = <&vdd1_reg>; |
| 24 | }; |
| 25 | }; |
| 26 | |
| 27 | memory { |
| 28 | device_type = "memory"; |
| 29 | reg = <0x80000000 0x10000000>; /* 256 MB */ |
| 30 | }; |
| 31 | |
Teresa Remmet | c72bfb8 | 2015-09-03 14:00:07 +0200 | [diff] [blame] | 32 | regulators { |
| 33 | compatible = "simple-bus"; |
| 34 | |
| 35 | vcc5v: fixedregulator@0 { |
| 36 | compatible = "regulator-fixed"; |
| 37 | regulator-name = "vcc5v"; |
| 38 | regulator-min-microvolt = <5000000>; |
| 39 | regulator-max-microvolt = <5000000>; |
| 40 | regulator-boot-on; |
| 41 | regulator-always-on; |
| 42 | }; |
Teresa Remmet | 52b0dcb | 2015-07-16 10:30:48 +0200 | [diff] [blame] | 43 | }; |
| 44 | }; |
| 45 | |
| 46 | /* Crypto Module */ |
| 47 | &aes { |
| 48 | status = "okay"; |
| 49 | }; |
| 50 | |
| 51 | &sham { |
| 52 | status = "okay"; |
| 53 | }; |
| 54 | |
| 55 | /* Ethernet */ |
| 56 | &am33xx_pinmux { |
| 57 | ethernet0_pins: pinmux_ethernet0 { |
| 58 | pinctrl-single,pins = < |
Javier Martinez Canillas | 9baa78d | 2015-11-13 01:53:51 -0300 | [diff] [blame] | 59 | AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ |
| 60 | AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ |
| 61 | AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */ |
| 62 | AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ |
| 63 | AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ |
| 64 | AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ |
| 65 | AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ |
| 66 | AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ |
Teresa Remmet | 52b0dcb | 2015-07-16 10:30:48 +0200 | [diff] [blame] | 67 | >; |
| 68 | }; |
| 69 | |
| 70 | mdio_pins: pinmux_mdio { |
| 71 | pinctrl-single,pins = < |
| 72 | /* MDIO */ |
Javier Martinez Canillas | 9baa78d | 2015-11-13 01:53:51 -0300 | [diff] [blame] | 73 | AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ |
| 74 | AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ |
Teresa Remmet | 52b0dcb | 2015-07-16 10:30:48 +0200 | [diff] [blame] | 75 | >; |
| 76 | }; |
| 77 | }; |
| 78 | |
| 79 | &cpsw_emac0 { |
| 80 | phy_id = <&davinci_mdio>, <0>; |
| 81 | phy-mode = "rmii"; |
| 82 | dual_emac_res_vlan = <1>; |
| 83 | }; |
| 84 | |
| 85 | &davinci_mdio { |
| 86 | pinctrl-names = "default"; |
| 87 | pinctrl-0 = <&mdio_pins>; |
| 88 | status = "okay"; |
| 89 | }; |
| 90 | |
| 91 | &mac { |
| 92 | slaves = <1>; |
| 93 | pinctrl-names = "default"; |
| 94 | pinctrl-0 = <ðernet0_pins>; |
| 95 | status = "okay"; |
| 96 | }; |
| 97 | |
| 98 | &phy_sel { |
| 99 | rmii-clock-ext; |
| 100 | }; |
| 101 | |
| 102 | /* I2C Busses */ |
| 103 | &am33xx_pinmux { |
| 104 | i2c0_pins: pinmux_i2c0 { |
| 105 | pinctrl-single,pins = < |
Javier Martinez Canillas | 9baa78d | 2015-11-13 01:53:51 -0300 | [diff] [blame] | 106 | AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
| 107 | AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
Teresa Remmet | 52b0dcb | 2015-07-16 10:30:48 +0200 | [diff] [blame] | 108 | >; |
| 109 | }; |
| 110 | }; |
| 111 | |
| 112 | &i2c0 { |
| 113 | pinctrl-names = "default"; |
| 114 | pinctrl-0 = <&i2c0_pins>; |
| 115 | clock-frequency = <400000>; |
| 116 | status = "okay"; |
| 117 | |
| 118 | tps: pmic@2d { |
| 119 | reg = <0x2d>; |
| 120 | }; |
| 121 | |
| 122 | i2c_eeprom: eeprom@52 { |
| 123 | compatible = "atmel,24c32"; |
| 124 | pagesize = <32>; |
| 125 | reg = <0x52>; |
| 126 | status = "disabled"; |
| 127 | }; |
| 128 | |
| 129 | i2c_rtc: rtc@68 { |
| 130 | compatible = "rv4162"; |
| 131 | reg = <0x68>; |
| 132 | status = "disabled"; |
| 133 | }; |
| 134 | }; |
| 135 | |
| 136 | /* NAND memory */ |
| 137 | &am33xx_pinmux { |
| 138 | nandflash_pins: pinmux_nandflash { |
| 139 | pinctrl-single,pins = < |
Javier Martinez Canillas | 9baa78d | 2015-11-13 01:53:51 -0300 | [diff] [blame] | 140 | AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ |
| 141 | AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ |
| 142 | AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ |
| 143 | AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ |
| 144 | AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ |
| 145 | AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ |
| 146 | AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ |
| 147 | AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ |
| 148 | AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ |
| 149 | AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ |
| 150 | AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ |
| 151 | AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ |
| 152 | AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ |
| 153 | AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ |
Teresa Remmet | 52b0dcb | 2015-07-16 10:30:48 +0200 | [diff] [blame] | 154 | >; |
| 155 | }; |
| 156 | }; |
| 157 | |
| 158 | &elm { |
| 159 | status = "okay"; |
| 160 | }; |
| 161 | |
| 162 | &gpmc { |
| 163 | status = "okay"; |
| 164 | pinctrl-names = "default"; |
| 165 | pinctrl-0 = <&nandflash_pins>; |
| 166 | ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */ |
| 167 | nandflash: nand@0,0 { |
| 168 | reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ |
| 169 | nand-bus-width = <8>; |
| 170 | ti,nand-ecc-opt = "bch8"; |
| 171 | gpmc,device-nand = "true"; |
| 172 | gpmc,device-width = <1>; |
| 173 | gpmc,sync-clk-ps = <0>; |
| 174 | gpmc,cs-on-ns = <0>; |
| 175 | gpmc,cs-rd-off-ns = <30>; |
| 176 | gpmc,cs-wr-off-ns = <30>; |
| 177 | gpmc,adv-on-ns = <0>; |
| 178 | gpmc,adv-rd-off-ns = <30>; |
| 179 | gpmc,adv-wr-off-ns = <30>; |
| 180 | gpmc,we-on-ns = <0>; |
| 181 | gpmc,we-off-ns = <20>; |
| 182 | gpmc,oe-on-ns = <10>; |
| 183 | gpmc,oe-off-ns = <30>; |
| 184 | gpmc,access-ns = <30>; |
| 185 | gpmc,rd-cycle-ns = <30>; |
| 186 | gpmc,wr-cycle-ns = <30>; |
| 187 | gpmc,wait-on-read = "true"; |
| 188 | gpmc,wait-on-write = "true"; |
| 189 | gpmc,bus-turnaround-ns = <0>; |
| 190 | gpmc,cycle2cycle-delay-ns = <50>; |
| 191 | gpmc,cycle2cycle-diffcsen; |
| 192 | gpmc,clk-activation-ns = <0>; |
| 193 | gpmc,wait-monitoring-ns = <0>; |
| 194 | gpmc,wr-access-ns = <30>; |
| 195 | gpmc,wr-data-mux-bus-ns = <0>; |
| 196 | |
| 197 | elm_id = <&elm>; |
| 198 | |
| 199 | #address-cells = <1>; |
| 200 | #size-cells = <1>; |
| 201 | |
| 202 | partition@0 { |
| 203 | label = "xload"; |
| 204 | reg = <0x0 0x20000>; |
| 205 | }; |
| 206 | partition@1 { |
| 207 | label = "xload_backup1"; |
| 208 | reg = <0x20000 0x20000>; |
| 209 | }; |
| 210 | partition@2 { |
| 211 | label = "xload_backup2"; |
| 212 | reg = <0x40000 0x20000>; |
| 213 | }; |
| 214 | partition@3 { |
| 215 | label = "xload_backup3"; |
| 216 | reg = <0x60000 0x20000>; |
| 217 | }; |
| 218 | partition@4 { |
| 219 | label = "barebox"; |
| 220 | reg = <0x80000 0x80000>; |
| 221 | }; |
| 222 | partition@5 { |
| 223 | label = "bareboxenv"; |
| 224 | reg = <0x100000 0x40000>; |
| 225 | }; |
| 226 | partition@6 { |
| 227 | label = "oftree"; |
| 228 | reg = <0x140000 0x40000>; |
| 229 | }; |
| 230 | partition@7 { |
| 231 | label = "kernel"; |
| 232 | reg = <0x180000 0x800000>; |
| 233 | }; |
| 234 | partition@8 { |
| 235 | label = "root"; |
| 236 | reg = <0x980000 0x0>; |
| 237 | }; |
| 238 | }; |
| 239 | }; |
| 240 | |
| 241 | /* Power */ |
| 242 | #include "tps65910.dtsi" |
| 243 | |
| 244 | &tps { |
Teresa Remmet | c72bfb8 | 2015-09-03 14:00:07 +0200 | [diff] [blame] | 245 | vcc1-supply = <&vcc5v>; |
| 246 | vcc2-supply = <&vcc5v>; |
| 247 | vcc3-supply = <&vcc5v>; |
| 248 | vcc4-supply = <&vcc5v>; |
| 249 | vcc5-supply = <&vcc5v>; |
| 250 | vcc6-supply = <&vcc5v>; |
| 251 | vcc7-supply = <&vcc5v>; |
| 252 | vccio-supply = <&vcc5v>; |
Teresa Remmet | 52b0dcb | 2015-07-16 10:30:48 +0200 | [diff] [blame] | 253 | |
| 254 | regulators { |
| 255 | vrtc_reg: regulator@0 { |
| 256 | regulator-always-on; |
| 257 | }; |
| 258 | |
| 259 | vio_reg: regulator@1 { |
| 260 | regulator-always-on; |
| 261 | }; |
| 262 | |
| 263 | vdd1_reg: regulator@2 { |
Teresa Remmet | 259c0c0 | 2015-09-03 14:00:06 +0200 | [diff] [blame] | 264 | /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */ |
Teresa Remmet | 52b0dcb | 2015-07-16 10:30:48 +0200 | [diff] [blame] | 265 | regulator-name = "vdd_mpu"; |
| 266 | regulator-min-microvolt = <912500>; |
Teresa Remmet | 259c0c0 | 2015-09-03 14:00:06 +0200 | [diff] [blame] | 267 | regulator-max-microvolt = <1378000>; |
Teresa Remmet | 52b0dcb | 2015-07-16 10:30:48 +0200 | [diff] [blame] | 268 | regulator-boot-on; |
| 269 | regulator-always-on; |
| 270 | }; |
| 271 | |
| 272 | vdd2_reg: regulator@3 { |
| 273 | /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ |
| 274 | regulator-name = "vdd_core"; |
| 275 | regulator-min-microvolt = <912500>; |
| 276 | regulator-max-microvolt = <1150000>; |
| 277 | regulator-boot-on; |
| 278 | regulator-always-on; |
| 279 | }; |
| 280 | |
| 281 | vdd3_reg: regulator@4 { |
| 282 | regulator-always-on; |
| 283 | }; |
| 284 | |
| 285 | vdig1_reg: regulator@5 { |
| 286 | regulator-name = "vdig1_1p8v"; |
| 287 | regulator-min-microvolt = <1800000>; |
| 288 | regulator-max-microvolt = <1800000>; |
| 289 | }; |
| 290 | |
| 291 | vdig2_reg: regulator@6 { |
| 292 | regulator-always-on; |
| 293 | }; |
| 294 | |
| 295 | vpll_reg: regulator@7 { |
| 296 | regulator-always-on; |
| 297 | }; |
| 298 | |
| 299 | vdac_reg: regulator@8 { |
| 300 | regulator-always-on; |
| 301 | }; |
| 302 | |
| 303 | vaux1_reg: regulator@9 { |
| 304 | regulator-always-on; |
| 305 | }; |
| 306 | |
| 307 | vaux2_reg: regulator@10 { |
| 308 | regulator-always-on; |
| 309 | }; |
| 310 | |
| 311 | vaux33_reg: regulator@11 { |
| 312 | regulator-always-on; |
| 313 | }; |
| 314 | |
| 315 | vmmc_reg: regulator@12 { |
| 316 | regulator-min-microvolt = <3300000>; |
| 317 | regulator-max-microvolt = <3300000>; |
| 318 | regulator-always-on; |
| 319 | }; |
| 320 | }; |
| 321 | }; |
| 322 | |
Teresa Remmet | 52b0dcb | 2015-07-16 10:30:48 +0200 | [diff] [blame] | 323 | /* SPI Busses */ |
| 324 | &am33xx_pinmux { |
| 325 | spi0_pins: pinmux_spi0 { |
| 326 | pinctrl-single,pins = < |
Javier Martinez Canillas | 9baa78d | 2015-11-13 01:53:51 -0300 | [diff] [blame] | 327 | AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */ |
| 328 | AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */ |
| 329 | AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ |
| 330 | AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ |
Teresa Remmet | 52b0dcb | 2015-07-16 10:30:48 +0200 | [diff] [blame] | 331 | >; |
| 332 | }; |
| 333 | }; |
| 334 | |
| 335 | &spi0 { |
| 336 | pinctrl-names = "default"; |
| 337 | pinctrl-0 = <&spi0_pins>; |
| 338 | status = "okay"; |
| 339 | |
| 340 | serial_flash: m25p80@0 { |
| 341 | compatible = "m25p80"; |
| 342 | spi-max-frequency = <48000000>; |
| 343 | reg = <0x0>; |
| 344 | m25p,fast-read; |
| 345 | status = "disabled"; |
| 346 | #address-cells = <1>; |
| 347 | #size-cells = <1>; |
| 348 | |
| 349 | partition@0 { |
| 350 | label = "xload"; |
| 351 | reg = <0x0 0x20000>; |
| 352 | }; |
| 353 | partition@1 { |
| 354 | label = "barebox"; |
| 355 | reg = <0x20000 0x80000>; |
| 356 | }; |
| 357 | partition@2 { |
| 358 | label = "bareboxenv"; |
| 359 | reg = <0xa0000 0x20000>; |
| 360 | }; |
| 361 | partition@3 { |
| 362 | label = "oftree"; |
| 363 | reg = <0xc0000 0x20000>; |
| 364 | }; |
| 365 | partition@4 { |
| 366 | label = "kernel"; |
| 367 | reg = <0xe0000 0x0>; |
| 368 | }; |
| 369 | }; |
| 370 | }; |