blob: 8126f12604071450bb79124ca05e76b3931914e9 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
John Crispinc06e8362013-01-20 22:00:57 +01002/*
John Crispinc06e8362013-01-20 22:00:57 +01003 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
John Crispin97b92102016-05-05 09:57:56 +02006 * Copyright (C) 2013 John Crispin <john@phrozen.org>
John Crispinc06e8362013-01-20 22:00:57 +01007 */
8
9#include <linux/pm.h>
10#include <linux/io.h>
John Crispin2a153f12013-09-04 00:16:59 +020011#include <linux/of.h>
John Crispin1a935202015-11-04 11:50:13 +010012#include <linux/delay.h>
John Crispin2a153f12013-09-04 00:16:59 +020013#include <linux/reset-controller.h>
John Crispinc06e8362013-01-20 22:00:57 +010014
15#include <asm/reboot.h>
16
17#include <asm/mach-ralink/ralink_regs.h>
18
19/* Reset Control */
John Crispin1a935202015-11-04 11:50:13 +010020#define SYSC_REG_RESET_CTRL 0x034
21
22#define RSTCTL_RESET_PCI BIT(26)
23#define RSTCTL_RESET_SYSTEM BIT(0)
John Crispinc06e8362013-01-20 22:00:57 +010024
John Crispin2a153f12013-09-04 00:16:59 +020025static int ralink_assert_device(struct reset_controller_dev *rcdev,
26 unsigned long id)
27{
28 u32 val;
29
30 if (id < 8)
31 return -1;
32
33 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
34 val |= BIT(id);
35 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
36
37 return 0;
38}
39
40static int ralink_deassert_device(struct reset_controller_dev *rcdev,
41 unsigned long id)
42{
43 u32 val;
44
45 if (id < 8)
46 return -1;
47
48 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
49 val &= ~BIT(id);
50 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
51
52 return 0;
53}
54
55static int ralink_reset_device(struct reset_controller_dev *rcdev,
56 unsigned long id)
57{
58 ralink_assert_device(rcdev, id);
59 return ralink_deassert_device(rcdev, id);
60}
61
Philipp Zabelb11d0222016-02-25 10:45:47 +010062static const struct reset_control_ops reset_ops = {
John Crispin2a153f12013-09-04 00:16:59 +020063 .reset = ralink_reset_device,
64 .assert = ralink_assert_device,
65 .deassert = ralink_deassert_device,
66};
67
68static struct reset_controller_dev reset_dev = {
69 .ops = &reset_ops,
70 .owner = THIS_MODULE,
71 .nr_resets = 32,
72 .of_reset_n_cells = 1,
73};
74
75void ralink_rst_init(void)
76{
77 reset_dev.of_node = of_find_compatible_node(NULL, NULL,
78 "ralink,rt2880-reset");
79 if (!reset_dev.of_node)
80 pr_err("Failed to find reset controller node");
81 else
82 reset_controller_register(&reset_dev);
83}
84
John Crispinc06e8362013-01-20 22:00:57 +010085static void ralink_restart(char *command)
86{
John Crispin1a935202015-11-04 11:50:13 +010087 if (IS_ENABLED(CONFIG_PCI)) {
88 rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL);
89 mdelay(50);
90 }
91
John Crispinc06e8362013-01-20 22:00:57 +010092 local_irq_disable();
93 rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
94 unreachable();
95}
96
John Crispinc06e8362013-01-20 22:00:57 +010097static int __init mips_reboot_setup(void)
98{
99 _machine_restart = ralink_restart;
John Crispinc06e8362013-01-20 22:00:57 +0100100
101 return 0;
102}
103
104arch_initcall(mips_reboot_setup);