Thomas Gleixner | 9952f69 | 2019-05-28 10:10:04 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Prashant Gaikwad | c7736ed | 2013-01-11 13:16:19 +0530 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. |
Prashant Gaikwad | c7736ed | 2013-01-11 13:16:19 +0530 | [diff] [blame] | 4 | */ |
| 5 | |
Thierry Reding | 306a7f9 | 2014-07-17 13:17:24 +0200 | [diff] [blame] | 6 | #ifndef __SOC_TEGRA_FUSE_H__ |
| 7 | #define __SOC_TEGRA_FUSE_H__ |
Prashant Gaikwad | c7736ed | 2013-01-11 13:16:19 +0530 | [diff] [blame] | 8 | |
Dmitry Osipenko | 45e9344 | 2021-09-12 23:29:02 +0300 | [diff] [blame] | 9 | #include <linux/types.h> |
| 10 | |
Thierry Reding | 304664e | 2014-07-11 09:52:41 +0200 | [diff] [blame] | 11 | #define TEGRA20 0x20 |
| 12 | #define TEGRA30 0x30 |
| 13 | #define TEGRA114 0x35 |
| 14 | #define TEGRA124 0x40 |
Thierry Reding | 24ef574 | 2015-01-08 08:24:45 +0100 | [diff] [blame] | 15 | #define TEGRA132 0x13 |
Thierry Reding | 0dc5a0d | 2015-04-29 16:55:57 +0200 | [diff] [blame] | 16 | #define TEGRA210 0x21 |
Sandipan Patra | 46011d4 | 2020-06-26 10:44:01 +0200 | [diff] [blame] | 17 | #define TEGRA186 0x18 |
| 18 | #define TEGRA194 0x19 |
Thierry Reding | 1f44feb | 2020-09-17 12:07:47 +0200 | [diff] [blame] | 19 | #define TEGRA234 0x23 |
Thierry Reding | 304664e | 2014-07-11 09:52:41 +0200 | [diff] [blame] | 20 | |
Peter De Schrijver | 783c8f4 | 2014-06-12 18:36:37 +0300 | [diff] [blame] | 21 | #define TEGRA_FUSE_SKU_CALIB_0 0xf0 |
| 22 | #define TEGRA30_FUSE_SATA_CALIB 0x124 |
Thierry Reding | 87d66f2 | 2015-11-11 18:25:02 +0100 | [diff] [blame] | 23 | #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250 |
Peter De Schrijver | 783c8f4 | 2014-06-12 18:36:37 +0300 | [diff] [blame] | 24 | |
Thierry Reding | 304664e | 2014-07-11 09:52:41 +0200 | [diff] [blame] | 25 | #ifndef __ASSEMBLY__ |
| 26 | |
Peter De Schrijver | 35874f3 | 2014-06-12 18:36:36 +0300 | [diff] [blame] | 27 | enum tegra_revision { |
| 28 | TEGRA_REVISION_UNKNOWN = 0, |
| 29 | TEGRA_REVISION_A01, |
| 30 | TEGRA_REVISION_A02, |
| 31 | TEGRA_REVISION_A03, |
| 32 | TEGRA_REVISION_A03p, |
| 33 | TEGRA_REVISION_A04, |
| 34 | TEGRA_REVISION_MAX, |
| 35 | }; |
| 36 | |
Peter De Schrijver | 783c8f4 | 2014-06-12 18:36:37 +0300 | [diff] [blame] | 37 | struct tegra_sku_info { |
| 38 | int sku_id; |
| 39 | int cpu_process_id; |
| 40 | int cpu_speedo_id; |
| 41 | int cpu_speedo_value; |
| 42 | int cpu_iddq_value; |
Thierry Reding | 03b3f4c | 2015-03-23 14:44:08 +0100 | [diff] [blame] | 43 | int soc_process_id; |
Peter De Schrijver | 783c8f4 | 2014-06-12 18:36:37 +0300 | [diff] [blame] | 44 | int soc_speedo_id; |
Thierry Reding | 0dc5a0d | 2015-04-29 16:55:57 +0200 | [diff] [blame] | 45 | int soc_speedo_value; |
Peter De Schrijver | 783c8f4 | 2014-06-12 18:36:37 +0300 | [diff] [blame] | 46 | int gpu_process_id; |
Thierry Reding | 0dc5a0d | 2015-04-29 16:55:57 +0200 | [diff] [blame] | 47 | int gpu_speedo_id; |
Peter De Schrijver | 783c8f4 | 2014-06-12 18:36:37 +0300 | [diff] [blame] | 48 | int gpu_speedo_value; |
| 49 | enum tegra_revision revision; |
| 50 | }; |
| 51 | |
Dmitry Osipenko | 30b44e8 | 2021-05-28 02:54:04 +0300 | [diff] [blame] | 52 | #ifdef CONFIG_ARCH_TEGRA |
| 53 | extern struct tegra_sku_info tegra_sku_info; |
Peter De Schrijver | 35874f3 | 2014-06-12 18:36:36 +0300 | [diff] [blame] | 54 | u32 tegra_read_straps(void); |
Mikko Perttunen | 6ea2609 | 2015-03-12 15:47:55 +0100 | [diff] [blame] | 55 | u32 tegra_read_ram_code(void); |
Peter De Schrijver | 783c8f4 | 2014-06-12 18:36:37 +0300 | [diff] [blame] | 56 | int tegra_fuse_readl(unsigned long offset, u32 *value); |
Dmitry Osipenko | 45e9344 | 2021-09-12 23:29:02 +0300 | [diff] [blame] | 57 | u32 tegra_read_chipid(void); |
| 58 | u8 tegra_get_chip_id(void); |
| 59 | u8 tegra_get_platform(void); |
| 60 | bool tegra_is_silicon(void); |
Dmitry Osipenko | 245157a | 2020-11-04 19:48:39 +0300 | [diff] [blame] | 61 | #else |
| 62 | static struct tegra_sku_info tegra_sku_info __maybe_unused; |
Dmitry Osipenko | 30b44e8 | 2021-05-28 02:54:04 +0300 | [diff] [blame] | 63 | |
| 64 | static inline u32 tegra_read_straps(void) |
| 65 | { |
| 66 | return 0; |
| 67 | } |
| 68 | |
| 69 | static inline u32 tegra_read_ram_code(void) |
| 70 | { |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | static inline int tegra_fuse_readl(unsigned long offset, u32 *value) |
| 75 | { |
| 76 | return -ENODEV; |
| 77 | } |
Dmitry Osipenko | 45e9344 | 2021-09-12 23:29:02 +0300 | [diff] [blame] | 78 | |
| 79 | static inline u32 tegra_read_chipid(void) |
| 80 | { |
| 81 | return 0; |
| 82 | } |
| 83 | |
| 84 | static inline u8 tegra_get_chip_id(void) |
| 85 | { |
| 86 | return 0; |
| 87 | } |
| 88 | |
| 89 | static inline u8 tegra_get_platform(void) |
| 90 | { |
| 91 | return 0; |
| 92 | } |
| 93 | |
| 94 | static inline bool tegra_is_silicon(void) |
| 95 | { |
| 96 | return false; |
| 97 | } |
Dmitry Osipenko | 245157a | 2020-11-04 19:48:39 +0300 | [diff] [blame] | 98 | #endif |
Peter De Schrijver | 35874f3 | 2014-06-12 18:36:36 +0300 | [diff] [blame] | 99 | |
Thierry Reding | 27a0342 | 2017-08-17 16:42:17 +0200 | [diff] [blame] | 100 | struct device *tegra_soc_device_register(void); |
| 101 | |
Thierry Reding | 304664e | 2014-07-11 09:52:41 +0200 | [diff] [blame] | 102 | #endif /* __ASSEMBLY__ */ |
Prashant Gaikwad | c7736ed | 2013-01-11 13:16:19 +0530 | [diff] [blame] | 103 | |
Thierry Reding | 306a7f9 | 2014-07-17 13:17:24 +0200 | [diff] [blame] | 104 | #endif /* __SOC_TEGRA_FUSE_H__ */ |