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Thomas Gleixner9952f692019-05-28 10:10:04 -07001/* SPDX-License-Identifier: GPL-2.0-only */
Prashant Gaikwadc7736ed2013-01-11 13:16:19 +05302/*
3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
Prashant Gaikwadc7736ed2013-01-11 13:16:19 +05304 */
5
Thierry Reding306a7f92014-07-17 13:17:24 +02006#ifndef __SOC_TEGRA_FUSE_H__
7#define __SOC_TEGRA_FUSE_H__
Prashant Gaikwadc7736ed2013-01-11 13:16:19 +05308
Dmitry Osipenko45e93442021-09-12 23:29:02 +03009#include <linux/types.h>
10
Thierry Reding304664e2014-07-11 09:52:41 +020011#define TEGRA20 0x20
12#define TEGRA30 0x30
13#define TEGRA114 0x35
14#define TEGRA124 0x40
Thierry Reding24ef5742015-01-08 08:24:45 +010015#define TEGRA132 0x13
Thierry Reding0dc5a0d2015-04-29 16:55:57 +020016#define TEGRA210 0x21
Sandipan Patra46011d42020-06-26 10:44:01 +020017#define TEGRA186 0x18
18#define TEGRA194 0x19
Thierry Reding1f44feb2020-09-17 12:07:47 +020019#define TEGRA234 0x23
Thierry Reding304664e2014-07-11 09:52:41 +020020
Peter De Schrijver783c8f42014-06-12 18:36:37 +030021#define TEGRA_FUSE_SKU_CALIB_0 0xf0
22#define TEGRA30_FUSE_SATA_CALIB 0x124
Thierry Reding87d66f22015-11-11 18:25:02 +010023#define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
Peter De Schrijver783c8f42014-06-12 18:36:37 +030024
Thierry Reding304664e2014-07-11 09:52:41 +020025#ifndef __ASSEMBLY__
26
Peter De Schrijver35874f32014-06-12 18:36:36 +030027enum tegra_revision {
28 TEGRA_REVISION_UNKNOWN = 0,
29 TEGRA_REVISION_A01,
30 TEGRA_REVISION_A02,
31 TEGRA_REVISION_A03,
32 TEGRA_REVISION_A03p,
33 TEGRA_REVISION_A04,
34 TEGRA_REVISION_MAX,
35};
36
Peter De Schrijver783c8f42014-06-12 18:36:37 +030037struct tegra_sku_info {
38 int sku_id;
39 int cpu_process_id;
40 int cpu_speedo_id;
41 int cpu_speedo_value;
42 int cpu_iddq_value;
Thierry Reding03b3f4c2015-03-23 14:44:08 +010043 int soc_process_id;
Peter De Schrijver783c8f42014-06-12 18:36:37 +030044 int soc_speedo_id;
Thierry Reding0dc5a0d2015-04-29 16:55:57 +020045 int soc_speedo_value;
Peter De Schrijver783c8f42014-06-12 18:36:37 +030046 int gpu_process_id;
Thierry Reding0dc5a0d2015-04-29 16:55:57 +020047 int gpu_speedo_id;
Peter De Schrijver783c8f42014-06-12 18:36:37 +030048 int gpu_speedo_value;
49 enum tegra_revision revision;
50};
51
Dmitry Osipenko30b44e82021-05-28 02:54:04 +030052#ifdef CONFIG_ARCH_TEGRA
53extern struct tegra_sku_info tegra_sku_info;
Peter De Schrijver35874f32014-06-12 18:36:36 +030054u32 tegra_read_straps(void);
Mikko Perttunen6ea26092015-03-12 15:47:55 +010055u32 tegra_read_ram_code(void);
Peter De Schrijver783c8f42014-06-12 18:36:37 +030056int tegra_fuse_readl(unsigned long offset, u32 *value);
Dmitry Osipenko45e93442021-09-12 23:29:02 +030057u32 tegra_read_chipid(void);
58u8 tegra_get_chip_id(void);
59u8 tegra_get_platform(void);
60bool tegra_is_silicon(void);
Dmitry Osipenko245157a2020-11-04 19:48:39 +030061#else
62static struct tegra_sku_info tegra_sku_info __maybe_unused;
Dmitry Osipenko30b44e82021-05-28 02:54:04 +030063
64static inline u32 tegra_read_straps(void)
65{
66 return 0;
67}
68
69static inline u32 tegra_read_ram_code(void)
70{
71 return 0;
72}
73
74static inline int tegra_fuse_readl(unsigned long offset, u32 *value)
75{
76 return -ENODEV;
77}
Dmitry Osipenko45e93442021-09-12 23:29:02 +030078
79static inline u32 tegra_read_chipid(void)
80{
81 return 0;
82}
83
84static inline u8 tegra_get_chip_id(void)
85{
86 return 0;
87}
88
89static inline u8 tegra_get_platform(void)
90{
91 return 0;
92}
93
94static inline bool tegra_is_silicon(void)
95{
96 return false;
97}
Dmitry Osipenko245157a2020-11-04 19:48:39 +030098#endif
Peter De Schrijver35874f32014-06-12 18:36:36 +030099
Thierry Reding27a03422017-08-17 16:42:17 +0200100struct device *tegra_soc_device_register(void);
101
Thierry Reding304664e2014-07-11 09:52:41 +0200102#endif /* __ASSEMBLY__ */
Prashant Gaikwadc7736ed2013-01-11 13:16:19 +0530103
Thierry Reding306a7f92014-07-17 13:17:24 +0200104#endif /* __SOC_TEGRA_FUSE_H__ */