blob: 68ed7fd642569d14dabf6cc27160ebcd70cf2fa4 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Shadi Ammouri60cadec2008-08-05 13:01:09 -07002/*
Grant Likelyca632f52011-06-06 01:16:30 -06003 * Marvell Orion SPI controller driver
Shadi Ammouri60cadec2008-08-05 13:01:09 -07004 *
5 * Author: Shadi Ammouri <shadi@marvell.com>
6 * Copyright (C) 2007-2008 Marvell Ltd.
Shadi Ammouri60cadec2008-08-05 13:01:09 -07007 */
8
Shadi Ammouri60cadec2008-08-05 13:01:09 -07009#include <linux/interrupt.h>
10#include <linux/delay.h>
11#include <linux/platform_device.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/spi/spi.h>
Paul Gortmakerd7614de2011-07-03 15:44:29 -040015#include <linux/module.h>
Russell King5c6786942014-06-21 12:22:37 +010016#include <linux/pm_runtime.h>
Andrew Lunnf814f9a2012-07-23 12:08:09 +020017#include <linux/of.h>
Stefan Roeseb3c195b2016-05-19 09:07:05 +020018#include <linux/of_address.h>
Greg Ungererdf59fa72014-09-28 23:24:04 +100019#include <linux/of_device.h>
Andrew Lunn4574b882012-04-06 17:17:26 +020020#include <linux/clk.h>
Mark Brown895248f2013-07-29 05:10:21 +010021#include <linux/sizes.h>
Shadi Ammouri60cadec2008-08-05 13:01:09 -070022#include <asm/unaligned.h>
23
24#define DRIVER_NAME "orion_spi"
25
Russell King5c6786942014-06-21 12:22:37 +010026/* Runtime PM autosuspend timeout: PM is fairly light on this driver */
27#define SPI_AUTOSUSPEND_TIMEOUT 200
28
Ken Wilson23244402015-01-16 13:10:47 +100029/* Some SoCs using this driver support up to 8 chip selects.
30 * It is up to the implementer to only use the chip selects
31 * that are available.
32 */
33#define ORION_NUM_CHIPSELECTS 8
34
Shadi Ammouri60cadec2008-08-05 13:01:09 -070035#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
36
37#define ORION_SPI_IF_CTRL_REG 0x00
38#define ORION_SPI_IF_CONFIG_REG 0x04
Bastian Stender1017f422017-04-07 15:52:33 +020039#define ORION_SPI_IF_RXLSBF BIT(14)
40#define ORION_SPI_IF_TXLSBF BIT(13)
Shadi Ammouri60cadec2008-08-05 13:01:09 -070041#define ORION_SPI_DATA_OUT_REG 0x08
42#define ORION_SPI_DATA_IN_REG 0x0c
43#define ORION_SPI_INT_CAUSE_REG 0x10
Nadav Haklai38d62112015-08-11 11:58:47 +020044#define ORION_SPI_TIMING_PARAMS_REG 0x18
45
Stefan Roeseb3c195b2016-05-19 09:07:05 +020046/* Register for the "Direct Mode" */
47#define SPI_DIRECT_WRITE_CONFIG_REG 0x20
48
Nadav Haklai38d62112015-08-11 11:58:47 +020049#define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6)
50#define ORION_SPI_TMISO_SAMPLE_1 (1 << 6)
51#define ORION_SPI_TMISO_SAMPLE_2 (2 << 6)
Shadi Ammouri60cadec2008-08-05 13:01:09 -070052
Jason Gunthorpeb15d5d72012-11-21 12:23:35 -070053#define ORION_SPI_MODE_CPOL (1 << 11)
54#define ORION_SPI_MODE_CPHA (1 << 12)
Shadi Ammouri60cadec2008-08-05 13:01:09 -070055#define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
56#define ORION_SPI_CLK_PRESCALE_MASK 0x1F
Greg Ungererdf59fa72014-09-28 23:24:04 +100057#define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
Jason Gunthorpeb15d5d72012-11-21 12:23:35 -070058#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
59 ORION_SPI_MODE_CPHA)
Ken Wilson23244402015-01-16 13:10:47 +100060#define ORION_SPI_CS_MASK 0x1C
61#define ORION_SPI_CS_SHIFT 2
62#define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
63 ORION_SPI_CS_MASK)
Shadi Ammouri60cadec2008-08-05 13:01:09 -070064
Greg Ungererdf59fa72014-09-28 23:24:04 +100065enum orion_spi_type {
66 ORION_SPI,
67 ARMADA_SPI,
68};
69
70struct orion_spi_dev {
71 enum orion_spi_type typ;
Gregory CLEMENTce2f6ea2015-05-26 11:44:42 +020072 /*
73 * min_divisor and max_hz should be exclusive, the only we can
74 * have both is for managing the armada-370-spi case with old
75 * device tree
76 */
77 unsigned long max_hz;
Greg Ungererdf59fa72014-09-28 23:24:04 +100078 unsigned int min_divisor;
79 unsigned int max_divisor;
80 u32 prescale_mask;
Nadav Haklai38d62112015-08-11 11:58:47 +020081 bool is_errata_50mhz_ac;
Greg Ungererdf59fa72014-09-28 23:24:04 +100082};
83
Stefan Roeseb3c195b2016-05-19 09:07:05 +020084struct orion_direct_acc {
85 void __iomem *vaddr;
86 u32 size;
87};
88
Jan Kundrát5c22af72018-02-10 12:20:23 +010089struct orion_child_options {
90 struct orion_direct_acc direct_access;
91};
92
Shadi Ammouri60cadec2008-08-05 13:01:09 -070093struct orion_spi {
Shadi Ammouri60cadec2008-08-05 13:01:09 -070094 struct spi_master *master;
95 void __iomem *base;
Andrew Lunn4574b882012-04-06 17:17:26 +020096 struct clk *clk;
Gregory CLEMENT92ae1122018-01-12 11:42:33 +010097 struct clk *axi_clk;
Greg Ungererdf59fa72014-09-28 23:24:04 +100098 const struct orion_spi_dev *devdata;
Marcin Wojtase2be7032020-12-23 12:38:26 +020099 struct device *dev;
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200100
Jan Kundrát5c22af72018-02-10 12:20:23 +0100101 struct orion_child_options child[ORION_NUM_CHIPSELECTS];
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700102};
103
Marcin Wojtase2be7032020-12-23 12:38:26 +0200104#ifdef CONFIG_PM
105static int orion_spi_runtime_suspend(struct device *dev);
106static int orion_spi_runtime_resume(struct device *dev);
107#endif
108
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700109static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
110{
111 return orion_spi->base + reg;
112}
113
114static inline void
115orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
116{
117 void __iomem *reg_addr = spi_reg(orion_spi, reg);
118 u32 val;
119
120 val = readl(reg_addr);
121 val |= mask;
122 writel(val, reg_addr);
123}
124
125static inline void
126orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
127{
128 void __iomem *reg_addr = spi_reg(orion_spi, reg);
129 u32 val;
130
131 val = readl(reg_addr);
132 val &= ~mask;
133 writel(val, reg_addr);
134}
135
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700136static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
137{
138 u32 tclk_hz;
139 u32 rate;
140 u32 prescale;
141 u32 reg;
142 struct orion_spi *orion_spi;
Greg Ungererdf59fa72014-09-28 23:24:04 +1000143 const struct orion_spi_dev *devdata;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700144
145 orion_spi = spi_master_get_devdata(spi->master);
Greg Ungererdf59fa72014-09-28 23:24:04 +1000146 devdata = orion_spi->devdata;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700147
Andrew Lunn4574b882012-04-06 17:17:26 +0200148 tclk_hz = clk_get_rate(orion_spi->clk);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700149
Greg Ungererdf59fa72014-09-28 23:24:04 +1000150 if (devdata->typ == ARMADA_SPI) {
Uwe Kleine-König7243e0b2016-12-08 17:37:08 +0100151 /*
152 * Given the core_clk (tclk_hz) and the target rate (speed) we
153 * determine the best values for SPR (in [0 .. 15]) and SPPR (in
154 * [0..7]) such that
155 *
156 * core_clk / (SPR * 2 ** SPPR)
157 *
158 * is as big as possible but not bigger than speed.
159 */
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700160
Uwe Kleine-König7243e0b2016-12-08 17:37:08 +0100161 /* best integer divider: */
162 unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
163 unsigned spr, sppr;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700164
Uwe Kleine-König7243e0b2016-12-08 17:37:08 +0100165 if (divider < 16) {
166 /* This is the easy case, divider is less than 16 */
167 spr = divider;
168 sppr = 0;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700169
Uwe Kleine-König7243e0b2016-12-08 17:37:08 +0100170 } else {
171 unsigned two_pow_sppr;
172 /*
173 * Find the highest bit set in divider. This and the
174 * three next bits define SPR (apart from rounding).
175 * SPPR is then the number of zero bits that must be
176 * appended:
177 */
178 sppr = fls(divider) - 4;
Greg Ungererdf59fa72014-09-28 23:24:04 +1000179
Uwe Kleine-König7243e0b2016-12-08 17:37:08 +0100180 /*
181 * As SPR only has 4 bits, we have to round divider up
182 * to the next multiple of 2 ** sppr.
183 */
184 two_pow_sppr = 1 << sppr;
185 divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
Greg Ungererdf59fa72014-09-28 23:24:04 +1000186
Uwe Kleine-König7243e0b2016-12-08 17:37:08 +0100187 /*
188 * recalculate sppr as rounding up divider might have
189 * increased it enough to change the position of the
190 * highest set bit. In this case the bit that now
191 * doesn't make it into SPR is 0, so there is no need to
192 * round again.
193 */
194 sppr = fls(divider) - 4;
195 spr = divider >> sppr;
196
197 /*
198 * Now do range checking. SPR is constructed to have a
199 * width of 4 bits, so this is fine for sure. So we
200 * still need to check for sppr to fit into 3 bits:
201 */
202 if (sppr > 7)
203 return -EINVAL;
Greg Ungererdf59fa72014-09-28 23:24:04 +1000204 }
205
Uwe Kleine-König7243e0b2016-12-08 17:37:08 +0100206 prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
Greg Ungererdf59fa72014-09-28 23:24:04 +1000207 } else {
208 /*
209 * the supported rates are: 4,6,8...30
210 * round up as we look for equal or less speed
211 */
212 rate = DIV_ROUND_UP(tclk_hz, speed);
213 rate = roundup(rate, 2);
214
215 /* check if requested speed is too small */
216 if (rate > 30)
217 return -EINVAL;
218
219 if (rate < 4)
220 rate = 4;
221
222 /* Convert the rate to SPI clock divisor value. */
223 prescale = 0x10 + rate/2;
224 }
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700225
226 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
Greg Ungererdf59fa72014-09-28 23:24:04 +1000227 reg = ((reg & ~devdata->prescale_mask) | prescale);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700228 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
229
230 return 0;
231}
232
Jason Gunthorpeb15d5d72012-11-21 12:23:35 -0700233static void
234orion_spi_mode_set(struct spi_device *spi)
235{
236 u32 reg;
237 struct orion_spi *orion_spi;
238
239 orion_spi = spi_master_get_devdata(spi->master);
240
241 reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
242 reg &= ~ORION_SPI_MODE_MASK;
243 if (spi->mode & SPI_CPOL)
244 reg |= ORION_SPI_MODE_CPOL;
245 if (spi->mode & SPI_CPHA)
246 reg |= ORION_SPI_MODE_CPHA;
Bastian Stender1017f422017-04-07 15:52:33 +0200247 if (spi->mode & SPI_LSB_FIRST)
248 reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF;
249 else
250 reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF);
251
Jason Gunthorpeb15d5d72012-11-21 12:23:35 -0700252 writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
253}
254
Nadav Haklai38d62112015-08-11 11:58:47 +0200255static void
256orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
257{
258 u32 reg;
259 struct orion_spi *orion_spi;
260
261 orion_spi = spi_master_get_devdata(spi->master);
262
263 /*
264 * Erratum description: (Erratum NO. FE-9144572) The device
265 * SPI interface supports frequencies of up to 50 MHz.
266 * However, due to this erratum, when the device core clock is
267 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
268 * clock and CPOL=CPHA=1 there might occur data corruption on
269 * reads from the SPI device.
270 * Erratum Workaround:
271 * Work in one of the following configurations:
272 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
273 * Register".
274 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
275 * Register" before setting the interface.
276 */
277 reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
278 reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
279
280 if (clk_get_rate(orion_spi->clk) == 250000000 &&
281 speed == 50000000 && spi->mode & SPI_CPOL &&
282 spi->mode & SPI_CPHA)
283 reg |= ORION_SPI_TMISO_SAMPLE_2;
284 else
285 reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
286
287 writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
288}
289
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700290/*
291 * called only when no transfer is active on the bus
292 */
293static int
294orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
295{
296 struct orion_spi *orion_spi;
297 unsigned int speed = spi->max_speed_hz;
298 unsigned int bits_per_word = spi->bits_per_word;
299 int rc;
300
301 orion_spi = spi_master_get_devdata(spi->master);
302
303 if ((t != NULL) && t->speed_hz)
304 speed = t->speed_hz;
305
306 if ((t != NULL) && t->bits_per_word)
307 bits_per_word = t->bits_per_word;
308
Jason Gunthorpeb15d5d72012-11-21 12:23:35 -0700309 orion_spi_mode_set(spi);
310
Nadav Haklai38d62112015-08-11 11:58:47 +0200311 if (orion_spi->devdata->is_errata_50mhz_ac)
312 orion_spi_50mhz_ac_timing_erratum(spi, speed);
313
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700314 rc = orion_spi_baudrate_set(spi, speed);
315 if (rc)
316 return rc;
317
Axel Lin495b3352014-02-11 20:51:36 +0800318 if (bits_per_word == 16)
319 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
320 ORION_SPI_IF_8_16_BIT_MODE);
321 else
322 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
323 ORION_SPI_IF_8_16_BIT_MODE);
324
325 return 0;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700326}
327
Ken Wilson75872eb2015-01-12 13:13:59 +1000328static void orion_spi_set_cs(struct spi_device *spi, bool enable)
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700329{
Ken Wilson75872eb2015-01-12 13:13:59 +1000330 struct orion_spi *orion_spi;
Chris Packhamb28b9142017-05-23 16:03:21 +1200331
Jan Kundrát544248622018-01-26 23:56:10 +0100332 orion_spi = spi_master_get_devdata(spi->master);
333
Linus Walleij66eb2282020-04-15 19:56:13 +0200334 /*
335 * If this line is using a GPIO to control chip select, this internal
336 * .set_cs() function will still be called, so we clear any previous
337 * chip select. The CS we activate will not have any elecrical effect,
338 * as it is handled by a GPIO, but that doesn't matter. What we need
339 * is to deassert the old chip select and assert some other chip select.
340 */
Ken Wilson23244402015-01-16 13:10:47 +1000341 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
342 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
Linus Walleij66eb2282020-04-15 19:56:13 +0200343 ORION_SPI_CS(spi->chip_select));
Ken Wilson23244402015-01-16 13:10:47 +1000344
Linus Walleij66eb2282020-04-15 19:56:13 +0200345 /*
346 * Chip select logic is inverted from spi_set_cs(). For lines using a
347 * GPIO to do chip select SPI_CS_HIGH is enforced and inversion happens
348 * in the GPIO library, but we don't care about that, because in those
349 * cases we are dealing with an unused native CS anyways so the polarity
350 * doesn't matter.
351 */
Ken Wilson75872eb2015-01-12 13:13:59 +1000352 if (!enable)
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700353 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
354 else
355 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
356}
357
358static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
359{
360 int i;
361
362 for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
363 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
364 return 1;
Jingoo Hanb8434042014-09-02 11:51:39 +0900365
366 udelay(1);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700367 }
368
369 return -1;
370}
371
372static inline int
373orion_spi_write_read_8bit(struct spi_device *spi,
374 const u8 **tx_buf, u8 **rx_buf)
375{
376 void __iomem *tx_reg, *rx_reg, *int_reg;
377 struct orion_spi *orion_spi;
Marcin Wojtas22a6d412020-12-23 12:38:27 +0200378 bool cs_single_byte;
379
380 cs_single_byte = spi->mode & SPI_CS_WORD;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700381
382 orion_spi = spi_master_get_devdata(spi->master);
Marcin Wojtas22a6d412020-12-23 12:38:27 +0200383
384 if (cs_single_byte)
385 orion_spi_set_cs(spi, 0);
386
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700387 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
388 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
389 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
390
391 /* clear the interrupt cause register */
392 writel(0x0, int_reg);
393
394 if (tx_buf && *tx_buf)
395 writel(*(*tx_buf)++, tx_reg);
396 else
397 writel(0, tx_reg);
398
399 if (orion_spi_wait_till_ready(orion_spi) < 0) {
Marcin Wojtas22a6d412020-12-23 12:38:27 +0200400 if (cs_single_byte) {
401 orion_spi_set_cs(spi, 1);
402 /* Satisfy some SLIC devices requirements */
403 udelay(4);
404 }
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700405 dev_err(&spi->dev, "TXS timed out\n");
406 return -1;
407 }
408
409 if (rx_buf && *rx_buf)
410 *(*rx_buf)++ = readl(rx_reg);
411
Marcin Wojtas22a6d412020-12-23 12:38:27 +0200412 if (cs_single_byte) {
413 orion_spi_set_cs(spi, 1);
414 /* Satisfy some SLIC devices requirements */
415 udelay(4);
416 }
417
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700418 return 1;
419}
420
421static inline int
422orion_spi_write_read_16bit(struct spi_device *spi,
423 const u16 **tx_buf, u16 **rx_buf)
424{
425 void __iomem *tx_reg, *rx_reg, *int_reg;
426 struct orion_spi *orion_spi;
427
Marcin Wojtas22a6d412020-12-23 12:38:27 +0200428 if (spi->mode & SPI_CS_WORD) {
429 dev_err(&spi->dev, "SPI_CS_WORD is only supported for 8 bit words\n");
430 return -1;
431 }
432
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700433 orion_spi = spi_master_get_devdata(spi->master);
434 tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
435 rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
436 int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
437
438 /* clear the interrupt cause register */
439 writel(0x0, int_reg);
440
441 if (tx_buf && *tx_buf)
442 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
443 else
444 writel(0, tx_reg);
445
446 if (orion_spi_wait_till_ready(orion_spi) < 0) {
447 dev_err(&spi->dev, "TXS timed out\n");
448 return -1;
449 }
450
451 if (rx_buf && *rx_buf)
452 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
453
454 return 1;
455}
456
457static unsigned int
458orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
459{
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700460 unsigned int count;
461 int word_len;
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200462 struct orion_spi *orion_spi;
463 int cs = spi->chip_select;
Kosta Zertsekelc7ba4732018-08-15 22:04:49 +0300464 void __iomem *vaddr;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700465
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700466 word_len = spi->bits_per_word;
467 count = xfer->len;
468
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200469 orion_spi = spi_master_get_devdata(spi->master);
470
471 /*
Marcin Wojtas22a6d412020-12-23 12:38:27 +0200472 * Use SPI direct write mode if base address is available
473 * and SPI_CS_WORD flag is not set.
474 * Otherwise fall back to PIO mode for this transfer.
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200475 */
Kosta Zertsekelc7ba4732018-08-15 22:04:49 +0300476 vaddr = orion_spi->child[cs].direct_access.vaddr;
477
Marcin Wojtas22a6d412020-12-23 12:38:27 +0200478 if (vaddr && xfer->tx_buf && word_len == 8 && (spi->mode & SPI_CS_WORD) == 0) {
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200479 unsigned int cnt = count / 4;
480 unsigned int rem = count % 4;
481
482 /*
483 * Send the TX-data to the SPI device via the direct
484 * mapped address window
485 */
Kosta Zertsekelc7ba4732018-08-15 22:04:49 +0300486 iowrite32_rep(vaddr, xfer->tx_buf, cnt);
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200487 if (rem) {
488 u32 *buf = (u32 *)xfer->tx_buf;
489
Kosta Zertsekelc7ba4732018-08-15 22:04:49 +0300490 iowrite8_rep(vaddr, &buf[cnt], rem);
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200491 }
492
493 return count;
494 }
495
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700496 if (word_len == 8) {
497 const u8 *tx = xfer->tx_buf;
498 u8 *rx = xfer->rx_buf;
499
500 do {
501 if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
502 goto out;
503 count--;
Alexandru Ardelean21e26062019-09-26 13:51:33 +0300504 spi_delay_exec(&xfer->word_delay, xfer);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700505 } while (count);
506 } else if (word_len == 16) {
507 const u16 *tx = xfer->tx_buf;
508 u16 *rx = xfer->rx_buf;
509
510 do {
511 if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
512 goto out;
513 count -= 2;
Alexandru Ardelean21e26062019-09-26 13:51:33 +0300514 spi_delay_exec(&xfer->word_delay, xfer);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700515 } while (count);
516 }
517
518out:
519 return xfer->len - count;
520}
521
Ken Wilson75872eb2015-01-12 13:13:59 +1000522static int orion_spi_transfer_one(struct spi_master *master,
523 struct spi_device *spi,
524 struct spi_transfer *t)
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700525{
Andrew Lunnba59a802012-07-23 13:16:55 +0200526 int status = 0;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700527
Ken Wilson75872eb2015-01-12 13:13:59 +1000528 status = orion_spi_setup_transfer(spi, t);
Andrew Lunnba59a802012-07-23 13:16:55 +0200529 if (status < 0)
Ken Wilson75872eb2015-01-12 13:13:59 +1000530 return status;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700531
Ken Wilson75872eb2015-01-12 13:13:59 +1000532 if (t->len)
533 orion_spi_write_read(spi, t);
Andrew Lunnba59a802012-07-23 13:16:55 +0200534
Ken Wilson75872eb2015-01-12 13:13:59 +1000535 return status;
536}
Andrew Lunnba59a802012-07-23 13:16:55 +0200537
Ken Wilson75872eb2015-01-12 13:13:59 +1000538static int orion_spi_setup(struct spi_device *spi)
539{
Marcin Wojtase2be7032020-12-23 12:38:26 +0200540 int ret;
541#ifdef CONFIG_PM
542 struct orion_spi *orion_spi = spi_master_get_devdata(spi->master);
543 struct device *dev = orion_spi->dev;
544
545 orion_spi_runtime_resume(dev);
546#endif
547
548 ret = orion_spi_setup_transfer(spi, NULL);
549
550#ifdef CONFIG_PM
551 orion_spi_runtime_suspend(dev);
552#endif
553
554 return ret;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700555}
556
Grant Likely2deff8d2013-02-05 13:27:35 +0000557static int orion_spi_reset(struct orion_spi *orion_spi)
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700558{
559 /* Verify that the CS is deasserted */
Ken Wilson75872eb2015-01-12 13:13:59 +1000560 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200561
562 /* Don't deassert CS between the direct mapped SPI transfers */
563 writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG));
564
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700565 return 0;
566}
567
Greg Ungererdf59fa72014-09-28 23:24:04 +1000568static const struct orion_spi_dev orion_spi_dev_data = {
569 .typ = ORION_SPI,
570 .min_divisor = 4,
571 .max_divisor = 30,
572 .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
573};
574
Gregory CLEMENT4dacccf2015-05-26 11:44:43 +0200575static const struct orion_spi_dev armada_370_spi_dev_data = {
Greg Ungererdf59fa72014-09-28 23:24:04 +1000576 .typ = ARMADA_SPI,
Gregory CLEMENTce2f6ea2015-05-26 11:44:42 +0200577 .min_divisor = 4,
Greg Ungererdf59fa72014-09-28 23:24:04 +1000578 .max_divisor = 1920,
Gregory CLEMENTce2f6ea2015-05-26 11:44:42 +0200579 .max_hz = 50000000,
Greg Ungererdf59fa72014-09-28 23:24:04 +1000580 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
581};
582
Gregory CLEMENT4dacccf2015-05-26 11:44:43 +0200583static const struct orion_spi_dev armada_xp_spi_dev_data = {
584 .typ = ARMADA_SPI,
585 .max_hz = 50000000,
586 .max_divisor = 1920,
587 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
588};
589
590static const struct orion_spi_dev armada_375_spi_dev_data = {
591 .typ = ARMADA_SPI,
592 .min_divisor = 15,
593 .max_divisor = 1920,
594 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
595};
596
Nadav Haklai38d62112015-08-11 11:58:47 +0200597static const struct orion_spi_dev armada_380_spi_dev_data = {
598 .typ = ARMADA_SPI,
599 .max_hz = 50000000,
600 .max_divisor = 1920,
601 .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
602 .is_errata_50mhz_ac = true,
603};
604
Greg Ungererdf59fa72014-09-28 23:24:04 +1000605static const struct of_device_id orion_spi_of_match_table[] = {
Gregory CLEMENT4dacccf2015-05-26 11:44:43 +0200606 {
607 .compatible = "marvell,orion-spi",
608 .data = &orion_spi_dev_data,
609 },
610 {
611 .compatible = "marvell,armada-370-spi",
612 .data = &armada_370_spi_dev_data,
613 },
614 {
615 .compatible = "marvell,armada-375-spi",
616 .data = &armada_375_spi_dev_data,
617 },
618 {
619 .compatible = "marvell,armada-380-spi",
Nadav Haklai38d62112015-08-11 11:58:47 +0200620 .data = &armada_380_spi_dev_data,
Gregory CLEMENT4dacccf2015-05-26 11:44:43 +0200621 },
622 {
623 .compatible = "marvell,armada-390-spi",
624 .data = &armada_xp_spi_dev_data,
625 },
626 {
627 .compatible = "marvell,armada-xp-spi",
628 .data = &armada_xp_spi_dev_data,
629 },
630
Greg Ungererdf59fa72014-09-28 23:24:04 +1000631 {}
632};
633MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
634
Grant Likely2deff8d2013-02-05 13:27:35 +0000635static int orion_spi_probe(struct platform_device *pdev)
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700636{
Greg Ungererdf59fa72014-09-28 23:24:04 +1000637 const struct of_device_id *of_id;
638 const struct orion_spi_dev *devdata;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700639 struct spi_master *master;
640 struct orion_spi *spi;
641 struct resource *r;
Andrew Lunn4574b882012-04-06 17:17:26 +0200642 unsigned long tclk_hz;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700643 int status = 0;
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200644 struct device_node *np;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700645
Jingoo Han3fed8062013-10-14 10:35:08 +0900646 master = spi_alloc_master(&pdev->dev, sizeof(*spi));
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700647 if (master == NULL) {
648 dev_dbg(&pdev->dev, "master allocation failed\n");
649 return -ENOMEM;
650 }
651
652 if (pdev->id != -1)
653 master->bus_num = pdev->id;
Andrew Lunnf814f9a2012-07-23 12:08:09 +0200654 if (pdev->dev.of_node) {
Thomas Petazzonie06871c2014-07-27 23:53:19 +0200655 u32 cell_index;
Jingoo Hanb8434042014-09-02 11:51:39 +0900656
Thomas Petazzonie06871c2014-07-27 23:53:19 +0200657 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
658 &cell_index))
659 master->bus_num = cell_index;
Andrew Lunnf814f9a2012-07-23 12:08:09 +0200660 }
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700661
Bastian Stender1017f422017-04-07 15:52:33 +0200662 /* we support all 4 SPI modes and LSB first option */
Marcin Wojtas22a6d412020-12-23 12:38:27 +0200663 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_CS_WORD;
Ken Wilson75872eb2015-01-12 13:13:59 +1000664 master->set_cs = orion_spi_set_cs;
665 master->transfer_one = orion_spi_transfer_one;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700666 master->num_chipselect = ORION_NUM_CHIPSELECTS;
Ken Wilson75872eb2015-01-12 13:13:59 +1000667 master->setup = orion_spi_setup;
Axel Lin495b3352014-02-11 20:51:36 +0800668 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
Russell King5c6786942014-06-21 12:22:37 +0100669 master->auto_runtime_pm = true;
Linus Walleij66eb2282020-04-15 19:56:13 +0200670 master->use_gpio_descriptors = true;
Chris Packhamb28b9142017-05-23 16:03:21 +1200671 master->flags = SPI_MASTER_GPIO_SS;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700672
Jingoo Han24b5a822013-05-23 19:20:40 +0900673 platform_set_drvdata(pdev, master);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700674
675 spi = spi_master_get_devdata(master);
676 spi->master = master;
Marcin Wojtase2be7032020-12-23 12:38:26 +0200677 spi->dev = &pdev->dev;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700678
Greg Ungererdf59fa72014-09-28 23:24:04 +1000679 of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
Greg Ungerer9a2d3632014-10-21 15:57:48 +1000680 devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
Greg Ungererdf59fa72014-09-28 23:24:04 +1000681 spi->devdata = devdata;
682
Jingoo Hanbb489842013-12-09 19:21:22 +0900683 spi->clk = devm_clk_get(&pdev->dev, NULL);
Andrew Lunn4574b882012-04-06 17:17:26 +0200684 if (IS_ERR(spi->clk)) {
685 status = PTR_ERR(spi->clk);
686 goto out;
687 }
688
Russell Kingc85012a2014-06-21 11:32:23 +0100689 status = clk_prepare_enable(spi->clk);
690 if (status)
691 goto out;
692
Gregory CLEMENT92ae1122018-01-12 11:42:33 +0100693 /* The following clock is only used by some SoCs */
694 spi->axi_clk = devm_clk_get(&pdev->dev, "axi");
Masahiro Yamada45586c72020-02-03 17:37:45 -0800695 if (PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) {
Christophe Jaillet479c03a2018-01-25 21:16:17 +0100696 status = -EPROBE_DEFER;
697 goto out_rel_clk;
698 }
Gregory CLEMENT92ae1122018-01-12 11:42:33 +0100699 if (!IS_ERR(spi->axi_clk))
700 clk_prepare_enable(spi->axi_clk);
701
Andrew Lunn4574b882012-04-06 17:17:26 +0200702 tclk_hz = clk_get_rate(spi->clk);
Gregory CLEMENTce2f6ea2015-05-26 11:44:42 +0200703
704 /*
705 * With old device tree, armada-370-spi could be used with
706 * Armada XP, however for this SoC the maximum frequency is
707 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
708 * higher than 200MHz. So, in order to be able to handle both
709 * SoCs, we can take the minimum of 50MHz and tclk/4.
710 */
711 if (of_device_is_compatible(pdev->dev.of_node,
712 "marvell,armada-370-spi"))
713 master->max_speed_hz = min(devdata->max_hz,
714 DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
Gregory CLEMENT4dacccf2015-05-26 11:44:43 +0200715 else if (devdata->min_divisor)
Gregory CLEMENTce2f6ea2015-05-26 11:44:42 +0200716 master->max_speed_hz =
717 DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
Gregory CLEMENT4dacccf2015-05-26 11:44:43 +0200718 else
719 master->max_speed_hz = devdata->max_hz;
Greg Ungererdf59fa72014-09-28 23:24:04 +1000720 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700721
722 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Mark Brown1729ce32013-07-28 14:38:06 +0100723 spi->base = devm_ioremap_resource(&pdev->dev, r);
724 if (IS_ERR(spi->base)) {
725 status = PTR_ERR(spi->base);
Christophe Jaillet479c03a2018-01-25 21:16:17 +0100726 goto out_rel_axi_clk;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700727 }
728
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200729 for_each_available_child_of_node(pdev->dev.of_node, np) {
Kosta Zertsekelc7ba4732018-08-15 22:04:49 +0300730 struct orion_direct_acc *dir_acc;
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200731 u32 cs;
732
733 /* Get chip-select number from the "reg" property */
734 status = of_property_read_u32(np, "reg", &cs);
735 if (status) {
736 dev_err(&pdev->dev,
Rob Herring25c56c82017-07-18 16:43:31 -0500737 "%pOF has no valid 'reg' property (%d)\n",
738 np, status);
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200739 continue;
740 }
741
742 /*
743 * Check if an address is configured for this SPI device. If
744 * not, the MBus mapping via the 'ranges' property in the 'soc'
745 * node is not configured and this device should not use the
746 * direct mode. In this case, just continue with the next
747 * device.
748 */
749 status = of_address_to_resource(pdev->dev.of_node, cs + 1, r);
750 if (status)
751 continue;
752
753 /*
754 * Only map one page for direct access. This is enough for the
755 * simple TX transfer which only writes to the first word.
Tudor Ambarus3e84cdd2020-07-16 08:11:44 +0300756 * This needs to get extended for the direct SPI NOR / SPI NAND
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200757 * support, once this gets implemented.
758 */
Kosta Zertsekelc7ba4732018-08-15 22:04:49 +0300759 dir_acc = &spi->child[cs].direct_access;
760 dir_acc->vaddr = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
761 if (!dir_acc->vaddr) {
Wei Yongjun57c624a2016-06-13 14:32:23 +0000762 status = -ENOMEM;
Christophe Jaillet479c03a2018-01-25 21:16:17 +0100763 goto out_rel_axi_clk;
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200764 }
Kosta Zertsekelc7ba4732018-08-15 22:04:49 +0300765 dir_acc->size = PAGE_SIZE;
Stefan Roeseb3c195b2016-05-19 09:07:05 +0200766
767 dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
768 }
769
Russell King5c6786942014-06-21 12:22:37 +0100770 pm_runtime_set_active(&pdev->dev);
771 pm_runtime_use_autosuspend(&pdev->dev);
772 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
773 pm_runtime_enable(&pdev->dev);
774
Wei Yongjun14033812014-07-20 22:03:14 +0800775 status = orion_spi_reset(spi);
776 if (status < 0)
Russell King5c6786942014-06-21 12:22:37 +0100777 goto out_rel_pm;
778
Andrew Lunnf814f9a2012-07-23 12:08:09 +0200779 master->dev.of_node = pdev->dev.of_node;
Russell King5c6786942014-06-21 12:22:37 +0100780 status = spi_register_master(master);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700781 if (status < 0)
Russell King5c6786942014-06-21 12:22:37 +0100782 goto out_rel_pm;
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700783
784 return status;
785
Russell King5c6786942014-06-21 12:22:37 +0100786out_rel_pm:
787 pm_runtime_disable(&pdev->dev);
Christophe Jaillet479c03a2018-01-25 21:16:17 +0100788out_rel_axi_clk:
Gregory CLEMENT92ae1122018-01-12 11:42:33 +0100789 clk_disable_unprepare(spi->axi_clk);
Christophe Jaillet479c03a2018-01-25 21:16:17 +0100790out_rel_clk:
Andrew Lunn4574b882012-04-06 17:17:26 +0200791 clk_disable_unprepare(spi->clk);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700792out:
793 spi_master_put(master);
794 return status;
795}
796
797
Grant Likely2deff8d2013-02-05 13:27:35 +0000798static int orion_spi_remove(struct platform_device *pdev)
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700799{
Russell King5c6786942014-06-21 12:22:37 +0100800 struct spi_master *master = platform_get_drvdata(pdev);
801 struct orion_spi *spi = spi_master_get_devdata(master);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700802
Russell King5c6786942014-06-21 12:22:37 +0100803 pm_runtime_get_sync(&pdev->dev);
Gregory CLEMENT92ae1122018-01-12 11:42:33 +0100804 clk_disable_unprepare(spi->axi_clk);
Andrew Lunn4574b882012-04-06 17:17:26 +0200805 clk_disable_unprepare(spi->clk);
Andrew Lunn4574b882012-04-06 17:17:26 +0200806
Russell King5c6786942014-06-21 12:22:37 +0100807 spi_unregister_master(master);
808 pm_runtime_disable(&pdev->dev);
809
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700810 return 0;
811}
812
813MODULE_ALIAS("platform:" DRIVER_NAME);
814
Rafael J. Wysockiec833052014-12-13 00:41:15 +0100815#ifdef CONFIG_PM
Russell King5c6786942014-06-21 12:22:37 +0100816static int orion_spi_runtime_suspend(struct device *dev)
817{
818 struct spi_master *master = dev_get_drvdata(dev);
819 struct orion_spi *spi = spi_master_get_devdata(master);
820
Gregory CLEMENT92ae1122018-01-12 11:42:33 +0100821 clk_disable_unprepare(spi->axi_clk);
Russell King5c6786942014-06-21 12:22:37 +0100822 clk_disable_unprepare(spi->clk);
823 return 0;
824}
825
826static int orion_spi_runtime_resume(struct device *dev)
827{
828 struct spi_master *master = dev_get_drvdata(dev);
829 struct orion_spi *spi = spi_master_get_devdata(master);
830
Gregory CLEMENT92ae1122018-01-12 11:42:33 +0100831 if (!IS_ERR(spi->axi_clk))
832 clk_prepare_enable(spi->axi_clk);
Russell King5c6786942014-06-21 12:22:37 +0100833 return clk_prepare_enable(spi->clk);
834}
835#endif
836
837static const struct dev_pm_ops orion_spi_pm_ops = {
838 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
839 orion_spi_runtime_resume,
840 NULL)
841};
842
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700843static struct platform_driver orion_spi_driver = {
844 .driver = {
845 .name = DRIVER_NAME,
Russell King5c6786942014-06-21 12:22:37 +0100846 .pm = &orion_spi_pm_ops,
Andrew Lunnf814f9a2012-07-23 12:08:09 +0200847 .of_match_table = of_match_ptr(orion_spi_of_match_table),
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700848 },
Ezequiel Garcia41ab7242013-02-04 09:26:26 -0300849 .probe = orion_spi_probe,
Grant Likely2deff8d2013-02-05 13:27:35 +0000850 .remove = orion_spi_remove,
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700851};
852
Ezequiel Garcia41ab7242013-02-04 09:26:26 -0300853module_platform_driver(orion_spi_driver);
Shadi Ammouri60cadec2008-08-05 13:01:09 -0700854
855MODULE_DESCRIPTION("Orion SPI driver");
856MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
857MODULE_LICENSE("GPL");