blob: 2d8932a20161b533f51f96e785e97b6cb8711f60 [file] [log] [blame]
Will Newtonf95f3852011-01-02 01:11:59 -05001/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
Will Newtonf95f3852011-01-02 01:11:59 -050025#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
Doug Andersonb24c8b22014-12-02 15:42:46 -080030#include <linux/mmc/card.h>
Will Newtonf95f3852011-01-02 01:11:59 -050031#include <linux/mmc/host.h>
32#include <linux/mmc/mmc.h>
Doug Anderson01730552014-08-22 19:17:51 +053033#include <linux/mmc/sd.h>
Seungwon Jeon90c21432013-08-31 00:14:05 +090034#include <linux/mmc/sdio.h>
Will Newtonf95f3852011-01-02 01:11:59 -050035#include <linux/bitops.h>
Jaehoon Chungc07946a2011-02-25 11:08:14 +090036#include <linux/regulator/consumer.h>
Thomas Abrahamc91eab42012-09-17 18:16:40 +000037#include <linux/of.h>
Doug Anderson55a6ceb2013-01-11 17:03:53 +000038#include <linux/of_gpio.h>
Zhangfei Gaobf626e52014-01-09 22:35:10 +080039#include <linux/mmc/slot-gpio.h>
Will Newtonf95f3852011-01-02 01:11:59 -050040
41#include "dw_mmc.h"
42
43/* Common flag combinations */
Jaehoon Chung3f7eec62013-05-27 13:47:57 +090044#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
Will Newtonf95f3852011-01-02 01:11:59 -050045 SDMMC_INT_HTO | SDMMC_INT_SBE | \
Doug Anderson7a3c5672015-03-10 08:48:10 -070046 SDMMC_INT_EBE | SDMMC_INT_HLE)
Will Newtonf95f3852011-01-02 01:11:59 -050047#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
Doug Anderson7a3c5672015-03-10 08:48:10 -070048 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
Will Newtonf95f3852011-01-02 01:11:59 -050049#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
Doug Anderson7a3c5672015-03-10 08:48:10 -070050 DW_MCI_CMD_ERROR_FLAGS)
Will Newtonf95f3852011-01-02 01:11:59 -050051#define DW_MCI_SEND_STATUS 1
52#define DW_MCI_RECV_STATUS 2
53#define DW_MCI_DMA_THRESHOLD 16
54
Seungwon Jeon1f44a2a2013-08-31 00:13:31 +090055#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
Jaehoon Chung72e83572016-11-17 16:40:35 +090056#define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
Seungwon Jeon1f44a2a2013-08-31 00:13:31 +090057
Joonyoung Shimfc79a4d2013-04-26 15:35:22 +090058#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
59 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
60 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
61 SDMMC_IDMAC_INT_TI)
62
Shawn Lincc190d42016-09-02 12:14:39 +080063#define DESC_RING_BUF_SZ PAGE_SIZE
64
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +000065struct idmac_desc_64addr {
66 u32 des0; /* Control Descriptor */
67
68 u32 des1; /* Reserved */
69
70 u32 des2; /*Buffer sizes */
71#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
Ben Dooks6687c422015-03-25 11:27:51 +000072 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
73 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +000074
75 u32 des3; /* Reserved */
76
77 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
78 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
79
80 u32 des6; /* Lower 32-bits of Next Descriptor Address */
81 u32 des7; /* Upper 32-bits of Next Descriptor Address */
82};
83
Will Newtonf95f3852011-01-02 01:11:59 -050084struct idmac_desc {
Ben Dooks6687c422015-03-25 11:27:51 +000085 __le32 des0; /* Control Descriptor */
Will Newtonf95f3852011-01-02 01:11:59 -050086#define IDMAC_DES0_DIC BIT(1)
87#define IDMAC_DES0_LD BIT(2)
88#define IDMAC_DES0_FD BIT(3)
89#define IDMAC_DES0_CH BIT(4)
90#define IDMAC_DES0_ER BIT(5)
91#define IDMAC_DES0_CES BIT(30)
92#define IDMAC_DES0_OWN BIT(31)
93
Ben Dooks6687c422015-03-25 11:27:51 +000094 __le32 des1; /* Buffer sizes */
Will Newtonf95f3852011-01-02 01:11:59 -050095#define IDMAC_SET_BUFFER1_SIZE(d, s) \
Ben Dookse5306c32016-06-07 14:37:19 +010096 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
Will Newtonf95f3852011-01-02 01:11:59 -050097
Ben Dooks6687c422015-03-25 11:27:51 +000098 __le32 des2; /* buffer 1 physical address */
Will Newtonf95f3852011-01-02 01:11:59 -050099
Ben Dooks6687c422015-03-25 11:27:51 +0000100 __le32 des3; /* buffer 2 physical address */
Will Newtonf95f3852011-01-02 01:11:59 -0500101};
Alexey Brodkin5959b322015-06-25 11:25:07 +0300102
103/* Each descriptor can transfer up to 4KB of data in chained mode */
104#define DW_MCI_DESC_DATA_LENGTH 0x1000
Will Newtonf95f3852011-01-02 01:11:59 -0500105
Sonny Rao3a33a942014-08-04 18:19:50 -0700106static bool dw_mci_reset(struct dw_mci *host);
Sonny Rao536f6b92014-10-16 09:58:05 -0700107static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
Doug Anderson0bdbd0e2015-02-20 12:31:56 -0800108static int dw_mci_card_busy(struct mmc_host *mmc);
Shawn Lin56f69112016-05-27 14:37:05 +0800109static int dw_mci_get_cd(struct mmc_host *mmc);
Seungwon Jeon31bff452013-08-31 00:14:23 +0900110
Will Newtonf95f3852011-01-02 01:11:59 -0500111#if defined(CONFIG_DEBUG_FS)
112static int dw_mci_req_show(struct seq_file *s, void *v)
113{
114 struct dw_mci_slot *slot = s->private;
115 struct mmc_request *mrq;
116 struct mmc_command *cmd;
117 struct mmc_command *stop;
118 struct mmc_data *data;
119
120 /* Make sure we get a consistent snapshot */
121 spin_lock_bh(&slot->host->lock);
122 mrq = slot->mrq;
123
124 if (mrq) {
125 cmd = mrq->cmd;
126 data = mrq->data;
127 stop = mrq->stop;
128
129 if (cmd)
130 seq_printf(s,
131 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
132 cmd->opcode, cmd->arg, cmd->flags,
133 cmd->resp[0], cmd->resp[1], cmd->resp[2],
134 cmd->resp[2], cmd->error);
135 if (data)
136 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
137 data->bytes_xfered, data->blocks,
138 data->blksz, data->flags, data->error);
139 if (stop)
140 seq_printf(s,
141 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
142 stop->opcode, stop->arg, stop->flags,
143 stop->resp[0], stop->resp[1], stop->resp[2],
144 stop->resp[2], stop->error);
145 }
146
147 spin_unlock_bh(&slot->host->lock);
148
149 return 0;
150}
151
152static int dw_mci_req_open(struct inode *inode, struct file *file)
153{
154 return single_open(file, dw_mci_req_show, inode->i_private);
155}
156
157static const struct file_operations dw_mci_req_fops = {
158 .owner = THIS_MODULE,
159 .open = dw_mci_req_open,
160 .read = seq_read,
161 .llseek = seq_lseek,
162 .release = single_release,
163};
164
165static int dw_mci_regs_show(struct seq_file *s, void *v)
166{
Jaehoon Chung21657ebd2016-11-17 16:40:33 +0900167 struct dw_mci *host = s->private;
168
169 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
170 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
171 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
172 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
173 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
174 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
Will Newtonf95f3852011-01-02 01:11:59 -0500175
176 return 0;
177}
178
179static int dw_mci_regs_open(struct inode *inode, struct file *file)
180{
181 return single_open(file, dw_mci_regs_show, inode->i_private);
182}
183
184static const struct file_operations dw_mci_regs_fops = {
185 .owner = THIS_MODULE,
186 .open = dw_mci_regs_open,
187 .read = seq_read,
188 .llseek = seq_lseek,
189 .release = single_release,
190};
191
192static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
193{
194 struct mmc_host *mmc = slot->mmc;
195 struct dw_mci *host = slot->host;
196 struct dentry *root;
197 struct dentry *node;
198
199 root = mmc->debugfs_root;
200 if (!root)
201 return;
202
203 node = debugfs_create_file("regs", S_IRUSR, root, host,
204 &dw_mci_regs_fops);
205 if (!node)
206 goto err;
207
208 node = debugfs_create_file("req", S_IRUSR, root, slot,
209 &dw_mci_req_fops);
210 if (!node)
211 goto err;
212
213 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
214 if (!node)
215 goto err;
216
217 node = debugfs_create_x32("pending_events", S_IRUSR, root,
218 (u32 *)&host->pending_events);
219 if (!node)
220 goto err;
221
222 node = debugfs_create_x32("completed_events", S_IRUSR, root,
223 (u32 *)&host->completed_events);
224 if (!node)
225 goto err;
226
227 return;
228
229err:
230 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
231}
232#endif /* defined(CONFIG_DEBUG_FS) */
233
Doug Anderson01730552014-08-22 19:17:51 +0530234static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
235
Will Newtonf95f3852011-01-02 01:11:59 -0500236static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
237{
Thomas Abraham800d78b2012-09-17 18:16:42 +0000238 struct dw_mci_slot *slot = mmc_priv(mmc);
Doug Anderson01730552014-08-22 19:17:51 +0530239 struct dw_mci *host = slot->host;
Will Newtonf95f3852011-01-02 01:11:59 -0500240 u32 cmdr;
Will Newtonf95f3852011-01-02 01:11:59 -0500241
Shawn Lin0e3a22c2015-08-03 15:07:21 +0800242 cmd->error = -EINPROGRESS;
Will Newtonf95f3852011-01-02 01:11:59 -0500243 cmdr = cmd->opcode;
244
Seungwon Jeon90c21432013-08-31 00:14:05 +0900245 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
246 cmd->opcode == MMC_GO_IDLE_STATE ||
247 cmd->opcode == MMC_GO_INACTIVE_STATE ||
248 (cmd->opcode == SD_IO_RW_DIRECT &&
249 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
Will Newtonf95f3852011-01-02 01:11:59 -0500250 cmdr |= SDMMC_CMD_STOP;
Jaehoon Chung4a1b27a2014-03-03 11:36:44 +0900251 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
252 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
Will Newtonf95f3852011-01-02 01:11:59 -0500253
Doug Anderson01730552014-08-22 19:17:51 +0530254 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
255 u32 clk_en_a;
256
257 /* Special bit makes CMD11 not die */
258 cmdr |= SDMMC_CMD_VOLT_SWITCH;
259
260 /* Change state to continue to handle CMD11 weirdness */
261 WARN_ON(slot->host->state != STATE_SENDING_CMD);
262 slot->host->state = STATE_SENDING_CMD11;
263
264 /*
265 * We need to disable low power mode (automatic clock stop)
266 * while doing voltage switch so we don't confuse the card,
267 * since stopping the clock is a specific part of the UHS
268 * voltage change dance.
269 *
270 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
271 * unconditionally turned back on in dw_mci_setup_bus() if it's
272 * ever called with a non-zero clock. That shouldn't happen
273 * until the voltage change is all done.
274 */
275 clk_en_a = mci_readl(host, CLKENA);
276 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
277 mci_writel(host, CLKENA, clk_en_a);
278 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
279 SDMMC_CMD_PRV_DAT_WAIT, 0);
280 }
281
Will Newtonf95f3852011-01-02 01:11:59 -0500282 if (cmd->flags & MMC_RSP_PRESENT) {
283 /* We expect a response, so set this bit */
284 cmdr |= SDMMC_CMD_RESP_EXP;
285 if (cmd->flags & MMC_RSP_136)
286 cmdr |= SDMMC_CMD_RESP_LONG;
287 }
288
289 if (cmd->flags & MMC_RSP_CRC)
290 cmdr |= SDMMC_CMD_RESP_CRC;
291
Jaehoon Chung0349c082016-11-17 16:40:39 +0900292 if (cmd->data) {
Will Newtonf95f3852011-01-02 01:11:59 -0500293 cmdr |= SDMMC_CMD_DAT_EXP;
Jaehoon Chung0349c082016-11-17 16:40:39 +0900294 if (cmd->data->flags & MMC_DATA_WRITE)
Will Newtonf95f3852011-01-02 01:11:59 -0500295 cmdr |= SDMMC_CMD_DAT_WR;
296 }
297
Jaehoon Chungaaaaeb72016-01-21 11:01:06 +0900298 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
299 cmdr |= SDMMC_CMD_USE_HOLD_REG;
Thomas Abraham800d78b2012-09-17 18:16:42 +0000300
Will Newtonf95f3852011-01-02 01:11:59 -0500301 return cmdr;
302}
303
Seungwon Jeon90c21432013-08-31 00:14:05 +0900304static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
305{
306 struct mmc_command *stop;
307 u32 cmdr;
308
309 if (!cmd->data)
310 return 0;
311
312 stop = &host->stop_abort;
313 cmdr = cmd->opcode;
314 memset(stop, 0, sizeof(struct mmc_command));
315
316 if (cmdr == MMC_READ_SINGLE_BLOCK ||
317 cmdr == MMC_READ_MULTIPLE_BLOCK ||
318 cmdr == MMC_WRITE_BLOCK ||
Ulf Hansson6c2c6502014-12-01 16:13:39 +0100319 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
320 cmdr == MMC_SEND_TUNING_BLOCK ||
321 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
Seungwon Jeon90c21432013-08-31 00:14:05 +0900322 stop->opcode = MMC_STOP_TRANSMISSION;
323 stop->arg = 0;
324 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
325 } else if (cmdr == SD_IO_RW_EXTENDED) {
326 stop->opcode = SD_IO_RW_DIRECT;
327 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
328 ((cmd->arg >> 28) & 0x7);
329 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
330 } else {
331 return 0;
332 }
333
334 cmdr = stop->opcode | SDMMC_CMD_STOP |
335 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
336
Jaehoon Chung8c005b42016-11-17 16:40:36 +0900337 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags))
338 cmdr |= SDMMC_CMD_USE_HOLD_REG;
339
Seungwon Jeon90c21432013-08-31 00:14:05 +0900340 return cmdr;
341}
342
Doug Anderson0bdbd0e2015-02-20 12:31:56 -0800343static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
344{
345 unsigned long timeout = jiffies + msecs_to_jiffies(500);
346
347 /*
348 * Databook says that before issuing a new data transfer command
349 * we need to check to see if the card is busy. Data transfer commands
350 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
351 *
352 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
353 * expected.
354 */
355 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
356 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
357 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
358 if (time_after(jiffies, timeout)) {
359 /* Command will fail; we'll pass error then */
360 dev_err(host->dev, "Busy; trying anyway\n");
361 break;
362 }
363 udelay(10);
364 }
365 }
366}
367
Will Newtonf95f3852011-01-02 01:11:59 -0500368static void dw_mci_start_command(struct dw_mci *host,
369 struct mmc_command *cmd, u32 cmd_flags)
370{
371 host->cmd = cmd;
Thomas Abraham4a909202012-09-17 18:16:35 +0000372 dev_vdbg(host->dev,
Will Newtonf95f3852011-01-02 01:11:59 -0500373 "start command: ARGR=0x%08x CMDR=0x%08x\n",
374 cmd->arg, cmd_flags);
375
376 mci_writel(host, CMDARG, cmd->arg);
Shawn Lin0e3a22c2015-08-03 15:07:21 +0800377 wmb(); /* drain writebuffer */
Doug Anderson0bdbd0e2015-02-20 12:31:56 -0800378 dw_mci_wait_while_busy(host, cmd_flags);
Will Newtonf95f3852011-01-02 01:11:59 -0500379
380 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
381}
382
Seungwon Jeon90c21432013-08-31 00:14:05 +0900383static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
Will Newtonf95f3852011-01-02 01:11:59 -0500384{
Jaehoon Chunge13c3c02016-11-17 16:40:37 +0900385 struct mmc_command *stop = &host->stop_abort;
Shawn Lin0e3a22c2015-08-03 15:07:21 +0800386
Seungwon Jeon90c21432013-08-31 00:14:05 +0900387 dw_mci_start_command(host, stop, host->stop_cmdr);
Will Newtonf95f3852011-01-02 01:11:59 -0500388}
389
390/* DMA interface functions */
391static void dw_mci_stop_dma(struct dw_mci *host)
392{
James Hogan03e8cb52011-06-29 09:28:43 +0100393 if (host->using_dma) {
Will Newtonf95f3852011-01-02 01:11:59 -0500394 host->dma_ops->stop(host);
395 host->dma_ops->cleanup(host);
Will Newtonf95f3852011-01-02 01:11:59 -0500396 }
Seungwon Jeonaa50f252013-08-31 00:14:38 +0900397
398 /* Data transfer was stopped by the interrupt handler */
399 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
Will Newtonf95f3852011-01-02 01:11:59 -0500400}
401
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900402static int dw_mci_get_dma_dir(struct mmc_data *data)
403{
404 if (data->flags & MMC_DATA_WRITE)
405 return DMA_TO_DEVICE;
406 else
407 return DMA_FROM_DEVICE;
408}
409
Will Newtonf95f3852011-01-02 01:11:59 -0500410static void dw_mci_dma_cleanup(struct dw_mci *host)
411{
412 struct mmc_data *data = host->data;
413
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900414 if (data && data->host_cookie == COOKIE_MAPPED) {
415 dma_unmap_sg(host->dev,
416 data->sg,
417 data->sg_len,
418 dw_mci_get_dma_dir(data));
419 data->host_cookie = COOKIE_UNMAPPED;
420 }
Will Newtonf95f3852011-01-02 01:11:59 -0500421}
422
Seungwon Jeon5ce9d962013-08-31 00:14:33 +0900423static void dw_mci_idmac_reset(struct dw_mci *host)
424{
425 u32 bmod = mci_readl(host, BMOD);
426 /* Software reset of DMA */
427 bmod |= SDMMC_IDMAC_SWRESET;
428 mci_writel(host, BMOD, bmod);
429}
430
Will Newtonf95f3852011-01-02 01:11:59 -0500431static void dw_mci_idmac_stop_dma(struct dw_mci *host)
432{
433 u32 temp;
434
435 /* Disable and reset the IDMAC interface */
436 temp = mci_readl(host, CTRL);
437 temp &= ~SDMMC_CTRL_USE_IDMAC;
438 temp |= SDMMC_CTRL_DMA_RESET;
439 mci_writel(host, CTRL, temp);
440
441 /* Stop the IDMAC running */
442 temp = mci_readl(host, BMOD);
Jaehoon Chunga5289a42011-02-25 11:08:13 +0900443 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
Seungwon Jeon5ce9d962013-08-31 00:14:33 +0900444 temp |= SDMMC_IDMAC_SWRESET;
Will Newtonf95f3852011-01-02 01:11:59 -0500445 mci_writel(host, BMOD, temp);
446}
447
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800448static void dw_mci_dmac_complete_dma(void *arg)
Will Newtonf95f3852011-01-02 01:11:59 -0500449{
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800450 struct dw_mci *host = arg;
Will Newtonf95f3852011-01-02 01:11:59 -0500451 struct mmc_data *data = host->data;
452
Thomas Abraham4a909202012-09-17 18:16:35 +0000453 dev_vdbg(host->dev, "DMA complete\n");
Will Newtonf95f3852011-01-02 01:11:59 -0500454
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800455 if ((host->use_dma == TRANS_MODE_EDMAC) &&
456 data && (data->flags & MMC_DATA_READ))
457 /* Invalidate cache after read */
458 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
459 data->sg,
460 data->sg_len,
461 DMA_FROM_DEVICE);
462
Will Newtonf95f3852011-01-02 01:11:59 -0500463 host->dma_ops->cleanup(host);
464
465 /*
466 * If the card was removed, data will be NULL. No point in trying to
467 * send the stop command or waiting for NBUSY in this case.
468 */
469 if (data) {
470 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
471 tasklet_schedule(&host->tasklet);
472 }
473}
474
Will Newtonf95f3852011-01-02 01:11:59 -0500475static int dw_mci_idmac_init(struct dw_mci *host)
476{
Seungwon Jeon897b69e2012-09-19 13:58:31 +0800477 int i;
Will Newtonf95f3852011-01-02 01:11:59 -0500478
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000479 if (host->dma_64bit_address == 1) {
480 struct idmac_desc_64addr *p;
481 /* Number of descriptors in the ring buffer */
Shawn Lincc190d42016-09-02 12:14:39 +0800482 host->ring_size =
483 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
Will Newtonf95f3852011-01-02 01:11:59 -0500484
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000485 /* Forward link the descriptor list */
486 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
487 i++, p++) {
488 p->des6 = (host->sg_dma +
489 (sizeof(struct idmac_desc_64addr) *
490 (i + 1))) & 0xffffffff;
Will Newtonf95f3852011-01-02 01:11:59 -0500491
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000492 p->des7 = (u64)(host->sg_dma +
493 (sizeof(struct idmac_desc_64addr) *
494 (i + 1))) >> 32;
495 /* Initialize reserved and buffer size fields to "0" */
496 p->des1 = 0;
497 p->des2 = 0;
498 p->des3 = 0;
499 }
500
501 /* Set the last descriptor as the end-of-ring descriptor */
502 p->des6 = host->sg_dma & 0xffffffff;
503 p->des7 = (u64)host->sg_dma >> 32;
504 p->des0 = IDMAC_DES0_ER;
505
506 } else {
507 struct idmac_desc *p;
508 /* Number of descriptors in the ring buffer */
Shawn Lincc190d42016-09-02 12:14:39 +0800509 host->ring_size =
510 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000511
512 /* Forward link the descriptor list */
Shawn Lin0e3a22c2015-08-03 15:07:21 +0800513 for (i = 0, p = host->sg_cpu;
514 i < host->ring_size - 1;
515 i++, p++) {
Ben Dooks6687c422015-03-25 11:27:51 +0000516 p->des3 = cpu_to_le32(host->sg_dma +
517 (sizeof(struct idmac_desc) * (i + 1)));
Zhangfei Gao4b244722015-04-30 22:16:28 +0800518 p->des1 = 0;
519 }
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000520
521 /* Set the last descriptor as the end-of-ring descriptor */
Ben Dooks6687c422015-03-25 11:27:51 +0000522 p->des3 = cpu_to_le32(host->sg_dma);
523 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000524 }
Will Newtonf95f3852011-01-02 01:11:59 -0500525
Seungwon Jeon5ce9d962013-08-31 00:14:33 +0900526 dw_mci_idmac_reset(host);
Seungwon Jeon141a7122012-05-22 13:01:03 +0900527
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000528 if (host->dma_64bit_address == 1) {
529 /* Mask out interrupts - get Tx & Rx complete only */
530 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
531 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
532 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
Will Newtonf95f3852011-01-02 01:11:59 -0500533
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +0000534 /* Set the descriptor base address */
535 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
536 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
537
538 } else {
539 /* Mask out interrupts - get Tx & Rx complete only */
540 mci_writel(host, IDSTS, IDMAC_INT_CLR);
541 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
542 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
543
544 /* Set the descriptor base address */
545 mci_writel(host, DBADDR, host->sg_dma);
546 }
547
Will Newtonf95f3852011-01-02 01:11:59 -0500548 return 0;
549}
550
Shawn Lin3b2a0672016-09-02 12:14:37 +0800551static inline int dw_mci_prepare_desc64(struct dw_mci *host,
552 struct mmc_data *data,
553 unsigned int sg_len)
554{
555 unsigned int desc_len;
556 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
557 unsigned long timeout;
558 int i;
559
560 desc_first = desc_last = desc = host->sg_cpu;
561
562 for (i = 0; i < sg_len; i++) {
563 unsigned int length = sg_dma_len(&data->sg[i]);
564
565 u64 mem_addr = sg_dma_address(&data->sg[i]);
566
567 for ( ; length ; desc++) {
568 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
569 length : DW_MCI_DESC_DATA_LENGTH;
570
571 length -= desc_len;
572
573 /*
574 * Wait for the former clear OWN bit operation
575 * of IDMAC to make sure that this descriptor
576 * isn't still owned by IDMAC as IDMAC's write
577 * ops and CPU's read ops are asynchronous.
578 */
579 timeout = jiffies + msecs_to_jiffies(100);
580 while (readl(&desc->des0) & IDMAC_DES0_OWN) {
581 if (time_after(jiffies, timeout))
582 goto err_own_bit;
583 udelay(10);
584 }
585
586 /*
587 * Set the OWN bit and disable interrupts
588 * for this descriptor
589 */
590 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
591 IDMAC_DES0_CH;
592
593 /* Buffer length */
594 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
595
596 /* Physical address to DMA to/from */
597 desc->des4 = mem_addr & 0xffffffff;
598 desc->des5 = mem_addr >> 32;
599
600 /* Update physical address for the next desc */
601 mem_addr += desc_len;
602
603 /* Save pointer to the last descriptor */
604 desc_last = desc;
605 }
606 }
607
608 /* Set first descriptor */
609 desc_first->des0 |= IDMAC_DES0_FD;
610
611 /* Set last descriptor */
612 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
613 desc_last->des0 |= IDMAC_DES0_LD;
614
615 return 0;
616err_own_bit:
617 /* restore the descriptor chain as it's polluted */
Colin Ian King26be9d72016-11-16 18:55:01 +0000618 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
Shawn Lincc190d42016-09-02 12:14:39 +0800619 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
Shawn Lin3b2a0672016-09-02 12:14:37 +0800620 dw_mci_idmac_init(host);
621 return -EINVAL;
622}
623
624
625static inline int dw_mci_prepare_desc32(struct dw_mci *host,
626 struct mmc_data *data,
627 unsigned int sg_len)
628{
629 unsigned int desc_len;
630 struct idmac_desc *desc_first, *desc_last, *desc;
631 unsigned long timeout;
632 int i;
633
634 desc_first = desc_last = desc = host->sg_cpu;
635
636 for (i = 0; i < sg_len; i++) {
637 unsigned int length = sg_dma_len(&data->sg[i]);
638
639 u32 mem_addr = sg_dma_address(&data->sg[i]);
640
641 for ( ; length ; desc++) {
642 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
643 length : DW_MCI_DESC_DATA_LENGTH;
644
645 length -= desc_len;
646
647 /*
648 * Wait for the former clear OWN bit operation
649 * of IDMAC to make sure that this descriptor
650 * isn't still owned by IDMAC as IDMAC's write
651 * ops and CPU's read ops are asynchronous.
652 */
653 timeout = jiffies + msecs_to_jiffies(100);
654 while (readl(&desc->des0) &
655 cpu_to_le32(IDMAC_DES0_OWN)) {
656 if (time_after(jiffies, timeout))
657 goto err_own_bit;
658 udelay(10);
659 }
660
661 /*
662 * Set the OWN bit and disable interrupts
663 * for this descriptor
664 */
665 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
666 IDMAC_DES0_DIC |
667 IDMAC_DES0_CH);
668
669 /* Buffer length */
670 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
671
672 /* Physical address to DMA to/from */
673 desc->des2 = cpu_to_le32(mem_addr);
674
675 /* Update physical address for the next desc */
676 mem_addr += desc_len;
677
678 /* Save pointer to the last descriptor */
679 desc_last = desc;
680 }
681 }
682
683 /* Set first descriptor */
684 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
685
686 /* Set last descriptor */
687 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
688 IDMAC_DES0_DIC));
689 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
690
691 return 0;
692err_own_bit:
693 /* restore the descriptor chain as it's polluted */
Colin Ian King26be9d72016-11-16 18:55:01 +0000694 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
Shawn Lincc190d42016-09-02 12:14:39 +0800695 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
Shawn Lin3b2a0672016-09-02 12:14:37 +0800696 dw_mci_idmac_init(host);
697 return -EINVAL;
698}
699
700static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
701{
702 u32 temp;
703 int ret;
704
705 if (host->dma_64bit_address == 1)
706 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
707 else
708 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
709
710 if (ret)
711 goto out;
712
713 /* drain writebuffer */
714 wmb();
715
716 /* Make sure to reset DMA in case we did PIO before this */
717 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
718 dw_mci_idmac_reset(host);
719
720 /* Select IDMAC interface */
721 temp = mci_readl(host, CTRL);
722 temp |= SDMMC_CTRL_USE_IDMAC;
723 mci_writel(host, CTRL, temp);
724
725 /* drain writebuffer */
726 wmb();
727
728 /* Enable the IDMAC */
729 temp = mci_readl(host, BMOD);
730 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
731 mci_writel(host, BMOD, temp);
732
733 /* Start it running */
734 mci_writel(host, PLDMND, 1);
735
736out:
737 return ret;
738}
739
Arnd Bergmann8e2b36e2012-11-06 22:55:31 +0100740static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
Seungwon Jeon885c3e82012-02-20 11:01:43 +0900741 .init = dw_mci_idmac_init,
742 .start = dw_mci_idmac_start_dma,
743 .stop = dw_mci_idmac_stop_dma,
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800744 .complete = dw_mci_dmac_complete_dma,
Seungwon Jeon885c3e82012-02-20 11:01:43 +0900745 .cleanup = dw_mci_dma_cleanup,
746};
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800747
748static void dw_mci_edmac_stop_dma(struct dw_mci *host)
749{
Shawn Linab925a32016-03-09 10:34:46 +0800750 dmaengine_terminate_async(host->dms->ch);
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800751}
752
753static int dw_mci_edmac_start_dma(struct dw_mci *host,
754 unsigned int sg_len)
755{
756 struct dma_slave_config cfg;
757 struct dma_async_tx_descriptor *desc = NULL;
758 struct scatterlist *sgl = host->data->sg;
759 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
760 u32 sg_elems = host->data->sg_len;
761 u32 fifoth_val;
762 u32 fifo_offset = host->fifo_reg - host->regs;
763 int ret = 0;
764
765 /* Set external dma config: burst size, burst width */
Arnd Bergmann260b3162015-11-12 15:14:23 +0100766 cfg.dst_addr = host->phy_regs + fifo_offset;
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800767 cfg.src_addr = cfg.dst_addr;
768 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
769 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
770
771 /* Match burst msize with external dma config */
772 fifoth_val = mci_readl(host, FIFOTH);
773 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
774 cfg.src_maxburst = cfg.dst_maxburst;
775
776 if (host->data->flags & MMC_DATA_WRITE)
777 cfg.direction = DMA_MEM_TO_DEV;
778 else
779 cfg.direction = DMA_DEV_TO_MEM;
780
781 ret = dmaengine_slave_config(host->dms->ch, &cfg);
782 if (ret) {
783 dev_err(host->dev, "Failed to config edmac.\n");
784 return -EBUSY;
785 }
786
787 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
788 sg_len, cfg.direction,
789 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
790 if (!desc) {
791 dev_err(host->dev, "Can't prepare slave sg.\n");
792 return -EBUSY;
793 }
794
795 /* Set dw_mci_dmac_complete_dma as callback */
796 desc->callback = dw_mci_dmac_complete_dma;
797 desc->callback_param = (void *)host;
798 dmaengine_submit(desc);
799
800 /* Flush cache before write */
801 if (host->data->flags & MMC_DATA_WRITE)
802 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
803 sg_elems, DMA_TO_DEVICE);
804
805 dma_async_issue_pending(host->dms->ch);
806
807 return 0;
808}
809
810static int dw_mci_edmac_init(struct dw_mci *host)
811{
812 /* Request external dma channel */
813 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
814 if (!host->dms)
815 return -ENOMEM;
816
817 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
818 if (!host->dms->ch) {
Dan Carpenter4539d362015-10-22 22:53:46 +0300819 dev_err(host->dev, "Failed to get external DMA channel.\n");
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800820 kfree(host->dms);
821 host->dms = NULL;
822 return -ENXIO;
823 }
824
825 return 0;
826}
827
828static void dw_mci_edmac_exit(struct dw_mci *host)
829{
830 if (host->dms) {
831 if (host->dms->ch) {
832 dma_release_channel(host->dms->ch);
833 host->dms->ch = NULL;
834 }
835 kfree(host->dms);
836 host->dms = NULL;
837 }
838}
839
840static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
841 .init = dw_mci_edmac_init,
842 .exit = dw_mci_edmac_exit,
843 .start = dw_mci_edmac_start_dma,
844 .stop = dw_mci_edmac_stop_dma,
845 .complete = dw_mci_dmac_complete_dma,
846 .cleanup = dw_mci_dma_cleanup,
847};
Seungwon Jeon885c3e82012-02-20 11:01:43 +0900848
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900849static int dw_mci_pre_dma_transfer(struct dw_mci *host,
850 struct mmc_data *data,
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900851 int cookie)
Will Newtonf95f3852011-01-02 01:11:59 -0500852{
853 struct scatterlist *sg;
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900854 unsigned int i, sg_len;
Will Newtonf95f3852011-01-02 01:11:59 -0500855
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900856 if (data->host_cookie == COOKIE_PRE_MAPPED)
857 return data->sg_len;
Will Newtonf95f3852011-01-02 01:11:59 -0500858
859 /*
860 * We don't do DMA on "complex" transfers, i.e. with
861 * non-word-aligned buffers or lengths. Also, we don't bother
862 * with all the DMA setup overhead for short transfers.
863 */
864 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
865 return -EINVAL;
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900866
Will Newtonf95f3852011-01-02 01:11:59 -0500867 if (data->blksz & 3)
868 return -EINVAL;
869
870 for_each_sg(data->sg, sg, data->sg_len, i) {
871 if (sg->offset & 3 || sg->length & 3)
872 return -EINVAL;
873 }
874
Thomas Abraham4a909202012-09-17 18:16:35 +0000875 sg_len = dma_map_sg(host->dev,
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900876 data->sg,
877 data->sg_len,
878 dw_mci_get_dma_dir(data));
879 if (sg_len == 0)
880 return -EINVAL;
881
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900882 data->host_cookie = cookie;
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900883
884 return sg_len;
885}
886
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900887static void dw_mci_pre_req(struct mmc_host *mmc,
Linus Walleijd3c6aac2016-11-23 11:02:24 +0100888 struct mmc_request *mrq)
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900889{
890 struct dw_mci_slot *slot = mmc_priv(mmc);
891 struct mmc_data *data = mrq->data;
892
893 if (!slot->host->use_dma || !data)
894 return;
895
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900896 /* This data might be unmapped at this time */
897 data->host_cookie = COOKIE_UNMAPPED;
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900898
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900899 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
900 COOKIE_PRE_MAPPED) < 0)
901 data->host_cookie = COOKIE_UNMAPPED;
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900902}
903
904static void dw_mci_post_req(struct mmc_host *mmc,
905 struct mmc_request *mrq,
906 int err)
907{
908 struct dw_mci_slot *slot = mmc_priv(mmc);
909 struct mmc_data *data = mrq->data;
910
911 if (!slot->host->use_dma || !data)
912 return;
913
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900914 if (data->host_cookie != COOKIE_UNMAPPED)
Thomas Abraham4a909202012-09-17 18:16:35 +0000915 dma_unmap_sg(slot->host->dev,
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900916 data->sg,
917 data->sg_len,
918 dw_mci_get_dma_dir(data));
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +0900919 data->host_cookie = COOKIE_UNMAPPED;
Seungwon Jeon9aa51402012-02-06 16:55:07 +0900920}
921
Seungwon Jeon52426892013-08-31 00:13:42 +0900922static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
923{
Seungwon Jeon52426892013-08-31 00:13:42 +0900924 unsigned int blksz = data->blksz;
925 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
926 u32 fifo_width = 1 << host->data_shift;
927 u32 blksz_depth = blksz / fifo_width, fifoth_val;
928 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
Shawn Lin0e3a22c2015-08-03 15:07:21 +0800929 int idx = ARRAY_SIZE(mszs) - 1;
Seungwon Jeon52426892013-08-31 00:13:42 +0900930
Shawn Lin3fc7eae2015-09-16 14:41:23 +0800931 /* pio should ship this scenario */
932 if (!host->use_dma)
933 return;
934
Seungwon Jeon52426892013-08-31 00:13:42 +0900935 tx_wmark = (host->fifo_depth) / 2;
936 tx_wmark_invers = host->fifo_depth - tx_wmark;
937
938 /*
939 * MSIZE is '1',
940 * if blksz is not a multiple of the FIFO width
941 */
Shawn Lin20753562016-09-21 10:40:25 +0800942 if (blksz % fifo_width)
Seungwon Jeon52426892013-08-31 00:13:42 +0900943 goto done;
Seungwon Jeon52426892013-08-31 00:13:42 +0900944
945 do {
946 if (!((blksz_depth % mszs[idx]) ||
947 (tx_wmark_invers % mszs[idx]))) {
948 msize = idx;
949 rx_wmark = mszs[idx] - 1;
950 break;
951 }
952 } while (--idx > 0);
953 /*
954 * If idx is '0', it won't be tried
955 * Thus, initial values are uesed
956 */
957done:
958 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
959 mci_writel(host, FIFOTH, fifoth_val);
Seungwon Jeon52426892013-08-31 00:13:42 +0900960}
961
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +0900962static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
Seungwon Jeonf1d27362013-08-31 00:13:55 +0900963{
964 unsigned int blksz = data->blksz;
965 u32 blksz_depth, fifo_depth;
966 u16 thld_size;
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +0900967 u8 enable;
Seungwon Jeonf1d27362013-08-31 00:13:55 +0900968
James Hogan66dfd102014-11-17 17:49:05 +0000969 /*
970 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
971 * in the FIFO region, so we really shouldn't access it).
972 */
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +0900973 if (host->verid < DW_MMC_240A ||
974 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
James Hogan66dfd102014-11-17 17:49:05 +0000975 return;
976
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +0900977 /*
978 * Card write Threshold is introduced since 2.80a
979 * It's used when HS400 mode is enabled.
980 */
981 if (data->flags & MMC_DATA_WRITE &&
982 !(host->timing != MMC_TIMING_MMC_HS400))
983 return;
984
985 if (data->flags & MMC_DATA_WRITE)
986 enable = SDMMC_CARD_WR_THR_EN;
987 else
988 enable = SDMMC_CARD_RD_THR_EN;
989
Seungwon Jeonf1d27362013-08-31 00:13:55 +0900990 if (host->timing != MMC_TIMING_MMC_HS200 &&
991 host->timing != MMC_TIMING_UHS_SDR104)
992 goto disable;
993
994 blksz_depth = blksz / (1 << host->data_shift);
995 fifo_depth = host->fifo_depth;
996
997 if (blksz_depth > fifo_depth)
998 goto disable;
999
1000 /*
1001 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1002 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1003 * Currently just choose blksz.
1004 */
1005 thld_size = blksz;
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001006 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
Seungwon Jeonf1d27362013-08-31 00:13:55 +09001007 return;
1008
1009disable:
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001010 mci_writel(host, CDTHRCTL, 0);
Seungwon Jeonf1d27362013-08-31 00:13:55 +09001011}
1012
Seungwon Jeon9aa51402012-02-06 16:55:07 +09001013static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1014{
Doug Andersonf8c58c12014-12-02 15:42:47 -08001015 unsigned long irqflags;
Seungwon Jeon9aa51402012-02-06 16:55:07 +09001016 int sg_len;
1017 u32 temp;
1018
1019 host->using_dma = 0;
1020
1021 /* If we don't have a channel, we can't do DMA */
1022 if (!host->use_dma)
1023 return -ENODEV;
1024
Jaehoon Chunga4cc7eb2016-11-17 16:40:38 +09001025 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
Seungwon Jeona99aa9b2012-04-10 09:53:32 +09001026 if (sg_len < 0) {
1027 host->dma_ops->stop(host);
Seungwon Jeon9aa51402012-02-06 16:55:07 +09001028 return sg_len;
Seungwon Jeona99aa9b2012-04-10 09:53:32 +09001029 }
Seungwon Jeon9aa51402012-02-06 16:55:07 +09001030
James Hogan03e8cb52011-06-29 09:28:43 +01001031 host->using_dma = 1;
1032
Shawn Lin3fc7eae2015-09-16 14:41:23 +08001033 if (host->use_dma == TRANS_MODE_IDMAC)
1034 dev_vdbg(host->dev,
1035 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1036 (unsigned long)host->sg_cpu,
1037 (unsigned long)host->sg_dma,
1038 sg_len);
Will Newtonf95f3852011-01-02 01:11:59 -05001039
Seungwon Jeon52426892013-08-31 00:13:42 +09001040 /*
1041 * Decide the MSIZE and RX/TX Watermark.
1042 * If current block size is same with previous size,
1043 * no need to update fifoth.
1044 */
1045 if (host->prev_blksz != data->blksz)
1046 dw_mci_adjust_fifoth(host, data);
1047
Will Newtonf95f3852011-01-02 01:11:59 -05001048 /* Enable the DMA interface */
1049 temp = mci_readl(host, CTRL);
1050 temp |= SDMMC_CTRL_DMA_ENABLE;
1051 mci_writel(host, CTRL, temp);
1052
1053 /* Disable RX/TX IRQs, let DMA handle it */
Doug Andersonf8c58c12014-12-02 15:42:47 -08001054 spin_lock_irqsave(&host->irq_lock, irqflags);
Will Newtonf95f3852011-01-02 01:11:59 -05001055 temp = mci_readl(host, INTMASK);
1056 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1057 mci_writel(host, INTMASK, temp);
Doug Andersonf8c58c12014-12-02 15:42:47 -08001058 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Will Newtonf95f3852011-01-02 01:11:59 -05001059
Shawn Lin3fc7eae2015-09-16 14:41:23 +08001060 if (host->dma_ops->start(host, sg_len)) {
Jaehoon Chung647f80a2016-11-21 10:51:48 +09001061 host->dma_ops->stop(host);
Shawn Lind12d0cb2016-09-02 12:14:38 +08001062 /* We can't do DMA, try PIO for this one */
1063 dev_dbg(host->dev,
1064 "%s: fall back to PIO mode for current transfer\n",
1065 __func__);
Shawn Lin3fc7eae2015-09-16 14:41:23 +08001066 return -ENODEV;
1067 }
Will Newtonf95f3852011-01-02 01:11:59 -05001068
1069 return 0;
1070}
1071
1072static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1073{
Doug Andersonf8c58c12014-12-02 15:42:47 -08001074 unsigned long irqflags;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08001075 int flags = SG_MITER_ATOMIC;
Will Newtonf95f3852011-01-02 01:11:59 -05001076 u32 temp;
1077
1078 data->error = -EINPROGRESS;
1079
1080 WARN_ON(host->data);
1081 host->sg = NULL;
1082 host->data = data;
1083
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001084 if (data->flags & MMC_DATA_READ)
James Hogan55c5efbc2011-06-29 09:29:58 +01001085 host->dir_status = DW_MCI_RECV_STATUS;
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001086 else
James Hogan55c5efbc2011-06-29 09:29:58 +01001087 host->dir_status = DW_MCI_SEND_STATUS;
Jaehoon Chung7e4bf1b2016-06-21 14:35:38 +09001088
1089 dw_mci_ctrl_thld(host, data);
James Hogan55c5efbc2011-06-29 09:29:58 +01001090
Will Newtonf95f3852011-01-02 01:11:59 -05001091 if (dw_mci_submit_data_dma(host, data)) {
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09001092 if (host->data->flags & MMC_DATA_READ)
1093 flags |= SG_MITER_TO_SG;
1094 else
1095 flags |= SG_MITER_FROM_SG;
1096
1097 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
Will Newtonf95f3852011-01-02 01:11:59 -05001098 host->sg = data->sg;
James Hogan34b664a2011-06-24 13:57:56 +01001099 host->part_buf_start = 0;
1100 host->part_buf_count = 0;
Will Newtonf95f3852011-01-02 01:11:59 -05001101
James Hoganb40af3a2011-06-24 13:54:06 +01001102 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
Doug Andersonf8c58c12014-12-02 15:42:47 -08001103
1104 spin_lock_irqsave(&host->irq_lock, irqflags);
Will Newtonf95f3852011-01-02 01:11:59 -05001105 temp = mci_readl(host, INTMASK);
1106 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1107 mci_writel(host, INTMASK, temp);
Doug Andersonf8c58c12014-12-02 15:42:47 -08001108 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Will Newtonf95f3852011-01-02 01:11:59 -05001109
1110 temp = mci_readl(host, CTRL);
1111 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1112 mci_writel(host, CTRL, temp);
Seungwon Jeon52426892013-08-31 00:13:42 +09001113
1114 /*
1115 * Use the initial fifoth_val for PIO mode.
1116 * If next issued data may be transfered by DMA mode,
1117 * prev_blksz should be invalidated.
1118 */
1119 mci_writel(host, FIFOTH, host->fifoth_val);
1120 host->prev_blksz = 0;
1121 } else {
1122 /*
1123 * Keep the current block size.
1124 * It will be used to decide whether to update
1125 * fifoth register next time.
1126 */
1127 host->prev_blksz = data->blksz;
Will Newtonf95f3852011-01-02 01:11:59 -05001128 }
1129}
1130
1131static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1132{
1133 struct dw_mci *host = slot->host;
1134 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1135 unsigned int cmd_status = 0;
1136
1137 mci_writel(host, CMDARG, arg);
Shawn Lin0e3a22c2015-08-03 15:07:21 +08001138 wmb(); /* drain writebuffer */
Doug Anderson0bdbd0e2015-02-20 12:31:56 -08001139 dw_mci_wait_while_busy(host, cmd);
Will Newtonf95f3852011-01-02 01:11:59 -05001140 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1141
1142 while (time_before(jiffies, timeout)) {
1143 cmd_status = mci_readl(host, CMD);
1144 if (!(cmd_status & SDMMC_CMD_START))
1145 return;
1146 }
1147 dev_err(&slot->mmc->class_dev,
1148 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1149 cmd, arg, cmd_status);
1150}
1151
Abhilash Kesavanab269122012-11-19 10:26:21 +05301152static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
Will Newtonf95f3852011-01-02 01:11:59 -05001153{
1154 struct dw_mci *host = slot->host;
Doug Andersonfdf492a2013-08-31 00:11:43 +09001155 unsigned int clock = slot->clock;
Will Newtonf95f3852011-01-02 01:11:59 -05001156 u32 div;
Doug Anderson9623b5b2012-07-25 08:33:17 -07001157 u32 clk_en_a;
Doug Anderson01730552014-08-22 19:17:51 +05301158 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1159
1160 /* We must continue to set bit 28 in CMD until the change is complete */
1161 if (host->state == STATE_WAITING_CMD11_DONE)
1162 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
Will Newtonf95f3852011-01-02 01:11:59 -05001163
Doug Andersonfdf492a2013-08-31 00:11:43 +09001164 if (!clock) {
1165 mci_writel(host, CLKENA, 0);
Doug Anderson01730552014-08-22 19:17:51 +05301166 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
Doug Andersonfdf492a2013-08-31 00:11:43 +09001167 } else if (clock != host->current_speed || force_clkinit) {
1168 div = host->bus_hz / clock;
1169 if (host->bus_hz % clock && host->bus_hz > clock)
Will Newtonf95f3852011-01-02 01:11:59 -05001170 /*
1171 * move the + 1 after the divide to prevent
1172 * over-clocking the card.
1173 */
Seungwon Jeone4199902012-05-22 13:01:21 +09001174 div += 1;
1175
Doug Andersonfdf492a2013-08-31 00:11:43 +09001176 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
Will Newtonf95f3852011-01-02 01:11:59 -05001177
Jaehoon Chunge6cd7a82016-11-24 20:04:42 +09001178 if ((clock != slot->__clk_old &&
1179 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1180 force_clkinit) {
Jaehoon Chung005d6752016-09-22 14:12:00 +09001181 dev_info(&slot->mmc->class_dev,
1182 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1183 slot->id, host->bus_hz, clock,
1184 div ? ((host->bus_hz / div) >> 1) :
1185 host->bus_hz, div);
Will Newtonf95f3852011-01-02 01:11:59 -05001186
Jaehoon Chunge6cd7a82016-11-24 20:04:42 +09001187 /*
1188 * If card is polling, display the message only
1189 * one time at boot time.
1190 */
1191 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1192 slot->mmc->f_min == clock)
1193 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1194 }
1195
Will Newtonf95f3852011-01-02 01:11:59 -05001196 /* disable clock */
1197 mci_writel(host, CLKENA, 0);
1198 mci_writel(host, CLKSRC, 0);
1199
1200 /* inform CIU */
Doug Anderson01730552014-08-22 19:17:51 +05301201 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
Will Newtonf95f3852011-01-02 01:11:59 -05001202
1203 /* set clock to desired speed */
1204 mci_writel(host, CLKDIV, div);
1205
1206 /* inform CIU */
Doug Anderson01730552014-08-22 19:17:51 +05301207 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
Will Newtonf95f3852011-01-02 01:11:59 -05001208
Doug Anderson9623b5b2012-07-25 08:33:17 -07001209 /* enable clock; only low power if no SDIO */
1210 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
Doug Andersonb24c8b22014-12-02 15:42:46 -08001211 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
Doug Anderson9623b5b2012-07-25 08:33:17 -07001212 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1213 mci_writel(host, CLKENA, clk_en_a);
Will Newtonf95f3852011-01-02 01:11:59 -05001214
1215 /* inform CIU */
Doug Anderson01730552014-08-22 19:17:51 +05301216 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
Jaehoon Chung005d6752016-09-22 14:12:00 +09001217
1218 /* keep the last clock value that was requested from core */
1219 slot->__clk_old = clock;
Will Newtonf95f3852011-01-02 01:11:59 -05001220 }
1221
Doug Andersonfdf492a2013-08-31 00:11:43 +09001222 host->current_speed = clock;
1223
Will Newtonf95f3852011-01-02 01:11:59 -05001224 /* Set the current slot bus width */
Seungwon Jeon1d56c452011-06-20 17:23:53 +09001225 mci_writel(host, CTYPE, (slot->ctype << slot->id));
Will Newtonf95f3852011-01-02 01:11:59 -05001226}
1227
Seungwon Jeon053b3ce2011-12-22 18:01:29 +09001228static void __dw_mci_start_request(struct dw_mci *host,
1229 struct dw_mci_slot *slot,
1230 struct mmc_command *cmd)
Will Newtonf95f3852011-01-02 01:11:59 -05001231{
1232 struct mmc_request *mrq;
Will Newtonf95f3852011-01-02 01:11:59 -05001233 struct mmc_data *data;
1234 u32 cmdflags;
1235
1236 mrq = slot->mrq;
Will Newtonf95f3852011-01-02 01:11:59 -05001237
Will Newtonf95f3852011-01-02 01:11:59 -05001238 host->cur_slot = slot;
1239 host->mrq = mrq;
1240
1241 host->pending_events = 0;
1242 host->completed_events = 0;
Seungwon Jeone352c812013-08-31 00:14:17 +09001243 host->cmd_status = 0;
Will Newtonf95f3852011-01-02 01:11:59 -05001244 host->data_status = 0;
Seungwon Jeone352c812013-08-31 00:14:17 +09001245 host->dir_status = 0;
Will Newtonf95f3852011-01-02 01:11:59 -05001246
Seungwon Jeon053b3ce2011-12-22 18:01:29 +09001247 data = cmd->data;
Will Newtonf95f3852011-01-02 01:11:59 -05001248 if (data) {
Jaehoon Chungf16afa82014-03-03 11:36:45 +09001249 mci_writel(host, TMOUT, 0xFFFFFFFF);
Will Newtonf95f3852011-01-02 01:11:59 -05001250 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1251 mci_writel(host, BLKSIZ, data->blksz);
1252 }
1253
Will Newtonf95f3852011-01-02 01:11:59 -05001254 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1255
1256 /* this is the first command, send the initialization clock */
1257 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1258 cmdflags |= SDMMC_CMD_INIT;
1259
1260 if (data) {
1261 dw_mci_submit_data(host, data);
Shawn Lin0e3a22c2015-08-03 15:07:21 +08001262 wmb(); /* drain writebuffer */
Will Newtonf95f3852011-01-02 01:11:59 -05001263 }
1264
1265 dw_mci_start_command(host, cmd, cmdflags);
1266
Doug Anderson5c935162015-03-09 16:18:21 -07001267 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
Doug Anderson49ba0302015-04-03 11:13:07 -07001268 unsigned long irqflags;
1269
Doug Anderson5c935162015-03-09 16:18:21 -07001270 /*
Doug Anderson8886a6f2015-04-03 11:13:05 -07001271 * Databook says to fail after 2ms w/ no response, but evidence
1272 * shows that sometimes the cmd11 interrupt takes over 130ms.
1273 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1274 * is just about to roll over.
Doug Anderson49ba0302015-04-03 11:13:07 -07001275 *
1276 * We do this whole thing under spinlock and only if the
1277 * command hasn't already completed (indicating the the irq
1278 * already ran so we don't want the timeout).
Doug Anderson5c935162015-03-09 16:18:21 -07001279 */
Doug Anderson49ba0302015-04-03 11:13:07 -07001280 spin_lock_irqsave(&host->irq_lock, irqflags);
1281 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1282 mod_timer(&host->cmd11_timer,
1283 jiffies + msecs_to_jiffies(500) + 1);
1284 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Doug Anderson5c935162015-03-09 16:18:21 -07001285 }
1286
Jaehoon Chunge13c3c02016-11-17 16:40:37 +09001287 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
Will Newtonf95f3852011-01-02 01:11:59 -05001288}
1289
Seungwon Jeon053b3ce2011-12-22 18:01:29 +09001290static void dw_mci_start_request(struct dw_mci *host,
1291 struct dw_mci_slot *slot)
1292{
1293 struct mmc_request *mrq = slot->mrq;
1294 struct mmc_command *cmd;
1295
1296 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1297 __dw_mci_start_request(host, slot, cmd);
1298}
1299
James Hogan7456caa2011-06-24 13:55:10 +01001300/* must be called with host->lock held */
Will Newtonf95f3852011-01-02 01:11:59 -05001301static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1302 struct mmc_request *mrq)
1303{
1304 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1305 host->state);
1306
Will Newtonf95f3852011-01-02 01:11:59 -05001307 slot->mrq = mrq;
1308
Doug Anderson01730552014-08-22 19:17:51 +05301309 if (host->state == STATE_WAITING_CMD11_DONE) {
1310 dev_warn(&slot->mmc->class_dev,
1311 "Voltage change didn't complete\n");
1312 /*
1313 * this case isn't expected to happen, so we can
1314 * either crash here or just try to continue on
1315 * in the closest possible state
1316 */
1317 host->state = STATE_IDLE;
1318 }
1319
Will Newtonf95f3852011-01-02 01:11:59 -05001320 if (host->state == STATE_IDLE) {
1321 host->state = STATE_SENDING_CMD;
1322 dw_mci_start_request(host, slot);
1323 } else {
1324 list_add_tail(&slot->queue_node, &host->queue);
1325 }
Will Newtonf95f3852011-01-02 01:11:59 -05001326}
1327
1328static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1329{
1330 struct dw_mci_slot *slot = mmc_priv(mmc);
1331 struct dw_mci *host = slot->host;
1332
1333 WARN_ON(slot->mrq);
1334
James Hogan7456caa2011-06-24 13:55:10 +01001335 /*
1336 * The check for card presence and queueing of the request must be
1337 * atomic, otherwise the card could be removed in between and the
1338 * request wouldn't fail until another card was inserted.
1339 */
James Hogan7456caa2011-06-24 13:55:10 +01001340
Shawn Lin56f69112016-05-27 14:37:05 +08001341 if (!dw_mci_get_cd(mmc)) {
Will Newtonf95f3852011-01-02 01:11:59 -05001342 mrq->cmd->error = -ENOMEDIUM;
1343 mmc_request_done(mmc, mrq);
1344 return;
1345 }
1346
Shawn Lin56f69112016-05-27 14:37:05 +08001347 spin_lock_bh(&host->lock);
1348
Will Newtonf95f3852011-01-02 01:11:59 -05001349 dw_mci_queue_request(host, slot, mrq);
James Hogan7456caa2011-06-24 13:55:10 +01001350
1351 spin_unlock_bh(&host->lock);
Will Newtonf95f3852011-01-02 01:11:59 -05001352}
1353
1354static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1355{
1356 struct dw_mci_slot *slot = mmc_priv(mmc);
Arnd Bergmanne95baf12012-11-08 14:26:11 +00001357 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
Jaehoon Chung41babf72011-02-24 13:46:11 +09001358 u32 regs;
Yuvaraj CD51da2242014-08-22 19:17:50 +05301359 int ret;
Will Newtonf95f3852011-01-02 01:11:59 -05001360
Will Newtonf95f3852011-01-02 01:11:59 -05001361 switch (ios->bus_width) {
Will Newtonf95f3852011-01-02 01:11:59 -05001362 case MMC_BUS_WIDTH_4:
1363 slot->ctype = SDMMC_CTYPE_4BIT;
1364 break;
Jaehoon Chungc9b2a062011-02-17 16:12:38 +09001365 case MMC_BUS_WIDTH_8:
1366 slot->ctype = SDMMC_CTYPE_8BIT;
1367 break;
Jaehoon Chungb2f7cb42012-11-08 17:35:31 +09001368 default:
1369 /* set default 1 bit mode */
1370 slot->ctype = SDMMC_CTYPE_1BIT;
Will Newtonf95f3852011-01-02 01:11:59 -05001371 }
1372
Seungwon Jeon3f514292012-01-02 16:00:02 +09001373 regs = mci_readl(slot->host, UHS_REG);
1374
Jaehoon Chung41babf72011-02-24 13:46:11 +09001375 /* DDR mode set */
Seungwon Jeon80113132015-01-29 08:11:57 +05301376 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
Jaehoon Chung7cc8d582015-10-21 19:49:42 +09001377 ios->timing == MMC_TIMING_UHS_DDR50 ||
Seungwon Jeon80113132015-01-29 08:11:57 +05301378 ios->timing == MMC_TIMING_MMC_HS400)
Hyeonsu Kimc69042a2013-02-22 09:32:46 +09001379 regs |= ((0x1 << slot->id) << 16);
Seungwon Jeon3f514292012-01-02 16:00:02 +09001380 else
Hyeonsu Kimc69042a2013-02-22 09:32:46 +09001381 regs &= ~((0x1 << slot->id) << 16);
Seungwon Jeon3f514292012-01-02 16:00:02 +09001382
1383 mci_writel(slot->host, UHS_REG, regs);
Seungwon Jeonf1d27362013-08-31 00:13:55 +09001384 slot->host->timing = ios->timing;
Jaehoon Chung41babf72011-02-24 13:46:11 +09001385
Doug Andersonfdf492a2013-08-31 00:11:43 +09001386 /*
1387 * Use mirror of ios->clock to prevent race with mmc
1388 * core ios update when finding the minimum.
1389 */
1390 slot->clock = ios->clock;
Will Newtonf95f3852011-01-02 01:11:59 -05001391
James Hogancb27a842012-10-16 09:43:08 +01001392 if (drv_data && drv_data->set_ios)
1393 drv_data->set_ios(slot->host, ios);
Thomas Abraham800d78b2012-09-17 18:16:42 +00001394
Will Newtonf95f3852011-01-02 01:11:59 -05001395 switch (ios->power_mode) {
1396 case MMC_POWER_UP:
Yuvaraj CD51da2242014-08-22 19:17:50 +05301397 if (!IS_ERR(mmc->supply.vmmc)) {
1398 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1399 ios->vdd);
1400 if (ret) {
1401 dev_err(slot->host->dev,
1402 "failed to enable vmmc regulator\n");
1403 /*return, if failed turn on vmmc*/
1404 return;
1405 }
1406 }
Doug Anderson29d0d162015-01-13 15:58:44 -08001407 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1408 regs = mci_readl(slot->host, PWREN);
1409 regs |= (1 << slot->id);
1410 mci_writel(slot->host, PWREN, regs);
1411 break;
1412 case MMC_POWER_ON:
Doug Andersond1f1dd82015-02-20 10:57:19 -08001413 if (!slot->host->vqmmc_enabled) {
1414 if (!IS_ERR(mmc->supply.vqmmc)) {
1415 ret = regulator_enable(mmc->supply.vqmmc);
1416 if (ret < 0)
1417 dev_err(slot->host->dev,
1418 "failed to enable vqmmc\n");
1419 else
1420 slot->host->vqmmc_enabled = true;
1421
1422 } else {
1423 /* Keep track so we don't reset again */
Yuvaraj CD51da2242014-08-22 19:17:50 +05301424 slot->host->vqmmc_enabled = true;
Doug Andersond1f1dd82015-02-20 10:57:19 -08001425 }
1426
1427 /* Reset our state machine after powering on */
1428 dw_mci_ctrl_reset(slot->host,
1429 SDMMC_CTRL_ALL_RESET_FLAGS);
Yuvaraj CD51da2242014-08-22 19:17:50 +05301430 }
Doug Anderson655babb2015-02-20 10:57:18 -08001431
1432 /* Adjust clock / bus width after power is up */
1433 dw_mci_setup_bus(slot, false);
1434
James Hogane6f34e22013-03-12 10:43:32 +00001435 break;
1436 case MMC_POWER_OFF:
Doug Anderson655babb2015-02-20 10:57:18 -08001437 /* Turn clock off before power goes down */
1438 dw_mci_setup_bus(slot, false);
1439
Yuvaraj CD51da2242014-08-22 19:17:50 +05301440 if (!IS_ERR(mmc->supply.vmmc))
1441 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1442
Doug Andersond1f1dd82015-02-20 10:57:19 -08001443 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
Yuvaraj CD51da2242014-08-22 19:17:50 +05301444 regulator_disable(mmc->supply.vqmmc);
Doug Andersond1f1dd82015-02-20 10:57:19 -08001445 slot->host->vqmmc_enabled = false;
Yuvaraj CD51da2242014-08-22 19:17:50 +05301446
Jaehoon Chung4366dcc2013-03-26 21:36:14 +09001447 regs = mci_readl(slot->host, PWREN);
1448 regs &= ~(1 << slot->id);
1449 mci_writel(slot->host, PWREN, regs);
Will Newtonf95f3852011-01-02 01:11:59 -05001450 break;
1451 default:
1452 break;
1453 }
Doug Anderson655babb2015-02-20 10:57:18 -08001454
1455 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1456 slot->host->state = STATE_IDLE;
Will Newtonf95f3852011-01-02 01:11:59 -05001457}
1458
Doug Anderson01730552014-08-22 19:17:51 +05301459static int dw_mci_card_busy(struct mmc_host *mmc)
1460{
1461 struct dw_mci_slot *slot = mmc_priv(mmc);
1462 u32 status;
1463
1464 /*
1465 * Check the busy bit which is low when DAT[3:0]
1466 * (the data lines) are 0000
1467 */
1468 status = mci_readl(slot->host, STATUS);
1469
1470 return !!(status & SDMMC_STATUS_BUSY);
1471}
1472
1473static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1474{
1475 struct dw_mci_slot *slot = mmc_priv(mmc);
1476 struct dw_mci *host = slot->host;
Zhangfei Gao8f7849c2015-05-14 16:45:18 +08001477 const struct dw_mci_drv_data *drv_data = host->drv_data;
Doug Anderson01730552014-08-22 19:17:51 +05301478 u32 uhs;
1479 u32 v18 = SDMMC_UHS_18V << slot->id;
Doug Anderson01730552014-08-22 19:17:51 +05301480 int ret;
1481
Zhangfei Gao8f7849c2015-05-14 16:45:18 +08001482 if (drv_data && drv_data->switch_voltage)
1483 return drv_data->switch_voltage(mmc, ios);
1484
Doug Anderson01730552014-08-22 19:17:51 +05301485 /*
1486 * Program the voltage. Note that some instances of dw_mmc may use
1487 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1488 * does no harm but you need to set the regulator directly. Try both.
1489 */
1490 uhs = mci_readl(host, UHS_REG);
Douglas Andersone0848f52015-10-12 14:48:26 +02001491 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
Doug Anderson01730552014-08-22 19:17:51 +05301492 uhs &= ~v18;
Douglas Andersone0848f52015-10-12 14:48:26 +02001493 else
Doug Anderson01730552014-08-22 19:17:51 +05301494 uhs |= v18;
Douglas Andersone0848f52015-10-12 14:48:26 +02001495
Doug Anderson01730552014-08-22 19:17:51 +05301496 if (!IS_ERR(mmc->supply.vqmmc)) {
Douglas Andersone0848f52015-10-12 14:48:26 +02001497 ret = mmc_regulator_set_vqmmc(mmc, ios);
Doug Anderson01730552014-08-22 19:17:51 +05301498
1499 if (ret) {
Doug Andersonb19caf32014-10-10 21:16:16 -07001500 dev_dbg(&mmc->class_dev,
Douglas Andersone0848f52015-10-12 14:48:26 +02001501 "Regulator set error %d - %s V\n",
1502 ret, uhs & v18 ? "1.8" : "3.3");
Doug Anderson01730552014-08-22 19:17:51 +05301503 return ret;
1504 }
1505 }
1506 mci_writel(host, UHS_REG, uhs);
1507
1508 return 0;
1509}
1510
Will Newtonf95f3852011-01-02 01:11:59 -05001511static int dw_mci_get_ro(struct mmc_host *mmc)
1512{
1513 int read_only;
1514 struct dw_mci_slot *slot = mmc_priv(mmc);
Jaehoon Chung9795a842014-03-03 11:36:46 +09001515 int gpio_ro = mmc_gpio_get_ro(mmc);
Will Newtonf95f3852011-01-02 01:11:59 -05001516
1517 /* Use platform get_ro function, else try on board write protect */
Arnd Bergmann287980e2016-05-27 23:23:25 +02001518 if (gpio_ro >= 0)
Jaehoon Chung9795a842014-03-03 11:36:46 +09001519 read_only = gpio_ro;
Will Newtonf95f3852011-01-02 01:11:59 -05001520 else
1521 read_only =
1522 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1523
1524 dev_dbg(&mmc->class_dev, "card is %s\n",
1525 read_only ? "read-only" : "read-write");
1526
1527 return read_only;
1528}
1529
1530static int dw_mci_get_cd(struct mmc_host *mmc)
1531{
1532 int present;
1533 struct dw_mci_slot *slot = mmc_priv(mmc);
Zhangfei Gao7cf347b2014-01-16 20:48:47 +08001534 struct dw_mci *host = slot->host;
1535 int gpio_cd = mmc_gpio_get_cd(mmc);
Will Newtonf95f3852011-01-02 01:11:59 -05001536
1537 /* Use platform get_cd function, else try onboard card detect */
Jaehoon Chungd10111c2016-11-24 20:04:41 +09001538 if (((mmc->caps & MMC_CAP_NEEDS_POLL)
1539 || !mmc_card_is_removable(mmc))) {
Jaehoon Chungfc3d7722011-02-25 11:08:15 +09001540 present = 1;
Jaehoon Chungd10111c2016-11-24 20:04:41 +09001541
1542 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1543 if (mmc->caps & MMC_CAP_NEEDS_POLL) {
1544 dev_info(&mmc->class_dev,
1545 "card is polling.\n");
1546 } else {
1547 dev_info(&mmc->class_dev,
1548 "card is non-removable.\n");
1549 }
1550 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1551 }
1552
1553 return present;
1554 } else if (gpio_cd >= 0)
Zhangfei Gao7cf347b2014-01-16 20:48:47 +08001555 present = gpio_cd;
Will Newtonf95f3852011-01-02 01:11:59 -05001556 else
1557 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1558 == 0 ? 1 : 0;
1559
Zhangfei Gao7cf347b2014-01-16 20:48:47 +08001560 spin_lock_bh(&host->lock);
Jaehoon Chung1f4d5072016-11-17 16:40:34 +09001561 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
Will Newtonf95f3852011-01-02 01:11:59 -05001562 dev_dbg(&mmc->class_dev, "card is present\n");
Jaehoon Chung1c238a92016-11-24 20:04:40 +09001563 else if (!present &&
1564 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
Will Newtonf95f3852011-01-02 01:11:59 -05001565 dev_dbg(&mmc->class_dev, "card is not present\n");
Zhangfei Gao7cf347b2014-01-16 20:48:47 +08001566 spin_unlock_bh(&host->lock);
Will Newtonf95f3852011-01-02 01:11:59 -05001567
1568 return present;
1569}
1570
Shawn Lin935a6652016-01-14 09:08:02 +08001571static void dw_mci_hw_reset(struct mmc_host *mmc)
1572{
1573 struct dw_mci_slot *slot = mmc_priv(mmc);
1574 struct dw_mci *host = slot->host;
1575 int reset;
1576
1577 if (host->use_dma == TRANS_MODE_IDMAC)
1578 dw_mci_idmac_reset(host);
1579
1580 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1581 SDMMC_CTRL_FIFO_RESET))
1582 return;
1583
1584 /*
1585 * According to eMMC spec, card reset procedure:
1586 * tRstW >= 1us: RST_n pulse width
1587 * tRSCA >= 200us: RST_n to Command time
1588 * tRSTH >= 1us: RST_n high period
1589 */
1590 reset = mci_readl(host, RST_N);
1591 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1592 mci_writel(host, RST_N, reset);
1593 usleep_range(1, 2);
1594 reset |= SDMMC_RST_HWACTIVE << slot->id;
1595 mci_writel(host, RST_N, reset);
1596 usleep_range(200, 300);
1597}
1598
Doug Andersonb24c8b22014-12-02 15:42:46 -08001599static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
Doug Anderson9623b5b2012-07-25 08:33:17 -07001600{
Doug Andersonb24c8b22014-12-02 15:42:46 -08001601 struct dw_mci_slot *slot = mmc_priv(mmc);
Doug Anderson9623b5b2012-07-25 08:33:17 -07001602 struct dw_mci *host = slot->host;
Doug Anderson9623b5b2012-07-25 08:33:17 -07001603
Doug Andersonb24c8b22014-12-02 15:42:46 -08001604 /*
1605 * Low power mode will stop the card clock when idle. According to the
1606 * description of the CLKENA register we should disable low power mode
1607 * for SDIO cards if we need SDIO interrupts to work.
1608 */
1609 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1610 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1611 u32 clk_en_a_old;
1612 u32 clk_en_a;
Doug Anderson9623b5b2012-07-25 08:33:17 -07001613
Doug Andersonb24c8b22014-12-02 15:42:46 -08001614 clk_en_a_old = mci_readl(host, CLKENA);
1615
1616 if (card->type == MMC_TYPE_SDIO ||
1617 card->type == MMC_TYPE_SD_COMBO) {
1618 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1619 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1620 } else {
1621 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1622 clk_en_a = clk_en_a_old | clken_low_pwr;
1623 }
1624
1625 if (clk_en_a != clk_en_a_old) {
1626 mci_writel(host, CLKENA, clk_en_a);
1627 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1628 SDMMC_CMD_PRV_DAT_WAIT, 0);
1629 }
Doug Anderson9623b5b2012-07-25 08:33:17 -07001630 }
1631}
1632
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301633static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1634{
1635 struct dw_mci_slot *slot = mmc_priv(mmc);
1636 struct dw_mci *host = slot->host;
Doug Andersonf8c58c12014-12-02 15:42:47 -08001637 unsigned long irqflags;
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301638 u32 int_mask;
1639
Doug Andersonf8c58c12014-12-02 15:42:47 -08001640 spin_lock_irqsave(&host->irq_lock, irqflags);
1641
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301642 /* Enable/disable Slot Specific SDIO interrupt */
1643 int_mask = mci_readl(host, INTMASK);
Doug Andersonb24c8b22014-12-02 15:42:46 -08001644 if (enb)
1645 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1646 else
1647 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1648 mci_writel(host, INTMASK, int_mask);
Doug Andersonf8c58c12014-12-02 15:42:47 -08001649
1650 spin_unlock_irqrestore(&host->irq_lock, irqflags);
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301651}
1652
Seungwon Jeon0976f162013-08-31 00:12:42 +09001653static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1654{
1655 struct dw_mci_slot *slot = mmc_priv(mmc);
1656 struct dw_mci *host = slot->host;
1657 const struct dw_mci_drv_data *drv_data = host->drv_data;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08001658 int err = -EINVAL;
Seungwon Jeon0976f162013-08-31 00:12:42 +09001659
Seungwon Jeon0976f162013-08-31 00:12:42 +09001660 if (drv_data && drv_data->execute_tuning)
Chaotian Jing9979dbe2015-10-27 14:24:28 +08001661 err = drv_data->execute_tuning(slot, opcode);
Seungwon Jeon0976f162013-08-31 00:12:42 +09001662 return err;
1663}
1664
Shawn Lin0e3a22c2015-08-03 15:07:21 +08001665static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1666 struct mmc_ios *ios)
Seungwon Jeon80113132015-01-29 08:11:57 +05301667{
1668 struct dw_mci_slot *slot = mmc_priv(mmc);
1669 struct dw_mci *host = slot->host;
1670 const struct dw_mci_drv_data *drv_data = host->drv_data;
1671
1672 if (drv_data && drv_data->prepare_hs400_tuning)
1673 return drv_data->prepare_hs400_tuning(host, ios);
1674
1675 return 0;
1676}
1677
Will Newtonf95f3852011-01-02 01:11:59 -05001678static const struct mmc_host_ops dw_mci_ops = {
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301679 .request = dw_mci_request,
Seungwon Jeon9aa51402012-02-06 16:55:07 +09001680 .pre_req = dw_mci_pre_req,
1681 .post_req = dw_mci_post_req,
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301682 .set_ios = dw_mci_set_ios,
1683 .get_ro = dw_mci_get_ro,
1684 .get_cd = dw_mci_get_cd,
Shawn Lin935a6652016-01-14 09:08:02 +08001685 .hw_reset = dw_mci_hw_reset,
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05301686 .enable_sdio_irq = dw_mci_enable_sdio_irq,
Seungwon Jeon0976f162013-08-31 00:12:42 +09001687 .execute_tuning = dw_mci_execute_tuning,
Doug Anderson01730552014-08-22 19:17:51 +05301688 .card_busy = dw_mci_card_busy,
1689 .start_signal_voltage_switch = dw_mci_switch_voltage,
Doug Andersonb24c8b22014-12-02 15:42:46 -08001690 .init_card = dw_mci_init_card,
Seungwon Jeon80113132015-01-29 08:11:57 +05301691 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
Will Newtonf95f3852011-01-02 01:11:59 -05001692};
1693
1694static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1695 __releases(&host->lock)
1696 __acquires(&host->lock)
1697{
1698 struct dw_mci_slot *slot;
1699 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1700
1701 WARN_ON(host->cmd || host->data);
1702
1703 host->cur_slot->mrq = NULL;
1704 host->mrq = NULL;
1705 if (!list_empty(&host->queue)) {
1706 slot = list_entry(host->queue.next,
1707 struct dw_mci_slot, queue_node);
1708 list_del(&slot->queue_node);
Thomas Abraham4a909202012-09-17 18:16:35 +00001709 dev_vdbg(host->dev, "list not empty: %s is next\n",
Will Newtonf95f3852011-01-02 01:11:59 -05001710 mmc_hostname(slot->mmc));
1711 host->state = STATE_SENDING_CMD;
1712 dw_mci_start_request(host, slot);
1713 } else {
Thomas Abraham4a909202012-09-17 18:16:35 +00001714 dev_vdbg(host->dev, "list empty\n");
Doug Anderson01730552014-08-22 19:17:51 +05301715
1716 if (host->state == STATE_SENDING_CMD11)
1717 host->state = STATE_WAITING_CMD11_DONE;
1718 else
1719 host->state = STATE_IDLE;
Will Newtonf95f3852011-01-02 01:11:59 -05001720 }
1721
1722 spin_unlock(&host->lock);
1723 mmc_request_done(prev_mmc, mrq);
1724 spin_lock(&host->lock);
1725}
1726
Seungwon Jeone352c812013-08-31 00:14:17 +09001727static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
Will Newtonf95f3852011-01-02 01:11:59 -05001728{
1729 u32 status = host->cmd_status;
1730
1731 host->cmd_status = 0;
1732
1733 /* Read the response from the card (up to 16 bytes) */
1734 if (cmd->flags & MMC_RSP_PRESENT) {
1735 if (cmd->flags & MMC_RSP_136) {
1736 cmd->resp[3] = mci_readl(host, RESP0);
1737 cmd->resp[2] = mci_readl(host, RESP1);
1738 cmd->resp[1] = mci_readl(host, RESP2);
1739 cmd->resp[0] = mci_readl(host, RESP3);
1740 } else {
1741 cmd->resp[0] = mci_readl(host, RESP0);
1742 cmd->resp[1] = 0;
1743 cmd->resp[2] = 0;
1744 cmd->resp[3] = 0;
1745 }
1746 }
1747
1748 if (status & SDMMC_INT_RTO)
1749 cmd->error = -ETIMEDOUT;
1750 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1751 cmd->error = -EILSEQ;
1752 else if (status & SDMMC_INT_RESP_ERR)
1753 cmd->error = -EIO;
1754 else
1755 cmd->error = 0;
1756
Seungwon Jeone352c812013-08-31 00:14:17 +09001757 return cmd->error;
1758}
1759
1760static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1761{
Seungwon Jeon31bff452013-08-31 00:14:23 +09001762 u32 status = host->data_status;
Seungwon Jeone352c812013-08-31 00:14:17 +09001763
1764 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1765 if (status & SDMMC_INT_DRTO) {
1766 data->error = -ETIMEDOUT;
1767 } else if (status & SDMMC_INT_DCRC) {
1768 data->error = -EILSEQ;
1769 } else if (status & SDMMC_INT_EBE) {
1770 if (host->dir_status ==
1771 DW_MCI_SEND_STATUS) {
1772 /*
1773 * No data CRC status was returned.
1774 * The number of bytes transferred
1775 * will be exaggerated in PIO mode.
1776 */
1777 data->bytes_xfered = 0;
1778 data->error = -ETIMEDOUT;
1779 } else if (host->dir_status ==
1780 DW_MCI_RECV_STATUS) {
Shawn Line7a1dec2016-08-22 10:57:16 +08001781 data->error = -EILSEQ;
Seungwon Jeone352c812013-08-31 00:14:17 +09001782 }
1783 } else {
1784 /* SDMMC_INT_SBE is included */
Shawn Line7a1dec2016-08-22 10:57:16 +08001785 data->error = -EILSEQ;
Seungwon Jeone352c812013-08-31 00:14:17 +09001786 }
1787
Doug Andersone6cc0122014-04-22 16:51:21 -07001788 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
Seungwon Jeone352c812013-08-31 00:14:17 +09001789
1790 /*
1791 * After an error, there may be data lingering
Seungwon Jeon31bff452013-08-31 00:14:23 +09001792 * in the FIFO
Seungwon Jeone352c812013-08-31 00:14:17 +09001793 */
Sonny Rao3a33a942014-08-04 18:19:50 -07001794 dw_mci_reset(host);
Seungwon Jeone352c812013-08-31 00:14:17 +09001795 } else {
1796 data->bytes_xfered = data->blocks * data->blksz;
1797 data->error = 0;
1798 }
1799
1800 return data->error;
Will Newtonf95f3852011-01-02 01:11:59 -05001801}
1802
Addy Ke57e10482015-08-11 01:27:18 +09001803static void dw_mci_set_drto(struct dw_mci *host)
1804{
1805 unsigned int drto_clks;
1806 unsigned int drto_ms;
1807
1808 drto_clks = mci_readl(host, TMOUT) >> 8;
1809 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1810
1811 /* add a bit spare time */
1812 drto_ms += 10;
1813
1814 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1815}
1816
Will Newtonf95f3852011-01-02 01:11:59 -05001817static void dw_mci_tasklet_func(unsigned long priv)
1818{
1819 struct dw_mci *host = (struct dw_mci *)priv;
1820 struct mmc_data *data;
1821 struct mmc_command *cmd;
Seungwon Jeone352c812013-08-31 00:14:17 +09001822 struct mmc_request *mrq;
Will Newtonf95f3852011-01-02 01:11:59 -05001823 enum dw_mci_state state;
1824 enum dw_mci_state prev_state;
Seungwon Jeone352c812013-08-31 00:14:17 +09001825 unsigned int err;
Will Newtonf95f3852011-01-02 01:11:59 -05001826
1827 spin_lock(&host->lock);
1828
1829 state = host->state;
1830 data = host->data;
Seungwon Jeone352c812013-08-31 00:14:17 +09001831 mrq = host->mrq;
Will Newtonf95f3852011-01-02 01:11:59 -05001832
1833 do {
1834 prev_state = state;
1835
1836 switch (state) {
1837 case STATE_IDLE:
Doug Anderson01730552014-08-22 19:17:51 +05301838 case STATE_WAITING_CMD11_DONE:
Will Newtonf95f3852011-01-02 01:11:59 -05001839 break;
1840
Doug Anderson01730552014-08-22 19:17:51 +05301841 case STATE_SENDING_CMD11:
Will Newtonf95f3852011-01-02 01:11:59 -05001842 case STATE_SENDING_CMD:
1843 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1844 &host->pending_events))
1845 break;
1846
1847 cmd = host->cmd;
1848 host->cmd = NULL;
1849 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
Seungwon Jeone352c812013-08-31 00:14:17 +09001850 err = dw_mci_command_complete(host, cmd);
1851 if (cmd == mrq->sbc && !err) {
Seungwon Jeon053b3ce2011-12-22 18:01:29 +09001852 prev_state = state = STATE_SENDING_CMD;
1853 __dw_mci_start_request(host, host->cur_slot,
Seungwon Jeone352c812013-08-31 00:14:17 +09001854 mrq->cmd);
Seungwon Jeon053b3ce2011-12-22 18:01:29 +09001855 goto unlock;
1856 }
1857
Seungwon Jeone352c812013-08-31 00:14:17 +09001858 if (cmd->data && err) {
Doug Anderson46d17952016-04-26 10:03:58 +02001859 /*
1860 * During UHS tuning sequence, sending the stop
1861 * command after the response CRC error would
1862 * throw the system into a confused state
1863 * causing all future tuning phases to report
1864 * failure.
1865 *
1866 * In such case controller will move into a data
1867 * transfer state after a response error or
1868 * response CRC error. Let's let that finish
1869 * before trying to send a stop, so we'll go to
1870 * STATE_SENDING_DATA.
1871 *
1872 * Although letting the data transfer take place
1873 * will waste a bit of time (we already know
1874 * the command was bad), it can't cause any
1875 * errors since it's possible it would have
1876 * taken place anyway if this tasklet got
1877 * delayed. Allowing the transfer to take place
1878 * avoids races and keeps things simple.
1879 */
1880 if ((err != -ETIMEDOUT) &&
1881 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1882 state = STATE_SENDING_DATA;
1883 continue;
1884 }
1885
Seungwon Jeon71abb132013-08-31 00:13:59 +09001886 dw_mci_stop_dma(host);
Seungwon Jeon90c21432013-08-31 00:14:05 +09001887 send_stop_abort(host, data);
1888 state = STATE_SENDING_STOP;
1889 break;
Seungwon Jeon71abb132013-08-31 00:13:59 +09001890 }
1891
Seungwon Jeone352c812013-08-31 00:14:17 +09001892 if (!cmd->data || err) {
1893 dw_mci_request_end(host, mrq);
Will Newtonf95f3852011-01-02 01:11:59 -05001894 goto unlock;
1895 }
1896
1897 prev_state = state = STATE_SENDING_DATA;
1898 /* fall through */
1899
1900 case STATE_SENDING_DATA:
Doug Anderson2aa35462014-08-13 08:13:43 -07001901 /*
1902 * We could get a data error and never a transfer
1903 * complete so we'd better check for it here.
1904 *
1905 * Note that we don't really care if we also got a
1906 * transfer complete; stopping the DMA and sending an
1907 * abort won't hurt.
1908 */
Will Newtonf95f3852011-01-02 01:11:59 -05001909 if (test_and_clear_bit(EVENT_DATA_ERROR,
1910 &host->pending_events)) {
1911 dw_mci_stop_dma(host);
Jaehoon Chunge13c3c02016-11-17 16:40:37 +09001912 if (!(host->data_status & (SDMMC_INT_DRTO |
addy kebdb9a902015-02-20 10:55:25 +08001913 SDMMC_INT_EBE)))
1914 send_stop_abort(host, data);
Will Newtonf95f3852011-01-02 01:11:59 -05001915 state = STATE_DATA_ERROR;
1916 break;
1917 }
1918
1919 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
Addy Ke57e10482015-08-11 01:27:18 +09001920 &host->pending_events)) {
1921 /*
1922 * If all data-related interrupts don't come
1923 * within the given time in reading data state.
1924 */
Jaehoon Chung16a34572016-06-21 14:35:37 +09001925 if (host->dir_status == DW_MCI_RECV_STATUS)
Addy Ke57e10482015-08-11 01:27:18 +09001926 dw_mci_set_drto(host);
Will Newtonf95f3852011-01-02 01:11:59 -05001927 break;
Addy Ke57e10482015-08-11 01:27:18 +09001928 }
Will Newtonf95f3852011-01-02 01:11:59 -05001929
1930 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
Doug Anderson2aa35462014-08-13 08:13:43 -07001931
1932 /*
1933 * Handle an EVENT_DATA_ERROR that might have shown up
1934 * before the transfer completed. This might not have
1935 * been caught by the check above because the interrupt
1936 * could have gone off between the previous check and
1937 * the check for transfer complete.
1938 *
1939 * Technically this ought not be needed assuming we
1940 * get a DATA_COMPLETE eventually (we'll notice the
1941 * error and end the request), but it shouldn't hurt.
1942 *
1943 * This has the advantage of sending the stop command.
1944 */
1945 if (test_and_clear_bit(EVENT_DATA_ERROR,
1946 &host->pending_events)) {
1947 dw_mci_stop_dma(host);
Jaehoon Chunge13c3c02016-11-17 16:40:37 +09001948 if (!(host->data_status & (SDMMC_INT_DRTO |
addy kebdb9a902015-02-20 10:55:25 +08001949 SDMMC_INT_EBE)))
1950 send_stop_abort(host, data);
Doug Anderson2aa35462014-08-13 08:13:43 -07001951 state = STATE_DATA_ERROR;
1952 break;
1953 }
Will Newtonf95f3852011-01-02 01:11:59 -05001954 prev_state = state = STATE_DATA_BUSY;
Doug Anderson2aa35462014-08-13 08:13:43 -07001955
Will Newtonf95f3852011-01-02 01:11:59 -05001956 /* fall through */
1957
1958 case STATE_DATA_BUSY:
1959 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
Addy Ke57e10482015-08-11 01:27:18 +09001960 &host->pending_events)) {
1961 /*
1962 * If data error interrupt comes but data over
1963 * interrupt doesn't come within the given time.
1964 * in reading data state.
1965 */
Jaehoon Chung16a34572016-06-21 14:35:37 +09001966 if (host->dir_status == DW_MCI_RECV_STATUS)
Addy Ke57e10482015-08-11 01:27:18 +09001967 dw_mci_set_drto(host);
Will Newtonf95f3852011-01-02 01:11:59 -05001968 break;
Addy Ke57e10482015-08-11 01:27:18 +09001969 }
Will Newtonf95f3852011-01-02 01:11:59 -05001970
1971 host->data = NULL;
1972 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
Seungwon Jeone352c812013-08-31 00:14:17 +09001973 err = dw_mci_data_complete(host, data);
Will Newtonf95f3852011-01-02 01:11:59 -05001974
Seungwon Jeone352c812013-08-31 00:14:17 +09001975 if (!err) {
1976 if (!data->stop || mrq->sbc) {
Sachin Kamat17c8bc82014-02-25 15:18:28 +05301977 if (mrq->sbc && data->stop)
Seungwon Jeone352c812013-08-31 00:14:17 +09001978 data->stop->error = 0;
1979 dw_mci_request_end(host, mrq);
1980 goto unlock;
Will Newtonf95f3852011-01-02 01:11:59 -05001981 }
Will Newtonf95f3852011-01-02 01:11:59 -05001982
Seungwon Jeon90c21432013-08-31 00:14:05 +09001983 /* stop command for open-ended transfer*/
Seungwon Jeone352c812013-08-31 00:14:17 +09001984 if (data->stop)
1985 send_stop_abort(host, data);
Doug Anderson2aa35462014-08-13 08:13:43 -07001986 } else {
1987 /*
1988 * If we don't have a command complete now we'll
1989 * never get one since we just reset everything;
1990 * better end the request.
1991 *
1992 * If we do have a command complete we'll fall
1993 * through to the SENDING_STOP command and
1994 * everything will be peachy keen.
1995 */
1996 if (!test_bit(EVENT_CMD_COMPLETE,
1997 &host->pending_events)) {
1998 host->cmd = NULL;
1999 dw_mci_request_end(host, mrq);
2000 goto unlock;
2001 }
Seungwon Jeon90c21432013-08-31 00:14:05 +09002002 }
Seungwon Jeone352c812013-08-31 00:14:17 +09002003
2004 /*
2005 * If err has non-zero,
2006 * stop-abort command has been already issued.
2007 */
2008 prev_state = state = STATE_SENDING_STOP;
2009
Will Newtonf95f3852011-01-02 01:11:59 -05002010 /* fall through */
2011
2012 case STATE_SENDING_STOP:
2013 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2014 &host->pending_events))
2015 break;
2016
Seungwon Jeon71abb132013-08-31 00:13:59 +09002017 /* CMD error in data command */
Seungwon Jeon31bff452013-08-31 00:14:23 +09002018 if (mrq->cmd->error && mrq->data)
Sonny Rao3a33a942014-08-04 18:19:50 -07002019 dw_mci_reset(host);
Seungwon Jeon71abb132013-08-31 00:13:59 +09002020
Will Newtonf95f3852011-01-02 01:11:59 -05002021 host->cmd = NULL;
Seungwon Jeon71abb132013-08-31 00:13:59 +09002022 host->data = NULL;
Seungwon Jeon90c21432013-08-31 00:14:05 +09002023
Jaehoon Chunge13c3c02016-11-17 16:40:37 +09002024 if (!mrq->sbc && mrq->stop)
Seungwon Jeone352c812013-08-31 00:14:17 +09002025 dw_mci_command_complete(host, mrq->stop);
Seungwon Jeon90c21432013-08-31 00:14:05 +09002026 else
2027 host->cmd_status = 0;
2028
Seungwon Jeone352c812013-08-31 00:14:17 +09002029 dw_mci_request_end(host, mrq);
Will Newtonf95f3852011-01-02 01:11:59 -05002030 goto unlock;
2031
2032 case STATE_DATA_ERROR:
2033 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2034 &host->pending_events))
2035 break;
2036
2037 state = STATE_DATA_BUSY;
2038 break;
2039 }
2040 } while (state != prev_state);
2041
2042 host->state = state;
2043unlock:
2044 spin_unlock(&host->lock);
2045
2046}
2047
James Hogan34b664a2011-06-24 13:57:56 +01002048/* push final bytes to part_buf, only use during push */
2049static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2050{
2051 memcpy((void *)&host->part_buf, buf, cnt);
2052 host->part_buf_count = cnt;
2053}
2054
2055/* append bytes to part_buf, only use during push */
2056static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2057{
2058 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2059 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2060 host->part_buf_count += cnt;
2061 return cnt;
2062}
2063
2064/* pull first bytes from part_buf, only use during pull */
2065static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2066{
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002067 cnt = min_t(int, cnt, host->part_buf_count);
James Hogan34b664a2011-06-24 13:57:56 +01002068 if (cnt) {
2069 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2070 cnt);
2071 host->part_buf_count -= cnt;
2072 host->part_buf_start += cnt;
2073 }
2074 return cnt;
2075}
2076
2077/* pull final bytes from the part_buf, assuming it's just been filled */
2078static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2079{
2080 memcpy(buf, &host->part_buf, cnt);
2081 host->part_buf_start = cnt;
2082 host->part_buf_count = (1 << host->data_shift) - cnt;
2083}
2084
Will Newtonf95f3852011-01-02 01:11:59 -05002085static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2086{
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002087 struct mmc_data *data = host->data;
2088 int init_cnt = cnt;
2089
James Hogan34b664a2011-06-24 13:57:56 +01002090 /* try and push anything in the part_buf */
2091 if (unlikely(host->part_buf_count)) {
2092 int len = dw_mci_push_part_bytes(host, buf, cnt);
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002093
James Hogan34b664a2011-06-24 13:57:56 +01002094 buf += len;
2095 cnt -= len;
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002096 if (host->part_buf_count == 2) {
Ben Dooks76184ac2015-03-25 11:27:52 +00002097 mci_fifo_writew(host->fifo_reg, host->part_buf16);
James Hogan34b664a2011-06-24 13:57:56 +01002098 host->part_buf_count = 0;
2099 }
2100 }
2101#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2102 if (unlikely((unsigned long)buf & 0x1)) {
2103 while (cnt >= 2) {
2104 u16 aligned_buf[64];
2105 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2106 int items = len >> 1;
2107 int i;
2108 /* memcpy from input buffer into aligned buffer */
2109 memcpy(aligned_buf, buf, len);
2110 buf += len;
2111 cnt -= len;
2112 /* push data from aligned buffer into fifo */
2113 for (i = 0; i < items; ++i)
Ben Dooks76184ac2015-03-25 11:27:52 +00002114 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
James Hogan34b664a2011-06-24 13:57:56 +01002115 }
2116 } else
2117#endif
2118 {
2119 u16 *pdata = buf;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002120
James Hogan34b664a2011-06-24 13:57:56 +01002121 for (; cnt >= 2; cnt -= 2)
Ben Dooks76184ac2015-03-25 11:27:52 +00002122 mci_fifo_writew(host->fifo_reg, *pdata++);
James Hogan34b664a2011-06-24 13:57:56 +01002123 buf = pdata;
2124 }
2125 /* put anything remaining in the part_buf */
2126 if (cnt) {
2127 dw_mci_set_part_bytes(host, buf, cnt);
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002128 /* Push data if we have reached the expected data length */
2129 if ((data->bytes_xfered + init_cnt) ==
2130 (data->blksz * data->blocks))
Ben Dooks76184ac2015-03-25 11:27:52 +00002131 mci_fifo_writew(host->fifo_reg, host->part_buf16);
Will Newtonf95f3852011-01-02 01:11:59 -05002132 }
2133}
2134
2135static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2136{
James Hogan34b664a2011-06-24 13:57:56 +01002137#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2138 if (unlikely((unsigned long)buf & 0x1)) {
2139 while (cnt >= 2) {
2140 /* pull data from fifo into aligned buffer */
2141 u16 aligned_buf[64];
2142 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2143 int items = len >> 1;
2144 int i;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002145
James Hogan34b664a2011-06-24 13:57:56 +01002146 for (i = 0; i < items; ++i)
Ben Dooks76184ac2015-03-25 11:27:52 +00002147 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002148 /* memcpy from aligned buffer into output buffer */
2149 memcpy(buf, aligned_buf, len);
2150 buf += len;
2151 cnt -= len;
2152 }
2153 } else
2154#endif
2155 {
2156 u16 *pdata = buf;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002157
James Hogan34b664a2011-06-24 13:57:56 +01002158 for (; cnt >= 2; cnt -= 2)
Ben Dooks76184ac2015-03-25 11:27:52 +00002159 *pdata++ = mci_fifo_readw(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002160 buf = pdata;
2161 }
2162 if (cnt) {
Ben Dooks76184ac2015-03-25 11:27:52 +00002163 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002164 dw_mci_pull_final_bytes(host, buf, cnt);
Will Newtonf95f3852011-01-02 01:11:59 -05002165 }
2166}
2167
2168static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2169{
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002170 struct mmc_data *data = host->data;
2171 int init_cnt = cnt;
2172
James Hogan34b664a2011-06-24 13:57:56 +01002173 /* try and push anything in the part_buf */
2174 if (unlikely(host->part_buf_count)) {
2175 int len = dw_mci_push_part_bytes(host, buf, cnt);
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002176
James Hogan34b664a2011-06-24 13:57:56 +01002177 buf += len;
2178 cnt -= len;
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002179 if (host->part_buf_count == 4) {
Ben Dooks76184ac2015-03-25 11:27:52 +00002180 mci_fifo_writel(host->fifo_reg, host->part_buf32);
James Hogan34b664a2011-06-24 13:57:56 +01002181 host->part_buf_count = 0;
2182 }
2183 }
2184#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2185 if (unlikely((unsigned long)buf & 0x3)) {
2186 while (cnt >= 4) {
2187 u32 aligned_buf[32];
2188 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2189 int items = len >> 2;
2190 int i;
2191 /* memcpy from input buffer into aligned buffer */
2192 memcpy(aligned_buf, buf, len);
2193 buf += len;
2194 cnt -= len;
2195 /* push data from aligned buffer into fifo */
2196 for (i = 0; i < items; ++i)
Ben Dooks76184ac2015-03-25 11:27:52 +00002197 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
James Hogan34b664a2011-06-24 13:57:56 +01002198 }
2199 } else
2200#endif
2201 {
2202 u32 *pdata = buf;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002203
James Hogan34b664a2011-06-24 13:57:56 +01002204 for (; cnt >= 4; cnt -= 4)
Ben Dooks76184ac2015-03-25 11:27:52 +00002205 mci_fifo_writel(host->fifo_reg, *pdata++);
James Hogan34b664a2011-06-24 13:57:56 +01002206 buf = pdata;
2207 }
2208 /* put anything remaining in the part_buf */
2209 if (cnt) {
2210 dw_mci_set_part_bytes(host, buf, cnt);
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002211 /* Push data if we have reached the expected data length */
2212 if ((data->bytes_xfered + init_cnt) ==
2213 (data->blksz * data->blocks))
Ben Dooks76184ac2015-03-25 11:27:52 +00002214 mci_fifo_writel(host->fifo_reg, host->part_buf32);
Will Newtonf95f3852011-01-02 01:11:59 -05002215 }
2216}
2217
2218static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2219{
James Hogan34b664a2011-06-24 13:57:56 +01002220#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2221 if (unlikely((unsigned long)buf & 0x3)) {
2222 while (cnt >= 4) {
2223 /* pull data from fifo into aligned buffer */
2224 u32 aligned_buf[32];
2225 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2226 int items = len >> 2;
2227 int i;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002228
James Hogan34b664a2011-06-24 13:57:56 +01002229 for (i = 0; i < items; ++i)
Ben Dooks76184ac2015-03-25 11:27:52 +00002230 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002231 /* memcpy from aligned buffer into output buffer */
2232 memcpy(buf, aligned_buf, len);
2233 buf += len;
2234 cnt -= len;
2235 }
2236 } else
2237#endif
2238 {
2239 u32 *pdata = buf;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002240
James Hogan34b664a2011-06-24 13:57:56 +01002241 for (; cnt >= 4; cnt -= 4)
Ben Dooks76184ac2015-03-25 11:27:52 +00002242 *pdata++ = mci_fifo_readl(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002243 buf = pdata;
2244 }
2245 if (cnt) {
Ben Dooks76184ac2015-03-25 11:27:52 +00002246 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002247 dw_mci_pull_final_bytes(host, buf, cnt);
Will Newtonf95f3852011-01-02 01:11:59 -05002248 }
2249}
2250
2251static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2252{
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002253 struct mmc_data *data = host->data;
2254 int init_cnt = cnt;
2255
James Hogan34b664a2011-06-24 13:57:56 +01002256 /* try and push anything in the part_buf */
2257 if (unlikely(host->part_buf_count)) {
2258 int len = dw_mci_push_part_bytes(host, buf, cnt);
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002259
James Hogan34b664a2011-06-24 13:57:56 +01002260 buf += len;
2261 cnt -= len;
Seungwon Jeonc09fbd72013-03-25 16:28:22 +09002262
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002263 if (host->part_buf_count == 8) {
Ben Dooks76184ac2015-03-25 11:27:52 +00002264 mci_fifo_writeq(host->fifo_reg, host->part_buf);
James Hogan34b664a2011-06-24 13:57:56 +01002265 host->part_buf_count = 0;
2266 }
2267 }
2268#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2269 if (unlikely((unsigned long)buf & 0x7)) {
2270 while (cnt >= 8) {
2271 u64 aligned_buf[16];
2272 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2273 int items = len >> 3;
2274 int i;
2275 /* memcpy from input buffer into aligned buffer */
2276 memcpy(aligned_buf, buf, len);
2277 buf += len;
2278 cnt -= len;
2279 /* push data from aligned buffer into fifo */
2280 for (i = 0; i < items; ++i)
Ben Dooks76184ac2015-03-25 11:27:52 +00002281 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
James Hogan34b664a2011-06-24 13:57:56 +01002282 }
2283 } else
2284#endif
2285 {
2286 u64 *pdata = buf;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002287
James Hogan34b664a2011-06-24 13:57:56 +01002288 for (; cnt >= 8; cnt -= 8)
Ben Dooks76184ac2015-03-25 11:27:52 +00002289 mci_fifo_writeq(host->fifo_reg, *pdata++);
James Hogan34b664a2011-06-24 13:57:56 +01002290 buf = pdata;
2291 }
2292 /* put anything remaining in the part_buf */
2293 if (cnt) {
2294 dw_mci_set_part_bytes(host, buf, cnt);
Markos Chandrascfbeb59c2013-03-12 10:53:13 +00002295 /* Push data if we have reached the expected data length */
2296 if ((data->bytes_xfered + init_cnt) ==
2297 (data->blksz * data->blocks))
Ben Dooks76184ac2015-03-25 11:27:52 +00002298 mci_fifo_writeq(host->fifo_reg, host->part_buf);
Will Newtonf95f3852011-01-02 01:11:59 -05002299 }
2300}
2301
2302static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2303{
James Hogan34b664a2011-06-24 13:57:56 +01002304#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2305 if (unlikely((unsigned long)buf & 0x7)) {
2306 while (cnt >= 8) {
2307 /* pull data from fifo into aligned buffer */
2308 u64 aligned_buf[16];
2309 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2310 int items = len >> 3;
2311 int i;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002312
James Hogan34b664a2011-06-24 13:57:56 +01002313 for (i = 0; i < items; ++i)
Ben Dooks76184ac2015-03-25 11:27:52 +00002314 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2315
James Hogan34b664a2011-06-24 13:57:56 +01002316 /* memcpy from aligned buffer into output buffer */
2317 memcpy(buf, aligned_buf, len);
2318 buf += len;
2319 cnt -= len;
2320 }
2321 } else
2322#endif
2323 {
2324 u64 *pdata = buf;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002325
James Hogan34b664a2011-06-24 13:57:56 +01002326 for (; cnt >= 8; cnt -= 8)
Ben Dooks76184ac2015-03-25 11:27:52 +00002327 *pdata++ = mci_fifo_readq(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002328 buf = pdata;
Will Newtonf95f3852011-01-02 01:11:59 -05002329 }
James Hogan34b664a2011-06-24 13:57:56 +01002330 if (cnt) {
Ben Dooks76184ac2015-03-25 11:27:52 +00002331 host->part_buf = mci_fifo_readq(host->fifo_reg);
James Hogan34b664a2011-06-24 13:57:56 +01002332 dw_mci_pull_final_bytes(host, buf, cnt);
2333 }
2334}
2335
2336static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2337{
2338 int len;
2339
2340 /* get remaining partial bytes */
2341 len = dw_mci_pull_part_bytes(host, buf, cnt);
2342 if (unlikely(len == cnt))
2343 return;
2344 buf += len;
2345 cnt -= len;
2346
2347 /* get the rest of the data */
2348 host->pull_data(host, buf, cnt);
Will Newtonf95f3852011-01-02 01:11:59 -05002349}
2350
Kyoungil Kim87a74d32013-01-22 16:46:30 +09002351static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
Will Newtonf95f3852011-01-02 01:11:59 -05002352{
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002353 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2354 void *buf;
2355 unsigned int offset;
Will Newtonf95f3852011-01-02 01:11:59 -05002356 struct mmc_data *data = host->data;
2357 int shift = host->data_shift;
2358 u32 status;
Markos Chandras3e4b0d82013-03-22 12:50:05 -04002359 unsigned int len;
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002360 unsigned int remain, fcnt;
Will Newtonf95f3852011-01-02 01:11:59 -05002361
2362 do {
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002363 if (!sg_miter_next(sg_miter))
2364 goto done;
Will Newtonf95f3852011-01-02 01:11:59 -05002365
Imre Deak4225fc82013-02-27 17:02:57 -08002366 host->sg = sg_miter->piter.sg;
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002367 buf = sg_miter->addr;
2368 remain = sg_miter->length;
2369 offset = 0;
2370
2371 do {
2372 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2373 << shift) + host->part_buf_count;
2374 len = min(remain, fcnt);
2375 if (!len)
2376 break;
2377 dw_mci_pull_data(host, (void *)(buf + offset), len);
Markos Chandras3e4b0d82013-03-22 12:50:05 -04002378 data->bytes_xfered += len;
Will Newtonf95f3852011-01-02 01:11:59 -05002379 offset += len;
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002380 remain -= len;
2381 } while (remain);
Will Newtonf95f3852011-01-02 01:11:59 -05002382
Seungwon Jeone74f3a92012-08-01 09:30:46 +09002383 sg_miter->consumed = offset;
Will Newtonf95f3852011-01-02 01:11:59 -05002384 status = mci_readl(host, MINTSTS);
2385 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
Kyoungil Kim87a74d32013-01-22 16:46:30 +09002386 /* if the RXDR is ready read again */
2387 } while ((status & SDMMC_INT_RXDR) ||
2388 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002389
2390 if (!remain) {
2391 if (!sg_miter_next(sg_miter))
2392 goto done;
2393 sg_miter->consumed = 0;
2394 }
2395 sg_miter_stop(sg_miter);
Will Newtonf95f3852011-01-02 01:11:59 -05002396 return;
2397
2398done:
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002399 sg_miter_stop(sg_miter);
2400 host->sg = NULL;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002401 smp_wmb(); /* drain writebuffer */
Will Newtonf95f3852011-01-02 01:11:59 -05002402 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2403}
2404
2405static void dw_mci_write_data_pio(struct dw_mci *host)
2406{
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002407 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2408 void *buf;
2409 unsigned int offset;
Will Newtonf95f3852011-01-02 01:11:59 -05002410 struct mmc_data *data = host->data;
2411 int shift = host->data_shift;
2412 u32 status;
Markos Chandras3e4b0d82013-03-22 12:50:05 -04002413 unsigned int len;
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002414 unsigned int fifo_depth = host->fifo_depth;
2415 unsigned int remain, fcnt;
Will Newtonf95f3852011-01-02 01:11:59 -05002416
2417 do {
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002418 if (!sg_miter_next(sg_miter))
2419 goto done;
Will Newtonf95f3852011-01-02 01:11:59 -05002420
Imre Deak4225fc82013-02-27 17:02:57 -08002421 host->sg = sg_miter->piter.sg;
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002422 buf = sg_miter->addr;
2423 remain = sg_miter->length;
2424 offset = 0;
2425
2426 do {
2427 fcnt = ((fifo_depth -
2428 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2429 << shift) - host->part_buf_count;
2430 len = min(remain, fcnt);
2431 if (!len)
2432 break;
2433 host->push_data(host, (void *)(buf + offset), len);
Markos Chandras3e4b0d82013-03-22 12:50:05 -04002434 data->bytes_xfered += len;
Will Newtonf95f3852011-01-02 01:11:59 -05002435 offset += len;
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002436 remain -= len;
2437 } while (remain);
Will Newtonf95f3852011-01-02 01:11:59 -05002438
Seungwon Jeone74f3a92012-08-01 09:30:46 +09002439 sg_miter->consumed = offset;
Will Newtonf95f3852011-01-02 01:11:59 -05002440 status = mci_readl(host, MINTSTS);
2441 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
Will Newtonf95f3852011-01-02 01:11:59 -05002442 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002443
2444 if (!remain) {
2445 if (!sg_miter_next(sg_miter))
2446 goto done;
2447 sg_miter->consumed = 0;
2448 }
2449 sg_miter_stop(sg_miter);
Will Newtonf95f3852011-01-02 01:11:59 -05002450 return;
2451
2452done:
Seungwon Jeonf9c2a0d2012-02-09 14:32:43 +09002453 sg_miter_stop(sg_miter);
2454 host->sg = NULL;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002455 smp_wmb(); /* drain writebuffer */
Will Newtonf95f3852011-01-02 01:11:59 -05002456 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2457}
2458
2459static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2460{
2461 if (!host->cmd_status)
2462 host->cmd_status = status;
2463
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002464 smp_wmb(); /* drain writebuffer */
Will Newtonf95f3852011-01-02 01:11:59 -05002465
2466 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2467 tasklet_schedule(&host->tasklet);
2468}
2469
Doug Anderson6130e7a2014-10-14 09:33:09 -07002470static void dw_mci_handle_cd(struct dw_mci *host)
2471{
2472 int i;
2473
2474 for (i = 0; i < host->num_slots; i++) {
2475 struct dw_mci_slot *slot = host->slot[i];
2476
2477 if (!slot)
2478 continue;
2479
2480 if (slot->mmc->ops->card_event)
2481 slot->mmc->ops->card_event(slot->mmc);
2482 mmc_detect_change(slot->mmc,
2483 msecs_to_jiffies(host->pdata->detect_delay_ms));
2484 }
2485}
2486
Will Newtonf95f3852011-01-02 01:11:59 -05002487static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2488{
2489 struct dw_mci *host = dev_id;
Seungwon Jeon182c9082012-08-01 09:30:30 +09002490 u32 pending;
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05302491 int i;
Will Newtonf95f3852011-01-02 01:11:59 -05002492
Markos Chandras1fb5f682013-03-12 10:53:11 +00002493 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2494
2495 if (pending) {
Doug Anderson01730552014-08-22 19:17:51 +05302496 /* Check volt switch first, since it can look like an error */
2497 if ((host->state == STATE_SENDING_CMD11) &&
2498 (pending & SDMMC_INT_VOLT_SWITCH)) {
Doug Anderson49ba0302015-04-03 11:13:07 -07002499 unsigned long irqflags;
Doug Anderson5c935162015-03-09 16:18:21 -07002500
Doug Anderson01730552014-08-22 19:17:51 +05302501 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2502 pending &= ~SDMMC_INT_VOLT_SWITCH;
Doug Anderson49ba0302015-04-03 11:13:07 -07002503
2504 /*
2505 * Hold the lock; we know cmd11_timer can't be kicked
2506 * off after the lock is released, so safe to delete.
2507 */
2508 spin_lock_irqsave(&host->irq_lock, irqflags);
Doug Anderson01730552014-08-22 19:17:51 +05302509 dw_mci_cmd_interrupt(host, pending);
Doug Anderson49ba0302015-04-03 11:13:07 -07002510 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2511
2512 del_timer(&host->cmd11_timer);
Doug Anderson01730552014-08-22 19:17:51 +05302513 }
2514
Will Newtonf95f3852011-01-02 01:11:59 -05002515 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2516 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
Seungwon Jeon182c9082012-08-01 09:30:30 +09002517 host->cmd_status = pending;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002518 smp_wmb(); /* drain writebuffer */
Will Newtonf95f3852011-01-02 01:11:59 -05002519 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
Will Newtonf95f3852011-01-02 01:11:59 -05002520 }
2521
2522 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2523 /* if there is an error report DATA_ERROR */
2524 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
Seungwon Jeon182c9082012-08-01 09:30:30 +09002525 host->data_status = pending;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002526 smp_wmb(); /* drain writebuffer */
Will Newtonf95f3852011-01-02 01:11:59 -05002527 set_bit(EVENT_DATA_ERROR, &host->pending_events);
Seungwon Jeon9b2026a2012-08-01 09:30:40 +09002528 tasklet_schedule(&host->tasklet);
Will Newtonf95f3852011-01-02 01:11:59 -05002529 }
2530
2531 if (pending & SDMMC_INT_DATA_OVER) {
Jaehoon Chung16a34572016-06-21 14:35:37 +09002532 del_timer(&host->dto_timer);
Addy Ke57e10482015-08-11 01:27:18 +09002533
Will Newtonf95f3852011-01-02 01:11:59 -05002534 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2535 if (!host->data_status)
Seungwon Jeon182c9082012-08-01 09:30:30 +09002536 host->data_status = pending;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002537 smp_wmb(); /* drain writebuffer */
Will Newtonf95f3852011-01-02 01:11:59 -05002538 if (host->dir_status == DW_MCI_RECV_STATUS) {
2539 if (host->sg != NULL)
Kyoungil Kim87a74d32013-01-22 16:46:30 +09002540 dw_mci_read_data_pio(host, true);
Will Newtonf95f3852011-01-02 01:11:59 -05002541 }
2542 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2543 tasklet_schedule(&host->tasklet);
2544 }
2545
2546 if (pending & SDMMC_INT_RXDR) {
2547 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
James Hoganb40af3a2011-06-24 13:54:06 +01002548 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
Kyoungil Kim87a74d32013-01-22 16:46:30 +09002549 dw_mci_read_data_pio(host, false);
Will Newtonf95f3852011-01-02 01:11:59 -05002550 }
2551
2552 if (pending & SDMMC_INT_TXDR) {
2553 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
James Hoganb40af3a2011-06-24 13:54:06 +01002554 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
Will Newtonf95f3852011-01-02 01:11:59 -05002555 dw_mci_write_data_pio(host);
2556 }
2557
2558 if (pending & SDMMC_INT_CMD_DONE) {
2559 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
Seungwon Jeon182c9082012-08-01 09:30:30 +09002560 dw_mci_cmd_interrupt(host, pending);
Will Newtonf95f3852011-01-02 01:11:59 -05002561 }
2562
2563 if (pending & SDMMC_INT_CD) {
2564 mci_writel(host, RINTSTS, SDMMC_INT_CD);
Doug Anderson6130e7a2014-10-14 09:33:09 -07002565 dw_mci_handle_cd(host);
Will Newtonf95f3852011-01-02 01:11:59 -05002566 }
2567
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05302568 /* Handle SDIO Interrupts */
2569 for (i = 0; i < host->num_slots; i++) {
2570 struct dw_mci_slot *slot = host->slot[i];
Doug Andersoned2540e2015-02-25 10:11:52 -08002571
2572 if (!slot)
2573 continue;
2574
Addy Ke76756232014-11-04 22:03:09 +08002575 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2576 mci_writel(host, RINTSTS,
2577 SDMMC_INT_SDIO(slot->sdio_id));
Shashidhar Hiremath1a5c8e12011-08-29 13:11:46 +05302578 mmc_signal_sdio_irq(slot->mmc);
2579 }
2580 }
2581
Markos Chandras1fb5f682013-03-12 10:53:11 +00002582 }
Will Newtonf95f3852011-01-02 01:11:59 -05002583
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002584 if (host->use_dma != TRANS_MODE_IDMAC)
2585 return IRQ_HANDLED;
2586
2587 /* Handle IDMA interrupts */
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +00002588 if (host->dma_64bit_address == 1) {
2589 pending = mci_readl(host, IDSTS64);
2590 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2591 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2592 SDMMC_IDMAC_INT_RI);
2593 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
Shawn Linfaecf412016-06-24 15:39:52 +08002594 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2595 host->dma_ops->complete((void *)host);
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +00002596 }
2597 } else {
2598 pending = mci_readl(host, IDSTS);
2599 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2600 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2601 SDMMC_IDMAC_INT_RI);
2602 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
Shawn Linfaecf412016-06-24 15:39:52 +08002603 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2604 host->dma_ops->complete((void *)host);
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +00002605 }
Will Newtonf95f3852011-01-02 01:11:59 -05002606 }
Will Newtonf95f3852011-01-02 01:11:59 -05002607
2608 return IRQ_HANDLED;
2609}
2610
Jaehoon Chung36c179a2012-08-23 20:31:48 +09002611static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
Will Newtonf95f3852011-01-02 01:11:59 -05002612{
2613 struct mmc_host *mmc;
2614 struct dw_mci_slot *slot;
Arnd Bergmanne95baf12012-11-08 14:26:11 +00002615 const struct dw_mci_drv_data *drv_data = host->drv_data;
Thomas Abraham800d78b2012-09-17 18:16:42 +00002616 int ctrl_id, ret;
Seungwon Jeon1f44a2a2013-08-31 00:13:31 +09002617 u32 freq[2];
Will Newtonf95f3852011-01-02 01:11:59 -05002618
Thomas Abraham4a909202012-09-17 18:16:35 +00002619 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
Will Newtonf95f3852011-01-02 01:11:59 -05002620 if (!mmc)
2621 return -ENOMEM;
2622
2623 slot = mmc_priv(mmc);
2624 slot->id = id;
Addy Ke76756232014-11-04 22:03:09 +08002625 slot->sdio_id = host->sdio_id0 + id;
Will Newtonf95f3852011-01-02 01:11:59 -05002626 slot->mmc = mmc;
2627 slot->host = host;
Thomas Abrahamc91eab42012-09-17 18:16:40 +00002628 host->slot[id] = slot;
Will Newtonf95f3852011-01-02 01:11:59 -05002629
2630 mmc->ops = &dw_mci_ops;
Seungwon Jeon1f44a2a2013-08-31 00:13:31 +09002631 if (of_property_read_u32_array(host->dev->of_node,
2632 "clock-freq-min-max", freq, 2)) {
2633 mmc->f_min = DW_MCI_FREQ_MIN;
2634 mmc->f_max = DW_MCI_FREQ_MAX;
2635 } else {
Jaehoon Chungb0230302016-11-17 16:40:40 +09002636 dev_info(host->dev,
2637 "'clock-freq-min-max' property was deprecated.\n");
Seungwon Jeon1f44a2a2013-08-31 00:13:31 +09002638 mmc->f_min = freq[0];
2639 mmc->f_max = freq[1];
2640 }
Will Newtonf95f3852011-01-02 01:11:59 -05002641
Yuvaraj CD51da2242014-08-22 19:17:50 +05302642 /*if there are external regulators, get them*/
2643 ret = mmc_regulator_get_supply(mmc);
2644 if (ret == -EPROBE_DEFER)
Doug Anderson3cf890f2014-08-25 11:19:04 -07002645 goto err_host_allocated;
Yuvaraj CD51da2242014-08-22 19:17:50 +05302646
2647 if (!mmc->ocr_avail)
2648 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
Will Newtonf95f3852011-01-02 01:11:59 -05002649
Jaehoon Chungfc3d7722011-02-25 11:08:15 +09002650 if (host->pdata->caps)
2651 mmc->caps = host->pdata->caps;
Jaehoon Chungfc3d7722011-02-25 11:08:15 +09002652
Jaehoon Chung6024e162016-07-15 10:54:50 +09002653 /*
2654 * Support MMC_CAP_ERASE by default.
2655 * It needs to use trim/discard/erase commands.
2656 */
2657 mmc->caps |= MMC_CAP_ERASE;
2658
Abhilash Kesavanab269122012-11-19 10:26:21 +05302659 if (host->pdata->pm_caps)
2660 mmc->pm_caps = host->pdata->pm_caps;
2661
Thomas Abraham800d78b2012-09-17 18:16:42 +00002662 if (host->dev->of_node) {
2663 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2664 if (ctrl_id < 0)
2665 ctrl_id = 0;
2666 } else {
2667 ctrl_id = to_platform_device(host->dev)->id;
2668 }
James Hogancb27a842012-10-16 09:43:08 +01002669 if (drv_data && drv_data->caps)
2670 mmc->caps |= drv_data->caps[ctrl_id];
Thomas Abraham800d78b2012-09-17 18:16:42 +00002671
Seungwon Jeon4f408cc2011-12-09 14:55:52 +09002672 if (host->pdata->caps2)
2673 mmc->caps2 = host->pdata->caps2;
Seungwon Jeon4f408cc2011-12-09 14:55:52 +09002674
Doug Anderson3cf890f2014-08-25 11:19:04 -07002675 ret = mmc_of_parse(mmc);
2676 if (ret)
2677 goto err_host_allocated;
Will Newtonf95f3852011-01-02 01:11:59 -05002678
Jaehoon Chung2b708df2015-08-06 16:23:25 +09002679 /* Useful defaults if platform data is unset. */
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002680 if (host->use_dma == TRANS_MODE_IDMAC) {
Jaehoon Chung2b708df2015-08-06 16:23:25 +09002681 mmc->max_segs = host->ring_size;
Jaehoon Chung225faf82016-05-04 11:24:14 +09002682 mmc->max_blk_size = 65535;
Jaehoon Chung2b708df2015-08-06 16:23:25 +09002683 mmc->max_seg_size = 0x1000;
2684 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2685 mmc->max_blk_count = mmc->max_req_size / 512;
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002686 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2687 mmc->max_segs = 64;
Jaehoon Chung225faf82016-05-04 11:24:14 +09002688 mmc->max_blk_size = 65535;
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002689 mmc->max_blk_count = 65535;
2690 mmc->max_req_size =
2691 mmc->max_blk_size * mmc->max_blk_count;
2692 mmc->max_seg_size = mmc->max_req_size;
Will Newtonf95f3852011-01-02 01:11:59 -05002693 } else {
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002694 /* TRANS_MODE_PIO */
Jaehoon Chung2b708df2015-08-06 16:23:25 +09002695 mmc->max_segs = 64;
Jaehoon Chung225faf82016-05-04 11:24:14 +09002696 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
Jaehoon Chung2b708df2015-08-06 16:23:25 +09002697 mmc->max_blk_count = 512;
2698 mmc->max_req_size = mmc->max_blk_size *
2699 mmc->max_blk_count;
2700 mmc->max_seg_size = mmc->max_req_size;
Jaehoon Chunga39e5742012-02-04 17:00:27 -05002701 }
Will Newtonf95f3852011-01-02 01:11:59 -05002702
Shawn Linc0834a52016-05-27 14:36:40 +08002703 dw_mci_get_cd(mmc);
Jaehoon Chungae0eb342014-03-03 11:36:48 +09002704
Jaehoon Chung0cea5292013-02-15 23:45:45 +09002705 ret = mmc_add_host(mmc);
2706 if (ret)
Doug Anderson3cf890f2014-08-25 11:19:04 -07002707 goto err_host_allocated;
Will Newtonf95f3852011-01-02 01:11:59 -05002708
2709#if defined(CONFIG_DEBUG_FS)
2710 dw_mci_init_debugfs(slot);
2711#endif
2712
Will Newtonf95f3852011-01-02 01:11:59 -05002713 return 0;
Thomas Abraham800d78b2012-09-17 18:16:42 +00002714
Doug Anderson3cf890f2014-08-25 11:19:04 -07002715err_host_allocated:
Thomas Abraham800d78b2012-09-17 18:16:42 +00002716 mmc_free_host(mmc);
Yuvaraj CD51da2242014-08-22 19:17:50 +05302717 return ret;
Will Newtonf95f3852011-01-02 01:11:59 -05002718}
2719
2720static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2721{
Will Newtonf95f3852011-01-02 01:11:59 -05002722 /* Debugfs stuff is cleaned up by mmc core */
2723 mmc_remove_host(slot->mmc);
2724 slot->host->slot[id] = NULL;
2725 mmc_free_host(slot->mmc);
2726}
2727
2728static void dw_mci_init_dma(struct dw_mci *host)
2729{
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +00002730 int addr_config;
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002731 struct device *dev = host->dev;
2732 struct device_node *np = dev->of_node;
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +00002733
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002734 /*
2735 * Check tansfer mode from HCON[17:16]
2736 * Clear the ambiguous description of dw_mmc databook:
2737 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2738 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2739 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2740 * 2b'11: Non DW DMA Interface -> pio only
2741 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2742 * simpler request/acknowledge handshake mechanism and both of them
2743 * are regarded as external dma master for dw_mmc.
2744 */
2745 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2746 if (host->use_dma == DMA_INTERFACE_IDMA) {
2747 host->use_dma = TRANS_MODE_IDMAC;
2748 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2749 host->use_dma == DMA_INTERFACE_GDMA) {
2750 host->use_dma = TRANS_MODE_EDMAC;
Prabu Thangamuthu69d99fd2014-10-20 07:12:33 +00002751 } else {
Will Newtonf95f3852011-01-02 01:11:59 -05002752 goto no_dma;
2753 }
2754
2755 /* Determine which DMA interface to use */
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002756 if (host->use_dma == TRANS_MODE_IDMAC) {
2757 /*
2758 * Check ADDR_CONFIG bit in HCON to find
2759 * IDMAC address bus width
2760 */
Shawn Lin70692752015-09-16 14:41:37 +08002761 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
Will Newtonf95f3852011-01-02 01:11:59 -05002762
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002763 if (addr_config == 1) {
2764 /* host supports IDMAC in 64-bit address mode */
2765 host->dma_64bit_address = 1;
2766 dev_info(host->dev,
2767 "IDMAC supports 64-bit address mode.\n");
2768 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2769 dma_set_coherent_mask(host->dev,
2770 DMA_BIT_MASK(64));
2771 } else {
2772 /* host supports IDMAC in 32-bit address mode */
2773 host->dma_64bit_address = 0;
2774 dev_info(host->dev,
2775 "IDMAC supports 32-bit address mode.\n");
2776 }
2777
2778 /* Alloc memory for sg translation */
Shawn Lincc190d42016-09-02 12:14:39 +08002779 host->sg_cpu = dmam_alloc_coherent(host->dev,
2780 DESC_RING_BUF_SZ,
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002781 &host->sg_dma, GFP_KERNEL);
2782 if (!host->sg_cpu) {
2783 dev_err(host->dev,
2784 "%s: could not alloc DMA memory\n",
2785 __func__);
2786 goto no_dma;
2787 }
2788
2789 host->dma_ops = &dw_mci_idmac_ops;
2790 dev_info(host->dev, "Using internal DMA controller.\n");
2791 } else {
2792 /* TRANS_MODE_EDMAC: check dma bindings again */
2793 if ((of_property_count_strings(np, "dma-names") < 0) ||
2794 (!of_find_property(np, "dmas", NULL))) {
2795 goto no_dma;
2796 }
2797 host->dma_ops = &dw_mci_edmac_ops;
2798 dev_info(host->dev, "Using external DMA controller.\n");
2799 }
Will Newtonf95f3852011-01-02 01:11:59 -05002800
Jaehoon Chunge1631f92012-04-18 15:42:31 +09002801 if (host->dma_ops->init && host->dma_ops->start &&
2802 host->dma_ops->stop && host->dma_ops->cleanup) {
Will Newtonf95f3852011-01-02 01:11:59 -05002803 if (host->dma_ops->init(host)) {
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002804 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2805 __func__);
Will Newtonf95f3852011-01-02 01:11:59 -05002806 goto no_dma;
2807 }
2808 } else {
Thomas Abraham4a909202012-09-17 18:16:35 +00002809 dev_err(host->dev, "DMA initialization not found.\n");
Will Newtonf95f3852011-01-02 01:11:59 -05002810 goto no_dma;
2811 }
2812
Will Newtonf95f3852011-01-02 01:11:59 -05002813 return;
2814
2815no_dma:
Thomas Abraham4a909202012-09-17 18:16:35 +00002816 dev_info(host->dev, "Using PIO mode.\n");
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002817 host->use_dma = TRANS_MODE_PIO;
Will Newtonf95f3852011-01-02 01:11:59 -05002818}
2819
Seungwon Jeon31bff452013-08-31 00:14:23 +09002820static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
Will Newtonf95f3852011-01-02 01:11:59 -05002821{
2822 unsigned long timeout = jiffies + msecs_to_jiffies(500);
Seungwon Jeon31bff452013-08-31 00:14:23 +09002823 u32 ctrl;
Will Newtonf95f3852011-01-02 01:11:59 -05002824
Seungwon Jeon31bff452013-08-31 00:14:23 +09002825 ctrl = mci_readl(host, CTRL);
2826 ctrl |= reset;
2827 mci_writel(host, CTRL, ctrl);
Will Newtonf95f3852011-01-02 01:11:59 -05002828
2829 /* wait till resets clear */
2830 do {
2831 ctrl = mci_readl(host, CTRL);
Seungwon Jeon31bff452013-08-31 00:14:23 +09002832 if (!(ctrl & reset))
Will Newtonf95f3852011-01-02 01:11:59 -05002833 return true;
2834 } while (time_before(jiffies, timeout));
2835
Seungwon Jeon31bff452013-08-31 00:14:23 +09002836 dev_err(host->dev,
2837 "Timeout resetting block (ctrl reset %#x)\n",
2838 ctrl & reset);
Will Newtonf95f3852011-01-02 01:11:59 -05002839
2840 return false;
2841}
2842
Sonny Rao3a33a942014-08-04 18:19:50 -07002843static bool dw_mci_reset(struct dw_mci *host)
Seungwon Jeon31bff452013-08-31 00:14:23 +09002844{
Sonny Rao3a33a942014-08-04 18:19:50 -07002845 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2846 bool ret = false;
2847
Seungwon Jeon31bff452013-08-31 00:14:23 +09002848 /*
2849 * Reseting generates a block interrupt, hence setting
2850 * the scatter-gather pointer to NULL.
2851 */
2852 if (host->sg) {
2853 sg_miter_stop(&host->sg_miter);
2854 host->sg = NULL;
2855 }
2856
Sonny Rao3a33a942014-08-04 18:19:50 -07002857 if (host->use_dma)
2858 flags |= SDMMC_CTRL_DMA_RESET;
Seungwon Jeon31bff452013-08-31 00:14:23 +09002859
Sonny Rao3a33a942014-08-04 18:19:50 -07002860 if (dw_mci_ctrl_reset(host, flags)) {
2861 /*
2862 * In all cases we clear the RAWINTS register to clear any
2863 * interrupts.
2864 */
2865 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2866
2867 /* if using dma we wait for dma_req to clear */
2868 if (host->use_dma) {
2869 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2870 u32 status;
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002871
Sonny Rao3a33a942014-08-04 18:19:50 -07002872 do {
2873 status = mci_readl(host, STATUS);
2874 if (!(status & SDMMC_STATUS_DMA_REQ))
2875 break;
2876 cpu_relax();
2877 } while (time_before(jiffies, timeout));
2878
2879 if (status & SDMMC_STATUS_DMA_REQ) {
2880 dev_err(host->dev,
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002881 "%s: Timeout waiting for dma_req to clear during reset\n",
2882 __func__);
Sonny Rao3a33a942014-08-04 18:19:50 -07002883 goto ciu_out;
2884 }
2885
2886 /* when using DMA next we reset the fifo again */
2887 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2888 goto ciu_out;
2889 }
2890 } else {
2891 /* if the controller reset bit did clear, then set clock regs */
2892 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002893 dev_err(host->dev,
2894 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
Sonny Rao3a33a942014-08-04 18:19:50 -07002895 __func__);
2896 goto ciu_out;
2897 }
2898 }
2899
Shawn Lin3fc7eae2015-09-16 14:41:23 +08002900 if (host->use_dma == TRANS_MODE_IDMAC)
2901 /* It is also recommended that we reset and reprogram idmac */
2902 dw_mci_idmac_reset(host);
Sonny Rao3a33a942014-08-04 18:19:50 -07002903
2904 ret = true;
2905
2906ciu_out:
2907 /* After a CTRL reset we need to have CIU set clock registers */
2908 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2909
2910 return ret;
Seungwon Jeon31bff452013-08-31 00:14:23 +09002911}
2912
Doug Anderson5c935162015-03-09 16:18:21 -07002913static void dw_mci_cmd11_timer(unsigned long arg)
2914{
2915 struct dw_mci *host = (struct dw_mci *)arg;
2916
Doug Andersonfd674192015-04-03 11:13:06 -07002917 if (host->state != STATE_SENDING_CMD11) {
2918 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2919 return;
2920 }
Doug Anderson5c935162015-03-09 16:18:21 -07002921
2922 host->cmd_status = SDMMC_INT_RTO;
2923 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2924 tasklet_schedule(&host->tasklet);
2925}
2926
Addy Ke57e10482015-08-11 01:27:18 +09002927static void dw_mci_dto_timer(unsigned long arg)
2928{
2929 struct dw_mci *host = (struct dw_mci *)arg;
2930
2931 switch (host->state) {
2932 case STATE_SENDING_DATA:
2933 case STATE_DATA_BUSY:
2934 /*
2935 * If DTO interrupt does NOT come in sending data state,
2936 * we should notify the driver to terminate current transfer
2937 * and report a data timeout to the core.
2938 */
2939 host->data_status = SDMMC_INT_DRTO;
2940 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2941 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2942 tasklet_schedule(&host->tasklet);
2943 break;
2944 default:
2945 break;
2946 }
2947}
2948
Thomas Abrahamc91eab42012-09-17 18:16:40 +00002949#ifdef CONFIG_OF
Thomas Abrahamc91eab42012-09-17 18:16:40 +00002950static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2951{
2952 struct dw_mci_board *pdata;
2953 struct device *dev = host->dev;
2954 struct device_node *np = dev->of_node;
Arnd Bergmanne95baf12012-11-08 14:26:11 +00002955 const struct dw_mci_drv_data *drv_data = host->drv_data;
Shawn Line8cc37b2016-01-21 14:52:52 +08002956 int ret;
Doug Anderson3c6d89e2013-06-07 10:28:30 -07002957 u32 clock_frequency;
Thomas Abrahamc91eab42012-09-17 18:16:40 +00002958
2959 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
Beomho Seobf3707e2014-12-23 21:07:33 +09002960 if (!pdata)
Thomas Abrahamc91eab42012-09-17 18:16:40 +00002961 return ERR_PTR(-ENOMEM);
Thomas Abrahamc91eab42012-09-17 18:16:40 +00002962
Guodong Xud6786fe2016-08-12 16:51:26 +08002963 /* find reset controller when exist */
Jaehoon Chung3a667e32016-10-31 11:49:42 +09002964 pdata->rstc = devm_reset_control_get_optional(dev, "reset");
Guodong Xud6786fe2016-08-12 16:51:26 +08002965 if (IS_ERR(pdata->rstc)) {
2966 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
2967 return ERR_PTR(-EPROBE_DEFER);
2968 }
2969
Thomas Abrahamc91eab42012-09-17 18:16:40 +00002970 /* find out number of slots supported */
Shawn Lin8a629d22016-02-02 14:11:25 +08002971 of_property_read_u32(np, "num-slots", &pdata->num_slots);
Thomas Abrahamc91eab42012-09-17 18:16:40 +00002972
Thomas Abrahamc91eab42012-09-17 18:16:40 +00002973 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
Shawn Lin0e3a22c2015-08-03 15:07:21 +08002974 dev_info(dev,
2975 "fifo-depth property not found, using value of FIFOTH register as default\n");
Thomas Abrahamc91eab42012-09-17 18:16:40 +00002976
2977 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2978
Doug Anderson3c6d89e2013-06-07 10:28:30 -07002979 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2980 pdata->bus_hz = clock_frequency;
2981
James Hogancb27a842012-10-16 09:43:08 +01002982 if (drv_data && drv_data->parse_dt) {
2983 ret = drv_data->parse_dt(host);
Thomas Abraham800d78b2012-09-17 18:16:42 +00002984 if (ret)
2985 return ERR_PTR(ret);
2986 }
2987
Thomas Abrahamc91eab42012-09-17 18:16:40 +00002988 return pdata;
2989}
2990
2991#else /* CONFIG_OF */
2992static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2993{
2994 return ERR_PTR(-EINVAL);
2995}
2996#endif /* CONFIG_OF */
2997
Doug Andersonfa0c3282015-02-25 10:11:51 -08002998static void dw_mci_enable_cd(struct dw_mci *host)
2999{
Doug Andersonfa0c3282015-02-25 10:11:51 -08003000 unsigned long irqflags;
3001 u32 temp;
3002 int i;
Shawn Line8cc37b2016-01-21 14:52:52 +08003003 struct dw_mci_slot *slot;
Doug Andersonfa0c3282015-02-25 10:11:51 -08003004
Shawn Line8cc37b2016-01-21 14:52:52 +08003005 /*
3006 * No need for CD if all slots have a non-error GPIO
3007 * as well as broken card detection is found.
3008 */
Doug Andersonfa0c3282015-02-25 10:11:51 -08003009 for (i = 0; i < host->num_slots; i++) {
Shawn Line8cc37b2016-01-21 14:52:52 +08003010 slot = host->slot[i];
3011 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3012 return;
Doug Andersonfa0c3282015-02-25 10:11:51 -08003013
Arnd Bergmann287980e2016-05-27 23:23:25 +02003014 if (mmc_gpio_get_cd(slot->mmc) < 0)
Doug Andersonfa0c3282015-02-25 10:11:51 -08003015 break;
3016 }
3017 if (i == host->num_slots)
3018 return;
3019
3020 spin_lock_irqsave(&host->irq_lock, irqflags);
3021 temp = mci_readl(host, INTMASK);
3022 temp |= SDMMC_INT_CD;
3023 mci_writel(host, INTMASK, temp);
3024 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3025}
3026
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +05303027int dw_mci_probe(struct dw_mci *host)
Will Newtonf95f3852011-01-02 01:11:59 -05003028{
Arnd Bergmanne95baf12012-11-08 14:26:11 +00003029 const struct dw_mci_drv_data *drv_data = host->drv_data;
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +05303030 int width, i, ret = 0;
Will Newtonf95f3852011-01-02 01:11:59 -05003031 u32 fifo_size;
Thomas Abraham1c2215b2012-09-17 18:16:37 +00003032 int init_slots = 0;
Will Newtonf95f3852011-01-02 01:11:59 -05003033
Thomas Abrahamc91eab42012-09-17 18:16:40 +00003034 if (!host->pdata) {
3035 host->pdata = dw_mci_parse_dt(host);
Guodong Xud6786fe2016-08-12 16:51:26 +08003036 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3037 return -EPROBE_DEFER;
3038 } else if (IS_ERR(host->pdata)) {
Thomas Abrahamc91eab42012-09-17 18:16:40 +00003039 dev_err(host->dev, "platform data not available\n");
3040 return -EINVAL;
3041 }
Will Newtonf95f3852011-01-02 01:11:59 -05003042 }
3043
Seungwon Jeon780f22a2012-11-28 19:26:03 +09003044 host->biu_clk = devm_clk_get(host->dev, "biu");
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003045 if (IS_ERR(host->biu_clk)) {
3046 dev_dbg(host->dev, "biu clock not available\n");
3047 } else {
3048 ret = clk_prepare_enable(host->biu_clk);
3049 if (ret) {
3050 dev_err(host->dev, "failed to enable biu clock\n");
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003051 return ret;
3052 }
Will Newtonf95f3852011-01-02 01:11:59 -05003053 }
3054
Seungwon Jeon780f22a2012-11-28 19:26:03 +09003055 host->ciu_clk = devm_clk_get(host->dev, "ciu");
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003056 if (IS_ERR(host->ciu_clk)) {
3057 dev_dbg(host->dev, "ciu clock not available\n");
Doug Anderson3c6d89e2013-06-07 10:28:30 -07003058 host->bus_hz = host->pdata->bus_hz;
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003059 } else {
3060 ret = clk_prepare_enable(host->ciu_clk);
3061 if (ret) {
3062 dev_err(host->dev, "failed to enable ciu clock\n");
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003063 goto err_clk_biu;
3064 }
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003065
Doug Anderson3c6d89e2013-06-07 10:28:30 -07003066 if (host->pdata->bus_hz) {
3067 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3068 if (ret)
3069 dev_warn(host->dev,
Jaehoon Chung612de4c2014-03-03 11:36:42 +09003070 "Unable to set bus rate to %uHz\n",
Doug Anderson3c6d89e2013-06-07 10:28:30 -07003071 host->pdata->bus_hz);
3072 }
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003073 host->bus_hz = clk_get_rate(host->ciu_clk);
Doug Anderson3c6d89e2013-06-07 10:28:30 -07003074 }
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003075
Jaehoon Chung612de4c2014-03-03 11:36:42 +09003076 if (!host->bus_hz) {
3077 dev_err(host->dev,
3078 "Platform data must supply bus speed\n");
3079 ret = -ENODEV;
3080 goto err_clk_ciu;
3081 }
3082
Yuvaraj Kumar C D002f0d52013-08-31 00:12:19 +09003083 if (drv_data && drv_data->init) {
3084 ret = drv_data->init(host);
3085 if (ret) {
3086 dev_err(host->dev,
3087 "implementation specific init failed\n");
3088 goto err_clk_ciu;
3089 }
3090 }
3091
Guodong Xud6786fe2016-08-12 16:51:26 +08003092 if (!IS_ERR(host->pdata->rstc)) {
3093 reset_control_assert(host->pdata->rstc);
3094 usleep_range(10, 50);
3095 reset_control_deassert(host->pdata->rstc);
3096 }
3097
Doug Anderson5c935162015-03-09 16:18:21 -07003098 setup_timer(&host->cmd11_timer,
3099 dw_mci_cmd11_timer, (unsigned long)host);
3100
Jaehoon Chung16a34572016-06-21 14:35:37 +09003101 setup_timer(&host->dto_timer,
3102 dw_mci_dto_timer, (unsigned long)host);
Addy Ke57e10482015-08-11 01:27:18 +09003103
Will Newtonf95f3852011-01-02 01:11:59 -05003104 spin_lock_init(&host->lock);
Doug Andersonf8c58c12014-12-02 15:42:47 -08003105 spin_lock_init(&host->irq_lock);
Will Newtonf95f3852011-01-02 01:11:59 -05003106 INIT_LIST_HEAD(&host->queue);
3107
Will Newtonf95f3852011-01-02 01:11:59 -05003108 /*
3109 * Get the host data width - this assumes that HCON has been set with
3110 * the correct values.
3111 */
Shawn Lin70692752015-09-16 14:41:37 +08003112 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
Will Newtonf95f3852011-01-02 01:11:59 -05003113 if (!i) {
3114 host->push_data = dw_mci_push_data16;
3115 host->pull_data = dw_mci_pull_data16;
3116 width = 16;
3117 host->data_shift = 1;
3118 } else if (i == 2) {
3119 host->push_data = dw_mci_push_data64;
3120 host->pull_data = dw_mci_pull_data64;
3121 width = 64;
3122 host->data_shift = 3;
3123 } else {
3124 /* Check for a reserved value, and warn if it is */
3125 WARN((i != 1),
3126 "HCON reports a reserved host data width!\n"
3127 "Defaulting to 32-bit access.\n");
3128 host->push_data = dw_mci_push_data32;
3129 host->pull_data = dw_mci_pull_data32;
3130 width = 32;
3131 host->data_shift = 2;
3132 }
3133
3134 /* Reset all blocks */
Shawn Lin37444152016-01-22 15:43:12 +08003135 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3136 ret = -ENODEV;
3137 goto err_clk_ciu;
3138 }
Seungwon Jeon141a7122012-05-22 13:01:03 +09003139
3140 host->dma_ops = host->pdata->dma_ops;
3141 dw_mci_init_dma(host);
Will Newtonf95f3852011-01-02 01:11:59 -05003142
3143 /* Clear the interrupts for the host controller */
3144 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3145 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3146
3147 /* Put in max timeout */
3148 mci_writel(host, TMOUT, 0xFFFFFFFF);
3149
3150 /*
3151 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3152 * Tx Mark = fifo_size / 2 DMA Size = 8
3153 */
James Hoganb86d8252011-06-24 13:57:18 +01003154 if (!host->pdata->fifo_depth) {
3155 /*
3156 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3157 * have been overwritten by the bootloader, just like we're
3158 * about to do, so if you know the value for your hardware, you
3159 * should put it in the platform data.
3160 */
3161 fifo_size = mci_readl(host, FIFOTH);
Jaehoon Chung8234e862012-01-11 09:28:21 +00003162 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
James Hoganb86d8252011-06-24 13:57:18 +01003163 } else {
3164 fifo_size = host->pdata->fifo_depth;
3165 }
3166 host->fifo_depth = fifo_size;
Seungwon Jeon52426892013-08-31 00:13:42 +09003167 host->fifoth_val =
3168 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
Jaehoon Chunge61cf112011-03-17 20:32:33 +09003169 mci_writel(host, FIFOTH, host->fifoth_val);
Will Newtonf95f3852011-01-02 01:11:59 -05003170
3171 /* disable clock to CIU */
3172 mci_writel(host, CLKENA, 0);
3173 mci_writel(host, CLKSRC, 0);
3174
James Hogan63008762013-03-12 10:43:54 +00003175 /*
3176 * In 2.40a spec, Data offset is changed.
3177 * Need to check the version-id and set data-offset for DATA register.
3178 */
3179 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3180 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3181
3182 if (host->verid < DW_MMC_240A)
Ben Dooks76184ac2015-03-25 11:27:52 +00003183 host->fifo_reg = host->regs + DATA_OFFSET;
James Hogan63008762013-03-12 10:43:54 +00003184 else
Ben Dooks76184ac2015-03-25 11:27:52 +00003185 host->fifo_reg = host->regs + DATA_240A_OFFSET;
James Hogan63008762013-03-12 10:43:54 +00003186
Will Newtonf95f3852011-01-02 01:11:59 -05003187 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
Seungwon Jeon780f22a2012-11-28 19:26:03 +09003188 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3189 host->irq_flags, "dw-mci", host);
Will Newtonf95f3852011-01-02 01:11:59 -05003190 if (ret)
Doug Anderson6130e7a2014-10-14 09:33:09 -07003191 goto err_dmaunmap;
Will Newtonf95f3852011-01-02 01:11:59 -05003192
Will Newtonf95f3852011-01-02 01:11:59 -05003193 if (host->pdata->num_slots)
3194 host->num_slots = host->pdata->num_slots;
3195 else
Shawn Lin8a629d22016-02-02 14:11:25 +08003196 host->num_slots = 1;
3197
3198 if (host->num_slots < 1 ||
3199 host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) {
3200 dev_err(host->dev,
3201 "Platform data must supply correct num_slots.\n");
3202 ret = -ENODEV;
3203 goto err_clk_ciu;
3204 }
Will Newtonf95f3852011-01-02 01:11:59 -05003205
Yuvaraj CD2da1d7f2012-10-08 14:29:51 +05303206 /*
Doug Andersonfa0c3282015-02-25 10:11:51 -08003207 * Enable interrupts for command done, data over, data empty,
Yuvaraj CD2da1d7f2012-10-08 14:29:51 +05303208 * receive ready and error such as transmit, receive timeout, crc error
3209 */
Yuvaraj CD2da1d7f2012-10-08 14:29:51 +05303210 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3211 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
Doug Andersonfa0c3282015-02-25 10:11:51 -08003212 DW_MCI_ERROR_FLAGS);
Shawn Lin0e3a22c2015-08-03 15:07:21 +08003213 /* Enable mci interrupt */
3214 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
Yuvaraj CD2da1d7f2012-10-08 14:29:51 +05303215
Shawn Lin0e3a22c2015-08-03 15:07:21 +08003216 dev_info(host->dev,
3217 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
Yuvaraj CD2da1d7f2012-10-08 14:29:51 +05303218 host->irq, width, fifo_size);
3219
Will Newtonf95f3852011-01-02 01:11:59 -05003220 /* We need at least one slot to succeed */
3221 for (i = 0; i < host->num_slots; i++) {
3222 ret = dw_mci_init_slot(host, i);
Thomas Abraham1c2215b2012-09-17 18:16:37 +00003223 if (ret)
3224 dev_dbg(host->dev, "slot %d init failed\n", i);
3225 else
3226 init_slots++;
3227 }
3228
3229 if (init_slots) {
3230 dev_info(host->dev, "%d slots initialized\n", init_slots);
3231 } else {
Shawn Lin0e3a22c2015-08-03 15:07:21 +08003232 dev_dbg(host->dev,
3233 "attempted to initialize %d slots, but failed on all\n",
3234 host->num_slots);
Doug Anderson6130e7a2014-10-14 09:33:09 -07003235 goto err_dmaunmap;
Will Newtonf95f3852011-01-02 01:11:59 -05003236 }
3237
Doug Andersonb793f652015-03-11 15:15:14 -07003238 /* Now that slots are all setup, we can enable card detect */
3239 dw_mci_enable_cd(host);
3240
Will Newtonf95f3852011-01-02 01:11:59 -05003241 return 0;
3242
Will Newtonf95f3852011-01-02 01:11:59 -05003243err_dmaunmap:
3244 if (host->use_dma && host->dma_ops->exit)
3245 host->dma_ops->exit(host);
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003246
Guodong Xud6786fe2016-08-12 16:51:26 +08003247 if (!IS_ERR(host->pdata->rstc))
3248 reset_control_assert(host->pdata->rstc);
3249
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003250err_clk_ciu:
Jaehoon Chung7037f3b2016-07-15 10:54:08 +09003251 clk_disable_unprepare(host->ciu_clk);
Seungwon Jeon780f22a2012-11-28 19:26:03 +09003252
Thomas Abrahamf90a0612012-09-17 18:16:38 +00003253err_clk_biu:
Jaehoon Chung7037f3b2016-07-15 10:54:08 +09003254 clk_disable_unprepare(host->biu_clk);
Seungwon Jeon780f22a2012-11-28 19:26:03 +09003255
Will Newtonf95f3852011-01-02 01:11:59 -05003256 return ret;
3257}
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +05303258EXPORT_SYMBOL(dw_mci_probe);
Will Newtonf95f3852011-01-02 01:11:59 -05003259
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +05303260void dw_mci_remove(struct dw_mci *host)
Will Newtonf95f3852011-01-02 01:11:59 -05003261{
Will Newtonf95f3852011-01-02 01:11:59 -05003262 int i;
3263
Will Newtonf95f3852011-01-02 01:11:59 -05003264 for (i = 0; i < host->num_slots; i++) {
Thomas Abraham4a909202012-09-17 18:16:35 +00003265 dev_dbg(host->dev, "remove slot %d\n", i);
Will Newtonf95f3852011-01-02 01:11:59 -05003266 if (host->slot[i])
3267 dw_mci_cleanup_slot(host->slot[i], i);
3268 }
3269
Prabu Thangamuthu048fd7e2015-05-28 12:21:06 +00003270 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3271 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3272
Will Newtonf95f3852011-01-02 01:11:59 -05003273 /* disable clock to CIU */
3274 mci_writel(host, CLKENA, 0);
3275 mci_writel(host, CLKSRC, 0);
3276
Will Newtonf95f3852011-01-02 01:11:59 -05003277 if (host->use_dma && host->dma_ops->exit)
3278 host->dma_ops->exit(host);
3279
Guodong Xud6786fe2016-08-12 16:51:26 +08003280 if (!IS_ERR(host->pdata->rstc))
3281 reset_control_assert(host->pdata->rstc);
3282
Jaehoon Chung7037f3b2016-07-15 10:54:08 +09003283 clk_disable_unprepare(host->ciu_clk);
3284 clk_disable_unprepare(host->biu_clk);
Will Newtonf95f3852011-01-02 01:11:59 -05003285}
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +05303286EXPORT_SYMBOL(dw_mci_remove);
3287
3288
Will Newtonf95f3852011-01-02 01:11:59 -05003289
Shawn Line9ed8832016-10-12 10:50:35 +08003290#ifdef CONFIG_PM
Shawn Lined24e1f2016-10-12 10:56:55 +08003291int dw_mci_runtime_suspend(struct device *dev)
Will Newtonf95f3852011-01-02 01:11:59 -05003292{
Shawn Lined24e1f2016-10-12 10:56:55 +08003293 struct dw_mci *host = dev_get_drvdata(dev);
3294
Shawn Lin3fc7eae2015-09-16 14:41:23 +08003295 if (host->use_dma && host->dma_ops->exit)
3296 host->dma_ops->exit(host);
3297
Shawn Lined24e1f2016-10-12 10:56:55 +08003298 clk_disable_unprepare(host->ciu_clk);
3299
3300 if (host->cur_slot &&
3301 (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3302 !mmc_card_is_removable(host->cur_slot->mmc)))
3303 clk_disable_unprepare(host->biu_clk);
3304
Will Newtonf95f3852011-01-02 01:11:59 -05003305 return 0;
3306}
Shawn Lined24e1f2016-10-12 10:56:55 +08003307EXPORT_SYMBOL(dw_mci_runtime_suspend);
Will Newtonf95f3852011-01-02 01:11:59 -05003308
Shawn Lined24e1f2016-10-12 10:56:55 +08003309int dw_mci_runtime_resume(struct device *dev)
Will Newtonf95f3852011-01-02 01:11:59 -05003310{
Shawn Lined24e1f2016-10-12 10:56:55 +08003311 int i, ret = 0;
3312 struct dw_mci *host = dev_get_drvdata(dev);
Will Newtonf95f3852011-01-02 01:11:59 -05003313
Shawn Lined24e1f2016-10-12 10:56:55 +08003314 if (host->cur_slot &&
3315 (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3316 !mmc_card_is_removable(host->cur_slot->mmc))) {
3317 ret = clk_prepare_enable(host->biu_clk);
3318 if (ret)
3319 return ret;
Jaehoon Chunge61cf112011-03-17 20:32:33 +09003320 }
3321
Shawn Lined24e1f2016-10-12 10:56:55 +08003322 ret = clk_prepare_enable(host->ciu_clk);
3323 if (ret)
Joonyoung Shimdf9bcc22016-11-25 12:47:15 +09003324 goto err;
3325
3326 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3327 clk_disable_unprepare(host->ciu_clk);
3328 ret = -ENODEV;
3329 goto err;
3330 }
Shawn Lined24e1f2016-10-12 10:56:55 +08003331
Jonathan Kliegman3bfe6192012-06-14 13:31:55 -04003332 if (host->use_dma && host->dma_ops->init)
Seungwon Jeon141a7122012-05-22 13:01:03 +09003333 host->dma_ops->init(host);
3334
Seungwon Jeon52426892013-08-31 00:13:42 +09003335 /*
3336 * Restore the initial value at FIFOTH register
3337 * And Invalidate the prev_blksz with zero
3338 */
Shawn Lined24e1f2016-10-12 10:56:55 +08003339 mci_writel(host, FIFOTH, host->fifoth_val);
3340 host->prev_blksz = 0;
Jaehoon Chunge61cf112011-03-17 20:32:33 +09003341
Doug Anderson2eb29442013-08-31 00:11:49 +09003342 /* Put in max timeout */
3343 mci_writel(host, TMOUT, 0xFFFFFFFF);
3344
Jaehoon Chunge61cf112011-03-17 20:32:33 +09003345 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3346 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3347 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
Doug Andersonfa0c3282015-02-25 10:11:51 -08003348 DW_MCI_ERROR_FLAGS);
Jaehoon Chunge61cf112011-03-17 20:32:33 +09003349 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3350
Will Newtonf95f3852011-01-02 01:11:59 -05003351 for (i = 0; i < host->num_slots; i++) {
3352 struct dw_mci_slot *slot = host->slot[i];
Shawn Lin0e3a22c2015-08-03 15:07:21 +08003353
Will Newtonf95f3852011-01-02 01:11:59 -05003354 if (!slot)
3355 continue;
Ziyuan Xue9748e02017-01-17 09:22:56 +08003356 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
Abhilash Kesavanab269122012-11-19 10:26:21 +05303357 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
Ziyuan Xue9748e02017-01-17 09:22:56 +08003358
3359 /* Force setup bus to guarantee available clock output */
3360 dw_mci_setup_bus(slot, true);
Will Newtonf95f3852011-01-02 01:11:59 -05003361 }
Doug Andersonfa0c3282015-02-25 10:11:51 -08003362
3363 /* Now that slots are all setup, we can enable card detect */
3364 dw_mci_enable_cd(host);
3365
Joonyoung Shimdf9bcc22016-11-25 12:47:15 +09003366 return 0;
3367
3368err:
3369 if (host->cur_slot &&
3370 (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3371 !mmc_card_is_removable(host->cur_slot->mmc)))
3372 clk_disable_unprepare(host->biu_clk);
3373
Shawn Lined24e1f2016-10-12 10:56:55 +08003374 return ret;
Shawn Line9ed8832016-10-12 10:50:35 +08003375}
3376EXPORT_SYMBOL(dw_mci_runtime_resume);
3377#endif /* CONFIG_PM */
Jaehoon Chung6fe88902011-12-08 19:23:03 +09003378
Will Newtonf95f3852011-01-02 01:11:59 -05003379static int __init dw_mci_init(void)
3380{
Sachin Kamat8e1c4e42013-04-04 11:25:11 +05303381 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
Shashidhar Hiremath62ca8032012-01-13 16:04:57 +05303382 return 0;
Will Newtonf95f3852011-01-02 01:11:59 -05003383}
3384
3385static void __exit dw_mci_exit(void)
3386{
Will Newtonf95f3852011-01-02 01:11:59 -05003387}
3388
3389module_init(dw_mci_init);
3390module_exit(dw_mci_exit);
3391
3392MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3393MODULE_AUTHOR("NXP Semiconductor VietNam");
3394MODULE_AUTHOR("Imagination Technologies Ltd");
3395MODULE_LICENSE("GPL v2");