Thomas Gleixner | c942fdd | 2019-05-27 08:55:06 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 2 | /* |
| 3 | * Driver for Mediatek IR Receiver Controller |
| 4 | * |
| 5 | * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <linux/clk.h> |
| 9 | #include <linux/interrupt.h> |
| 10 | #include <linux/module.h> |
| 11 | #include <linux/of_platform.h> |
| 12 | #include <linux/reset.h> |
| 13 | #include <media/rc-core.h> |
| 14 | |
| 15 | #define MTK_IR_DEV KBUILD_MODNAME |
| 16 | |
| 17 | /* Register to enable PWM and IR */ |
| 18 | #define MTK_CONFIG_HIGH_REG 0x0c |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 19 | |
| 20 | /* Bit to enable IR pulse width detection */ |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 21 | #define MTK_PWM_EN BIT(13) |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 22 | |
| 23 | /* |
| 24 | * Register to setting ok count whose unit based on hardware sampling period |
| 25 | * indicating IR receiving completion and then making IRQ fires |
| 26 | */ |
| 27 | #define MTK_OK_COUNT(x) (((x) & GENMASK(23, 16)) << 16) |
| 28 | |
| 29 | /* Bit to enable IR hardware function */ |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 30 | #define MTK_IR_EN BIT(0) |
| 31 | |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 32 | /* Bit to restart IR receiving */ |
| 33 | #define MTK_IRCLR BIT(0) |
| 34 | |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 35 | /* Fields containing pulse width data */ |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 36 | #define MTK_WIDTH_MASK (GENMASK(7, 0)) |
| 37 | |
Sean Young | 5dd4b89 | 2019-07-12 18:47:00 -0400 | [diff] [blame] | 38 | /* IR threshold */ |
| 39 | #define MTK_IRTHD 0x14 |
| 40 | #define MTK_DG_CNT_MASK (GENMASK(12, 8)) |
| 41 | #define MTK_DG_CNT(x) ((x) << 8) |
| 42 | |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 43 | /* Bit to enable interrupt */ |
| 44 | #define MTK_IRINT_EN BIT(0) |
| 45 | |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 46 | /* Bit to clear interrupt status */ |
| 47 | #define MTK_IRINT_CLR BIT(0) |
| 48 | |
| 49 | /* Maximum count of samples */ |
| 50 | #define MTK_MAX_SAMPLES 0xff |
| 51 | /* Indicate the end of IR message */ |
| 52 | #define MTK_IR_END(v, p) ((v) == MTK_MAX_SAMPLES && (p) == 0) |
| 53 | /* Number of registers to record the pulse width */ |
| 54 | #define MTK_CHKDATA_SZ 17 |
Sean Young | 528222d8 | 2020-08-23 19:23:05 +0200 | [diff] [blame] | 55 | /* Sample period in us */ |
| 56 | #define MTK_IR_SAMPLE 46 |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 57 | |
| 58 | enum mtk_fields { |
| 59 | /* Register to setting software sampling period */ |
| 60 | MTK_CHK_PERIOD, |
| 61 | /* Register to setting hardware sampling period */ |
| 62 | MTK_HW_PERIOD, |
| 63 | }; |
| 64 | |
| 65 | enum mtk_regs { |
| 66 | /* Register to clear state of state machine */ |
| 67 | MTK_IRCLR_REG, |
| 68 | /* Register containing pulse width data */ |
| 69 | MTK_CHKDATA_REG, |
| 70 | /* Register to enable IR interrupt */ |
| 71 | MTK_IRINT_EN_REG, |
| 72 | /* Register to ack IR interrupt */ |
| 73 | MTK_IRINT_CLR_REG |
| 74 | }; |
| 75 | |
| 76 | static const u32 mt7623_regs[] = { |
| 77 | [MTK_IRCLR_REG] = 0x20, |
| 78 | [MTK_CHKDATA_REG] = 0x88, |
| 79 | [MTK_IRINT_EN_REG] = 0xcc, |
| 80 | [MTK_IRINT_CLR_REG] = 0xd0, |
| 81 | }; |
| 82 | |
Sean Wang | 5838998 | 2017-06-30 02:03:06 -0400 | [diff] [blame] | 83 | static const u32 mt7622_regs[] = { |
| 84 | [MTK_IRCLR_REG] = 0x18, |
| 85 | [MTK_CHKDATA_REG] = 0x30, |
| 86 | [MTK_IRINT_EN_REG] = 0x1c, |
| 87 | [MTK_IRINT_CLR_REG] = 0x20, |
| 88 | }; |
| 89 | |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 90 | struct mtk_field_type { |
| 91 | u32 reg; |
| 92 | u8 offset; |
| 93 | u32 mask; |
| 94 | }; |
| 95 | |
| 96 | /* |
| 97 | * struct mtk_ir_data - This is the structure holding all differences among |
| 98 | various hardwares |
| 99 | * @regs: The pointer to the array holding registers offset |
| 100 | * @fields: The pointer to the array holding fields location |
| 101 | * @div: The internal divisor for the based reference clock |
| 102 | * @ok_count: The count indicating the completion of IR data |
| 103 | * receiving when count is reached |
| 104 | * @hw_period: The value indicating the hardware sampling period |
| 105 | */ |
| 106 | struct mtk_ir_data { |
| 107 | const u32 *regs; |
| 108 | const struct mtk_field_type *fields; |
| 109 | u8 div; |
| 110 | u8 ok_count; |
| 111 | u32 hw_period; |
| 112 | }; |
| 113 | |
| 114 | static const struct mtk_field_type mt7623_fields[] = { |
| 115 | [MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)}, |
| 116 | [MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)}, |
| 117 | }; |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 118 | |
Sean Wang | 5838998 | 2017-06-30 02:03:06 -0400 | [diff] [blame] | 119 | static const struct mtk_field_type mt7622_fields[] = { |
| 120 | [MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)}, |
| 121 | [MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)}, |
| 122 | }; |
| 123 | |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 124 | /* |
| 125 | * struct mtk_ir - This is the main datasructure for holding the state |
| 126 | * of the driver |
| 127 | * @dev: The device pointer |
| 128 | * @rc: The rc instrance |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 129 | * @base: The mapped register i/o base |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 130 | * @irq: The IRQ that we are using |
| 131 | * @clk: The clock that IR internal is using |
| 132 | * @bus: The clock that software decoder is using |
| 133 | * @data: Holding specific data for vaious platform |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 134 | */ |
| 135 | struct mtk_ir { |
| 136 | struct device *dev; |
| 137 | struct rc_dev *rc; |
| 138 | void __iomem *base; |
| 139 | int irq; |
| 140 | struct clk *clk; |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 141 | struct clk *bus; |
| 142 | const struct mtk_ir_data *data; |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 143 | }; |
| 144 | |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 145 | static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i) |
| 146 | { |
| 147 | return ir->data->regs[MTK_CHKDATA_REG] + 4 * i; |
| 148 | } |
| 149 | |
| 150 | static inline u32 mtk_chk_period(struct mtk_ir *ir) |
| 151 | { |
| 152 | u32 val; |
| 153 | |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 154 | /* |
| 155 | * Period for software decoder used in the |
| 156 | * unit of raw software sampling |
| 157 | */ |
Sean Young | d904eb0 | 2020-11-29 18:01:26 +0100 | [diff] [blame] | 158 | val = DIV_ROUND_CLOSEST(clk_get_rate(ir->bus), |
| 159 | USEC_PER_SEC * ir->data->div / MTK_IR_SAMPLE); |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 160 | |
| 161 | dev_dbg(ir->dev, "@pwm clk = \t%lu\n", |
| 162 | clk_get_rate(ir->bus) / ir->data->div); |
| 163 | dev_dbg(ir->dev, "@chkperiod = %08x\n", val); |
| 164 | |
| 165 | return val; |
| 166 | } |
| 167 | |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 168 | static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg) |
| 169 | { |
| 170 | u32 tmp; |
| 171 | |
| 172 | tmp = __raw_readl(ir->base + reg); |
| 173 | tmp = (tmp & ~mask) | val; |
| 174 | __raw_writel(tmp, ir->base + reg); |
| 175 | } |
| 176 | |
| 177 | static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg) |
| 178 | { |
| 179 | __raw_writel(val, ir->base + reg); |
| 180 | } |
| 181 | |
| 182 | static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg) |
| 183 | { |
| 184 | return __raw_readl(ir->base + reg); |
| 185 | } |
| 186 | |
| 187 | static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask) |
| 188 | { |
| 189 | u32 val; |
| 190 | |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 191 | val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]); |
| 192 | mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]); |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 193 | } |
| 194 | |
| 195 | static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask) |
| 196 | { |
| 197 | u32 val; |
| 198 | |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 199 | val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]); |
| 200 | mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]); |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 201 | } |
| 202 | |
| 203 | static irqreturn_t mtk_ir_irq(int irqno, void *dev_id) |
| 204 | { |
| 205 | struct mtk_ir *ir = dev_id; |
| 206 | u8 wid = 0; |
| 207 | u32 i, j, val; |
Sean Young | 183e19f | 2018-08-21 15:57:52 -0400 | [diff] [blame] | 208 | struct ir_raw_event rawir = {}; |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 209 | |
| 210 | /* |
| 211 | * Reset decoder state machine explicitly is required |
| 212 | * because 1) the longest duration for space MTK IR hardware |
| 213 | * could record is not safely long. e.g 12ms if rx resolution |
| 214 | * is 46us by default. There is still the risk to satisfying |
| 215 | * every decoder to reset themselves through long enough |
| 216 | * trailing spaces and 2) the IRQ handler guarantees that |
| 217 | * start of IR message is always contained in and starting |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 218 | * from register mtk_chkdata_reg(ir, i). |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 219 | */ |
| 220 | ir_raw_event_reset(ir->rc); |
| 221 | |
| 222 | /* First message must be pulse */ |
| 223 | rawir.pulse = false; |
| 224 | |
| 225 | /* Handle all pulse and space IR controller captures */ |
| 226 | for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) { |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 227 | val = mtk_r32(ir, mtk_chkdata_reg(ir, i)); |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 228 | dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val); |
| 229 | |
| 230 | for (j = 0 ; j < 4 ; j++) { |
| 231 | wid = (val & (MTK_WIDTH_MASK << j * 8)) >> j * 8; |
| 232 | rawir.pulse = !rawir.pulse; |
| 233 | rawir.duration = wid * (MTK_IR_SAMPLE + 1); |
| 234 | ir_raw_event_store_with_filter(ir->rc, &rawir); |
| 235 | } |
| 236 | } |
| 237 | |
| 238 | /* |
| 239 | * The maximum number of edges the IR controller can |
| 240 | * hold is MTK_CHKDATA_SZ * 4. So if received IR messages |
| 241 | * is over the limit, the last incomplete IR message would |
| 242 | * be appended trailing space and still would be sent into |
| 243 | * ir-rc-raw to decode. That helps it is possible that it |
| 244 | * has enough information to decode a scancode even if the |
| 245 | * trailing end of the message is missing. |
| 246 | */ |
| 247 | if (!MTK_IR_END(wid, rawir.pulse)) { |
| 248 | rawir.pulse = false; |
| 249 | rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1); |
| 250 | ir_raw_event_store_with_filter(ir->rc, &rawir); |
| 251 | } |
| 252 | |
| 253 | ir_raw_event_handle(ir->rc); |
| 254 | |
| 255 | /* |
| 256 | * Restart controller for the next receive that would |
| 257 | * clear up all CHKDATA registers |
| 258 | */ |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 259 | mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]); |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 260 | |
| 261 | /* Clear interrupt status */ |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 262 | mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR, |
| 263 | ir->data->regs[MTK_IRINT_CLR_REG]); |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 264 | |
| 265 | return IRQ_HANDLED; |
| 266 | } |
| 267 | |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 268 | static const struct mtk_ir_data mt7623_data = { |
| 269 | .regs = mt7623_regs, |
| 270 | .fields = mt7623_fields, |
| 271 | .ok_count = 0xf, |
| 272 | .hw_period = 0xff, |
| 273 | .div = 4, |
| 274 | }; |
| 275 | |
Sean Wang | 5838998 | 2017-06-30 02:03:06 -0400 | [diff] [blame] | 276 | static const struct mtk_ir_data mt7622_data = { |
| 277 | .regs = mt7622_regs, |
| 278 | .fields = mt7622_fields, |
| 279 | .ok_count = 0xf, |
| 280 | .hw_period = 0xffff, |
| 281 | .div = 32, |
| 282 | }; |
| 283 | |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 284 | static const struct of_device_id mtk_ir_match[] = { |
| 285 | { .compatible = "mediatek,mt7623-cir", .data = &mt7623_data}, |
Sean Wang | 5838998 | 2017-06-30 02:03:06 -0400 | [diff] [blame] | 286 | { .compatible = "mediatek,mt7622-cir", .data = &mt7622_data}, |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 287 | {}, |
| 288 | }; |
| 289 | MODULE_DEVICE_TABLE(of, mtk_ir_match); |
| 290 | |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 291 | static int mtk_ir_probe(struct platform_device *pdev) |
| 292 | { |
| 293 | struct device *dev = &pdev->dev; |
| 294 | struct device_node *dn = dev->of_node; |
| 295 | struct resource *res; |
| 296 | struct mtk_ir *ir; |
| 297 | u32 val; |
| 298 | int ret = 0; |
| 299 | const char *map_name; |
| 300 | |
| 301 | ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL); |
| 302 | if (!ir) |
| 303 | return -ENOMEM; |
| 304 | |
| 305 | ir->dev = dev; |
Ryder Lee | 5d0af51 | 2018-04-15 22:34:30 -0400 | [diff] [blame] | 306 | ir->data = of_device_get_match_data(dev); |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 307 | |
| 308 | ir->clk = devm_clk_get(dev, "clk"); |
| 309 | if (IS_ERR(ir->clk)) { |
| 310 | dev_err(dev, "failed to get a ir clock.\n"); |
| 311 | return PTR_ERR(ir->clk); |
| 312 | } |
| 313 | |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 314 | ir->bus = devm_clk_get(dev, "bus"); |
| 315 | if (IS_ERR(ir->bus)) { |
| 316 | /* |
| 317 | * For compatibility with older device trees try unnamed |
| 318 | * ir->bus uses the same clock as ir->clock. |
| 319 | */ |
| 320 | ir->bus = ir->clk; |
| 321 | } |
| 322 | |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 323 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 324 | ir->base = devm_ioremap_resource(dev, res); |
Ding Xiang | 9e2e438 | 2019-06-18 05:13:09 -0400 | [diff] [blame] | 325 | if (IS_ERR(ir->base)) |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 326 | return PTR_ERR(ir->base); |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 327 | |
| 328 | ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW); |
| 329 | if (!ir->rc) { |
| 330 | dev_err(dev, "failed to allocate device\n"); |
| 331 | return -ENOMEM; |
| 332 | } |
| 333 | |
| 334 | ir->rc->priv = ir; |
Sean Young | 518f4b2 | 2017-07-01 12:13:19 -0400 | [diff] [blame] | 335 | ir->rc->device_name = MTK_IR_DEV; |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 336 | ir->rc->input_phys = MTK_IR_DEV "/input0"; |
| 337 | ir->rc->input_id.bustype = BUS_HOST; |
| 338 | ir->rc->input_id.vendor = 0x0001; |
| 339 | ir->rc->input_id.product = 0x0001; |
| 340 | ir->rc->input_id.version = 0x0001; |
| 341 | map_name = of_get_property(dn, "linux,rc-map-name", NULL); |
| 342 | ir->rc->map_name = map_name ?: RC_MAP_EMPTY; |
| 343 | ir->rc->dev.parent = dev; |
| 344 | ir->rc->driver_name = MTK_IR_DEV; |
Sean Young | eab8652 | 2019-07-12 18:46:58 -0400 | [diff] [blame] | 345 | ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 346 | ir->rc->rx_resolution = MTK_IR_SAMPLE; |
| 347 | ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1); |
| 348 | |
| 349 | ret = devm_rc_register_device(dev, ir->rc); |
| 350 | if (ret) { |
| 351 | dev_err(dev, "failed to register rc device\n"); |
| 352 | return ret; |
| 353 | } |
| 354 | |
| 355 | platform_set_drvdata(pdev, ir); |
| 356 | |
| 357 | ir->irq = platform_get_irq(pdev, 0); |
Stephen Boyd | 97299a3 | 2019-07-30 15:15:25 -0300 | [diff] [blame] | 358 | if (ir->irq < 0) |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 359 | return -ENODEV; |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 360 | |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 361 | if (clk_prepare_enable(ir->clk)) { |
| 362 | dev_err(dev, "try to enable ir_clk failed\n"); |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 363 | return -EINVAL; |
| 364 | } |
| 365 | |
| 366 | if (clk_prepare_enable(ir->bus)) { |
| 367 | dev_err(dev, "try to enable ir_clk failed\n"); |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 368 | ret = -EINVAL; |
| 369 | goto exit_clkdisable_clk; |
| 370 | } |
| 371 | |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 372 | /* |
| 373 | * Enable interrupt after proper hardware |
| 374 | * setup and IRQ handler registration |
| 375 | */ |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 376 | mtk_irq_disable(ir, MTK_IRINT_EN); |
| 377 | |
| 378 | ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir); |
| 379 | if (ret) { |
| 380 | dev_err(dev, "failed request irq\n"); |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 381 | goto exit_clkdisable_bus; |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 382 | } |
| 383 | |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 384 | /* |
| 385 | * Setup software sample period as the reference of software decoder |
| 386 | */ |
| 387 | val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) & |
| 388 | ir->data->fields[MTK_CHK_PERIOD].mask; |
| 389 | mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask, |
| 390 | ir->data->fields[MTK_CHK_PERIOD].reg); |
| 391 | |
| 392 | /* |
| 393 | * Setup hardware sampling period used to setup the proper timeout for |
| 394 | * indicating end of IR receiving completion |
| 395 | */ |
| 396 | val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) & |
| 397 | ir->data->fields[MTK_HW_PERIOD].mask; |
| 398 | mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask, |
| 399 | ir->data->fields[MTK_HW_PERIOD].reg); |
| 400 | |
Sean Young | 5dd4b89 | 2019-07-12 18:47:00 -0400 | [diff] [blame] | 401 | /* Set de-glitch counter */ |
| 402 | mtk_w32_mask(ir, MTK_DG_CNT(1), MTK_DG_CNT_MASK, MTK_IRTHD); |
| 403 | |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 404 | /* Enable IR and PWM */ |
| 405 | val = mtk_r32(ir, MTK_CONFIG_HIGH_REG); |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 406 | val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN; |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 407 | mtk_w32(ir, val, MTK_CONFIG_HIGH_REG); |
| 408 | |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 409 | mtk_irq_enable(ir, MTK_IRINT_EN); |
| 410 | |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 411 | dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n", |
Sean Young | d904eb0 | 2020-11-29 18:01:26 +0100 | [diff] [blame] | 412 | MTK_IR_SAMPLE); |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 413 | |
| 414 | return 0; |
| 415 | |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 416 | exit_clkdisable_bus: |
| 417 | clk_disable_unprepare(ir->bus); |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 418 | exit_clkdisable_clk: |
| 419 | clk_disable_unprepare(ir->clk); |
| 420 | |
| 421 | return ret; |
| 422 | } |
| 423 | |
| 424 | static int mtk_ir_remove(struct platform_device *pdev) |
| 425 | { |
| 426 | struct mtk_ir *ir = platform_get_drvdata(pdev); |
| 427 | |
| 428 | /* |
| 429 | * Avoid contention between remove handler and |
| 430 | * IRQ handler so that disabling IR interrupt and |
| 431 | * waiting for pending IRQ handler to complete |
| 432 | */ |
| 433 | mtk_irq_disable(ir, MTK_IRINT_EN); |
| 434 | synchronize_irq(ir->irq); |
| 435 | |
Sean Wang | 50c3c1b | 2017-06-30 02:03:05 -0400 | [diff] [blame] | 436 | clk_disable_unprepare(ir->bus); |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 437 | clk_disable_unprepare(ir->clk); |
| 438 | |
| 439 | return 0; |
| 440 | } |
| 441 | |
Sean Wang | 6691e7b | 2017-01-13 05:35:39 -0200 | [diff] [blame] | 442 | static struct platform_driver mtk_ir_driver = { |
| 443 | .probe = mtk_ir_probe, |
| 444 | .remove = mtk_ir_remove, |
| 445 | .driver = { |
| 446 | .name = MTK_IR_DEV, |
| 447 | .of_match_table = mtk_ir_match, |
| 448 | }, |
| 449 | }; |
| 450 | |
| 451 | module_platform_driver(mtk_ir_driver); |
| 452 | |
| 453 | MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver"); |
| 454 | MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); |
| 455 | MODULE_LICENSE("GPL"); |