blob: 8d85fc58142e62861f5481ff711aabe206bd5f0f [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53#define RADEON_VERSION "0.2.0"
54
Linus Torvalds1da177e2005-04-16 15:20:36 -070055#include <linux/module.h>
56#include <linux/moduleparam.h>
57#include <linux/kernel.h>
58#include <linux/errno.h>
59#include <linux/string.h>
60#include <linux/mm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070061#include <linux/slab.h>
62#include <linux/delay.h>
63#include <linux/time.h>
64#include <linux/fb.h>
65#include <linux/ioport.h>
66#include <linux/init.h>
67#include <linux/pci.h>
68#include <linux/vmalloc.h>
69#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070070
71#include <asm/io.h>
72#include <asm/uaccess.h>
73
74#ifdef CONFIG_PPC_OF
75
76#include <asm/pci-bridge.h>
77#include "../macmodes.h"
78
Linus Torvalds1da177e2005-04-16 15:20:36 -070079#ifdef CONFIG_BOOTX_TEXT
80#include <asm/btext.h>
81#endif
82
83#endif /* CONFIG_PPC_OF */
84
85#ifdef CONFIG_MTRR
86#include <asm/mtrr.h>
87#endif
88
89#include <video/radeon.h>
90#include <linux/radeonfb.h>
91
92#include "../edid.h" // MOVE THAT TO include/video
93#include "ati_ids.h"
94#include "radeonfb.h"
95
96#define MAX_MAPPED_VRAM (2048*2048*4)
97#define MIN_MAPPED_VRAM (1024*768*1)
98
99#define CHIP_DEF(id, family, flags) \
100 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
101
102static struct pci_device_id radeonfb_pci_table[] = {
103 /* Mobility M6 */
104 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
105 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
106 /* Radeon VE/7000 */
107 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
108 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
Jake Moilanen183dee02005-11-07 01:00:55 -0800109 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110 /* Radeon IGP320M (U1) */
111 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
112 /* Radeon IGP320 (A3) */
113 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
114 /* IGP330M/340M/350M (U2) */
115 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
116 /* IGP330/340/350 (A4) */
117 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
118 /* Mobility 7000 IGP */
119 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
120 /* 7000 IGP (A4+) */
121 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
122 /* 8500 AIW */
123 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
124 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
125 /* 8700/8800 */
126 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
127 /* 8500 */
128 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
129 /* 9100 */
130 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
131 /* Mobility M7 */
132 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
133 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
134 /* 7500 */
135 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
136 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
137 /* Mobility M9 */
138 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
139 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
141 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
142 /* 9000/Pro */
143 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
144 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
145 /* Mobility 9100 IGP (U3) */
146 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
147 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
148 /* 9100 IGP (A5) */
149 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
150 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
151 /* Mobility 9200 (M9+) */
152 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
153 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
154 /* 9200 */
155 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
156 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
157 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
158 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
159 /* 9500 */
160 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
161 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
162 /* 9600TX / FireGL Z1 */
163 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
165 /* 9700/9500/Pro/FireGL X1 */
166 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
167 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
168 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
169 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
170 /* Mobility M10/M11 */
171 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
172 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
173 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
174 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
175 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
176 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
177 /* 9600/FireGL T2 */
178 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
179 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
180 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
181 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
182 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
183 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
184 /* 9800/Pro/FileGL X2 */
185 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
191 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
193 /* Newer stuff */
194 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
197 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
198 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
199 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
200 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
201 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
203 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
205 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
211 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
212 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
220 /* Original Radeon/7200 */
221 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
222 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
223 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
224 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
225 { 0, }
226};
227MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
228
229
230typedef struct {
231 u16 reg;
232 u32 val;
233} reg_val;
234
235
236/* these common regs are cleared before mode setting so they do not
237 * interfere with anything
238 */
239static reg_val common_regs[] = {
240 { OVR_CLR, 0 },
241 { OVR_WID_LEFT_RIGHT, 0 },
242 { OVR_WID_TOP_BOTTOM, 0 },
243 { OV0_SCALE_CNTL, 0 },
244 { SUBPIC_CNTL, 0 },
245 { VIPH_CONTROL, 0 },
246 { I2C_CNTL_1, 0 },
247 { GEN_INT_CNTL, 0 },
248 { CAP0_TRIG_CNTL, 0 },
249 { CAP1_TRIG_CNTL, 0 },
250};
251
252/*
253 * globals
254 */
255
256static char *mode_option;
257static char *monitor_layout;
258static int noaccel = 0;
259static int default_dynclk = -2;
260static int nomodeset = 0;
261static int ignore_edid = 0;
262static int mirror = 0;
263static int panel_yres = 0;
264static int force_dfp = 0;
265static int force_measure_pll = 0;
266#ifdef CONFIG_MTRR
267static int nomtrr = 0;
268#endif
269
270/*
271 * prototypes
272 */
273
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
275{
276 if (!rinfo->bios_seg)
277 return;
278 pci_unmap_rom(dev, rinfo->bios_seg);
279}
280
281static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
282{
283 void __iomem *rom;
284 u16 dptr;
285 u8 rom_type;
286 size_t rom_size;
287
288 /* If this is a primary card, there is a shadow copy of the
289 * ROM somewhere in the first meg. We will just ignore the copy
290 * and use the ROM directly.
291 */
292
293 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
294 unsigned int temp;
295 temp = INREG(MPP_TB_CONFIG);
296 temp &= 0x00ffffffu;
297 temp |= 0x04 << 24;
298 OUTREG(MPP_TB_CONFIG, temp);
299 temp = INREG(MPP_TB_CONFIG);
300
301 rom = pci_map_rom(dev, &rom_size);
302 if (!rom) {
303 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
304 pci_name(rinfo->pdev));
305 return -ENOMEM;
306 }
307
308 rinfo->bios_seg = rom;
309
310 /* Very simple test to make sure it appeared */
311 if (BIOS_IN16(0) != 0xaa55) {
Olaf Hering3b4abff2005-09-09 13:10:06 -0700312 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
313 "should be 0xaa55\n",
314 pci_name(rinfo->pdev), BIOS_IN16(0));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315 goto failed;
316 }
317 /* Look for the PCI data to check the ROM type */
318 dptr = BIOS_IN16(0x18);
319
320 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
321 * for now, until I've verified this works everywhere. The goal here is more
322 * to phase out Open Firmware images.
323 *
324 * Currently, we only look at the first PCI data, we could iteratre and deal with
325 * them all, and we should use fb_bios_start relative to start of image and not
326 * relative start of ROM, but so far, I never found a dual-image ATI card
327 *
328 * typedef struct {
329 * u32 signature; + 0x00
330 * u16 vendor; + 0x04
331 * u16 device; + 0x06
332 * u16 reserved_1; + 0x08
333 * u16 dlen; + 0x0a
334 * u8 drevision; + 0x0c
335 * u8 class_hi; + 0x0d
336 * u16 class_lo; + 0x0e
337 * u16 ilen; + 0x10
338 * u16 irevision; + 0x12
339 * u8 type; + 0x14
340 * u8 indicator; + 0x15
341 * u16 reserved_2; + 0x16
342 * } pci_data_t;
343 */
344 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
345 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
346 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
347 goto anyway;
348 }
349 rom_type = BIOS_IN8(dptr + 0x14);
350 switch(rom_type) {
351 case 0:
352 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
353 break;
354 case 1:
355 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
356 goto failed;
357 case 2:
358 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
359 goto failed;
360 default:
361 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
362 goto failed;
363 }
364 anyway:
365 /* Locate the flat panel infos, do some sanity checking !!! */
366 rinfo->fp_bios_start = BIOS_IN16(0x48);
367 return 0;
368
369 failed:
370 rinfo->bios_seg = NULL;
371 radeon_unmap_ROM(rinfo, dev);
372 return -ENXIO;
373}
374
375#ifdef CONFIG_X86
376static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
377{
378 /* I simplified this code as we used to miss the signatures in
379 * a lot of case. It's now closer to XFree, we just don't check
380 * for signatures at all... Something better will have to be done
381 * if we end up having conflicts
382 */
383 u32 segstart;
384 void __iomem *rom_base = NULL;
385
386 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
387 rom_base = ioremap(segstart, 0x10000);
388 if (rom_base == NULL)
389 return -ENOMEM;
390 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
391 break;
392 iounmap(rom_base);
393 rom_base = NULL;
394 }
395 if (rom_base == NULL)
396 return -ENXIO;
397
398 /* Locate the flat panel infos, do some sanity checking !!! */
399 rinfo->bios_seg = rom_base;
400 rinfo->fp_bios_start = BIOS_IN16(0x48);
401
402 return 0;
403}
404#endif
405
406#ifdef CONFIG_PPC_OF
407/*
408 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
409 * tree. Hopefully, ATI OF driver is kind enough to fill these
410 */
411static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
412{
413 struct device_node *dp = rinfo->of_node;
414 u32 *val;
415
416 if (dp == NULL)
417 return -ENODEV;
418 val = (u32 *) get_property(dp, "ATY,RefCLK", NULL);
419 if (!val || !*val) {
420 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
421 return -EINVAL;
422 }
423
424 rinfo->pll.ref_clk = (*val) / 10;
425
426 val = (u32 *) get_property(dp, "ATY,SCLK", NULL);
427 if (val && *val)
428 rinfo->pll.sclk = (*val) / 10;
429
430 val = (u32 *) get_property(dp, "ATY,MCLK", NULL);
431 if (val && *val)
432 rinfo->pll.mclk = (*val) / 10;
433
434 return 0;
435}
436#endif /* CONFIG_PPC_OF */
437
438/*
439 * Read PLL infos from chip registers
440 */
441static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
442{
443 unsigned char ppll_div_sel;
444 unsigned Ns, Nm, M;
445 unsigned sclk, mclk, tmp, ref_div;
446 int hTotal, vTotal, num, denom, m, n;
447 unsigned long long hz, vclk;
448 long xtal;
449 struct timeval start_tv, stop_tv;
450 long total_secs, total_usecs;
451 int i;
452
453 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
454 * here, so... --BenH
455 */
456
457 /* Flush PCI buffers ? */
David S. Miller017fb982005-09-29 19:26:51 -0700458 tmp = INREG16(DEVICE_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459
460 local_irq_disable();
461
462 for(i=0; i<1000000; i++)
463 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
464 break;
465
466 do_gettimeofday(&start_tv);
467
468 for(i=0; i<1000000; i++)
469 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
470 break;
471
472 for(i=0; i<1000000; i++)
473 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
474 break;
475
476 do_gettimeofday(&stop_tv);
477
478 local_irq_enable();
479
480 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
481 if (total_secs > 10)
482 return -1;
483 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
484 total_usecs += total_secs * 1000000;
485 if (total_usecs < 0)
486 total_usecs = -total_usecs;
487 hz = 1000000/total_usecs;
488
489 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
490 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
491 vclk = (long long)hTotal * (long long)vTotal * hz;
492
493 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
494 case 0:
495 default:
496 num = 1;
497 denom = 1;
498 break;
499 case 1:
500 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
501 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
502 num = 2*n;
503 denom = 2*m;
504 break;
505 case 2:
506 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
507 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
508 num = 2*n;
509 denom = 2*m;
510 break;
511 }
512
513 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
514 radeon_pll_errata_after_index(rinfo);
515
516 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
517 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
518
519 num *= n;
520 denom *= m;
521
522 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
523 case 1:
524 denom *= 2;
525 break;
526 case 2:
527 denom *= 4;
528 break;
529 case 3:
530 denom *= 8;
531 break;
532 case 4:
533 denom *= 3;
534 break;
535 case 6:
536 denom *= 6;
537 break;
538 case 7:
539 denom *= 12;
540 break;
541 }
542
543 vclk *= denom;
544 do_div(vclk, 1000 * num);
545 xtal = vclk;
546
547 if ((xtal > 26900) && (xtal < 27100))
548 xtal = 2700;
549 else if ((xtal > 14200) && (xtal < 14400))
550 xtal = 1432;
551 else if ((xtal > 29400) && (xtal < 29600))
552 xtal = 2950;
553 else {
554 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
555 return -1;
556 }
557
558 tmp = INPLL(M_SPLL_REF_FB_DIV);
559 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
560
561 Ns = (tmp & 0xff0000) >> 16;
562 Nm = (tmp & 0xff00) >> 8;
563 M = (tmp & 0xff);
564 sclk = round_div((2 * Ns * xtal), (2 * M));
565 mclk = round_div((2 * Nm * xtal), (2 * M));
566
567 /* we're done, hopefully these are sane values */
568 rinfo->pll.ref_clk = xtal;
569 rinfo->pll.ref_div = ref_div;
570 rinfo->pll.sclk = sclk;
571 rinfo->pll.mclk = mclk;
572
573 return 0;
574}
575
576/*
Matt Mackall4a4efbd2006-01-03 13:27:11 +0100577 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700578 */
579static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
580{
581 /*
582 * In the case nothing works, these are defaults; they are mostly
583 * incomplete, however. It does provide ppll_max and _min values
584 * even for most other methods, however.
585 */
586 switch (rinfo->chipset) {
587 case PCI_DEVICE_ID_ATI_RADEON_QW:
588 case PCI_DEVICE_ID_ATI_RADEON_QX:
589 rinfo->pll.ppll_max = 35000;
590 rinfo->pll.ppll_min = 12000;
591 rinfo->pll.mclk = 23000;
592 rinfo->pll.sclk = 23000;
593 rinfo->pll.ref_clk = 2700;
594 break;
595 case PCI_DEVICE_ID_ATI_RADEON_QL:
596 case PCI_DEVICE_ID_ATI_RADEON_QN:
597 case PCI_DEVICE_ID_ATI_RADEON_QO:
598 case PCI_DEVICE_ID_ATI_RADEON_Ql:
599 case PCI_DEVICE_ID_ATI_RADEON_BB:
600 rinfo->pll.ppll_max = 35000;
601 rinfo->pll.ppll_min = 12000;
602 rinfo->pll.mclk = 27500;
603 rinfo->pll.sclk = 27500;
604 rinfo->pll.ref_clk = 2700;
605 break;
606 case PCI_DEVICE_ID_ATI_RADEON_Id:
607 case PCI_DEVICE_ID_ATI_RADEON_Ie:
608 case PCI_DEVICE_ID_ATI_RADEON_If:
609 case PCI_DEVICE_ID_ATI_RADEON_Ig:
610 rinfo->pll.ppll_max = 35000;
611 rinfo->pll.ppll_min = 12000;
612 rinfo->pll.mclk = 25000;
613 rinfo->pll.sclk = 25000;
614 rinfo->pll.ref_clk = 2700;
615 break;
616 case PCI_DEVICE_ID_ATI_RADEON_ND:
617 case PCI_DEVICE_ID_ATI_RADEON_NE:
618 case PCI_DEVICE_ID_ATI_RADEON_NF:
619 case PCI_DEVICE_ID_ATI_RADEON_NG:
620 rinfo->pll.ppll_max = 40000;
621 rinfo->pll.ppll_min = 20000;
622 rinfo->pll.mclk = 27000;
623 rinfo->pll.sclk = 27000;
624 rinfo->pll.ref_clk = 2700;
625 break;
626 case PCI_DEVICE_ID_ATI_RADEON_QD:
627 case PCI_DEVICE_ID_ATI_RADEON_QE:
628 case PCI_DEVICE_ID_ATI_RADEON_QF:
629 case PCI_DEVICE_ID_ATI_RADEON_QG:
630 default:
631 rinfo->pll.ppll_max = 35000;
632 rinfo->pll.ppll_min = 12000;
633 rinfo->pll.mclk = 16600;
634 rinfo->pll.sclk = 16600;
635 rinfo->pll.ref_clk = 2700;
636 break;
637 }
638 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
639
640
641#ifdef CONFIG_PPC_OF
642 /*
Matt Mackall4a4efbd2006-01-03 13:27:11 +0100643 * Retrieve PLL infos from Open Firmware first
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644 */
645 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
Matt Mackall4a4efbd2006-01-03 13:27:11 +0100646 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647 goto found;
648 }
649#endif /* CONFIG_PPC_OF */
650
651 /*
652 * Check out if we have an X86 which gave us some PLL informations
Matt Mackall4a4efbd2006-01-03 13:27:11 +0100653 * and if yes, retrieve them
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654 */
655 if (!force_measure_pll && rinfo->bios_seg) {
656 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
657
658 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
659 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
660 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
661 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
662 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
663 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
664
Matt Mackall4a4efbd2006-01-03 13:27:11 +0100665 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666 goto found;
667 }
668
669 /*
670 * We didn't get PLL parameters from either OF or BIOS, we try to
671 * probe them
672 */
673 if (radeon_probe_pll_params(rinfo) == 0) {
Matt Mackall4a4efbd2006-01-03 13:27:11 +0100674 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675 goto found;
676 }
677
678 /*
679 * Fall back to already-set defaults...
680 */
681 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
682
683found:
684 /*
Matt Mackall4a4efbd2006-01-03 13:27:11 +0100685 * Some methods fail to retrieve SCLK and MCLK values, we apply default
Linus Torvalds1da177e2005-04-16 15:20:36 -0700686 * settings in this case (200Mhz). If that really happne often, we could
687 * fetch from registers instead...
688 */
689 if (rinfo->pll.mclk == 0)
690 rinfo->pll.mclk = 20000;
691 if (rinfo->pll.sclk == 0)
692 rinfo->pll.sclk = 20000;
693
694 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
695 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
696 rinfo->pll.ref_div,
697 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
698 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
699 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
700}
701
702static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
703{
704 struct radeonfb_info *rinfo = info->par;
705 struct fb_var_screeninfo v;
706 int nom, den;
707 unsigned int pitch;
708
709 if (radeon_match_mode(rinfo, &v, var))
710 return -EINVAL;
711
712 switch (v.bits_per_pixel) {
713 case 0 ... 8:
714 v.bits_per_pixel = 8;
715 break;
716 case 9 ... 16:
717 v.bits_per_pixel = 16;
718 break;
719 case 17 ... 24:
720#if 0 /* Doesn't seem to work */
721 v.bits_per_pixel = 24;
722 break;
723#endif
724 return -EINVAL;
725 case 25 ... 32:
726 v.bits_per_pixel = 32;
727 break;
728 default:
729 return -EINVAL;
730 }
731
732 switch (var_to_depth(&v)) {
733 case 8:
734 nom = den = 1;
735 v.red.offset = v.green.offset = v.blue.offset = 0;
736 v.red.length = v.green.length = v.blue.length = 8;
737 v.transp.offset = v.transp.length = 0;
738 break;
739 case 15:
740 nom = 2;
741 den = 1;
742 v.red.offset = 10;
743 v.green.offset = 5;
744 v.blue.offset = 0;
745 v.red.length = v.green.length = v.blue.length = 5;
746 v.transp.offset = v.transp.length = 0;
747 break;
748 case 16:
749 nom = 2;
750 den = 1;
751 v.red.offset = 11;
752 v.green.offset = 5;
753 v.blue.offset = 0;
754 v.red.length = 5;
755 v.green.length = 6;
756 v.blue.length = 5;
757 v.transp.offset = v.transp.length = 0;
758 break;
759 case 24:
760 nom = 4;
761 den = 1;
762 v.red.offset = 16;
763 v.green.offset = 8;
764 v.blue.offset = 0;
765 v.red.length = v.blue.length = v.green.length = 8;
766 v.transp.offset = v.transp.length = 0;
767 break;
768 case 32:
769 nom = 4;
770 den = 1;
771 v.red.offset = 16;
772 v.green.offset = 8;
773 v.blue.offset = 0;
774 v.red.length = v.blue.length = v.green.length = 8;
775 v.transp.offset = 24;
776 v.transp.length = 8;
777 break;
778 default:
779 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
780 var->xres, var->yres, var->bits_per_pixel);
781 return -EINVAL;
782 }
783
784 if (v.yres_virtual < v.yres)
785 v.yres_virtual = v.yres;
786 if (v.xres_virtual < v.xres)
787 v.xres_virtual = v.xres;
788
789
790 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
791 * with some panels, though I don't quite like this solution
792 */
793 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
794 v.xres_virtual = v.xres_virtual & ~7ul;
795 } else {
796 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
797 & ~(0x3f)) >> 6;
798 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
799 }
800
801 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
802 return -EINVAL;
803
804 if (v.xres_virtual < v.xres)
805 v.xres = v.xres_virtual;
806
807 if (v.xoffset < 0)
808 v.xoffset = 0;
809 if (v.yoffset < 0)
810 v.yoffset = 0;
811
812 if (v.xoffset > v.xres_virtual - v.xres)
813 v.xoffset = v.xres_virtual - v.xres - 1;
814
815 if (v.yoffset > v.yres_virtual - v.yres)
816 v.yoffset = v.yres_virtual - v.yres - 1;
817
818 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
819 v.transp.offset = v.transp.length =
820 v.transp.msb_right = 0;
821
822 memcpy(var, &v, sizeof(v));
823
824 return 0;
825}
826
827
828static int radeonfb_pan_display (struct fb_var_screeninfo *var,
829 struct fb_info *info)
830{
831 struct radeonfb_info *rinfo = info->par;
832
833 if ((var->xoffset + var->xres > var->xres_virtual)
834 || (var->yoffset + var->yres > var->yres_virtual))
835 return -EINVAL;
836
837 if (rinfo->asleep)
838 return 0;
839
840 radeon_fifo_wait(2);
841 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
842 * var->bits_per_pixel / 8) & ~7);
843 return 0;
844}
845
846
Christoph Hellwig67a66802006-01-14 13:21:25 -0800847static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
848 unsigned long arg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849{
850 struct radeonfb_info *rinfo = info->par;
851 unsigned int tmp;
852 u32 value = 0;
853 int rc;
854
855 switch (cmd) {
856 /*
857 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
858 * and do something better using 2nd CRTC instead of just hackish
859 * routing to second output
860 */
861 case FBIO_RADEON_SET_MIRROR:
862 if (!rinfo->is_mobility)
863 return -EINVAL;
864
865 rc = get_user(value, (__u32 __user *)arg);
866
867 if (rc)
868 return rc;
869
870 radeon_fifo_wait(2);
871 if (value & 0x01) {
872 tmp = INREG(LVDS_GEN_CNTL);
873
874 tmp |= (LVDS_ON | LVDS_BLON);
875 } else {
876 tmp = INREG(LVDS_GEN_CNTL);
877
878 tmp &= ~(LVDS_ON | LVDS_BLON);
879 }
880
881 OUTREG(LVDS_GEN_CNTL, tmp);
882
883 if (value & 0x02) {
884 tmp = INREG(CRTC_EXT_CNTL);
885 tmp |= CRTC_CRT_ON;
886
887 mirror = 1;
888 } else {
889 tmp = INREG(CRTC_EXT_CNTL);
890 tmp &= ~CRTC_CRT_ON;
891
892 mirror = 0;
893 }
894
895 OUTREG(CRTC_EXT_CNTL, tmp);
896
897 return 0;
898 case FBIO_RADEON_GET_MIRROR:
899 if (!rinfo->is_mobility)
900 return -EINVAL;
901
902 tmp = INREG(LVDS_GEN_CNTL);
903 if ((LVDS_ON | LVDS_BLON) & tmp)
904 value |= 0x01;
905
906 tmp = INREG(CRTC_EXT_CNTL);
907 if (CRTC_CRT_ON & tmp)
908 value |= 0x02;
909
910 return put_user(value, (__u32 __user *)arg);
911 default:
912 return -EINVAL;
913 }
914
915 return -EINVAL;
916}
917
918
919int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
920{
921 u32 val;
922 u32 tmp_pix_clks;
923 int unblank = 0;
924
925 if (rinfo->lock_blank)
926 return 0;
927
928 radeon_engine_idle();
929
930 val = INREG(CRTC_EXT_CNTL);
931 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
932 CRTC_VSYNC_DIS);
933 switch (blank) {
934 case FB_BLANK_VSYNC_SUSPEND:
935 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
936 break;
937 case FB_BLANK_HSYNC_SUSPEND:
938 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
939 break;
940 case FB_BLANK_POWERDOWN:
941 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
942 CRTC_HSYNC_DIS);
943 break;
944 case FB_BLANK_NORMAL:
945 val |= CRTC_DISPLAY_DIS;
946 break;
947 case FB_BLANK_UNBLANK:
948 default:
949 unblank = 1;
950 }
951 OUTREG(CRTC_EXT_CNTL, val);
952
953
954 switch (rinfo->mon1_type) {
955 case MT_DFP:
956 if (unblank)
957 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
958 ~(FP_FPON | FP_TMDS_EN));
959 else {
960 if (mode_switch || blank == FB_BLANK_NORMAL)
961 break;
962 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
963 }
964 break;
965 case MT_LCD:
966 del_timer_sync(&rinfo->lvds_timer);
967 val = INREG(LVDS_GEN_CNTL);
968 if (unblank) {
969 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
970 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
971 & (LVDS_DIGON | LVDS_BL_MOD_EN));
972 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
973 OUTREG(LVDS_GEN_CNTL, target_val);
974 else if ((val ^ target_val) != 0) {
975 OUTREG(LVDS_GEN_CNTL, target_val
976 & ~(LVDS_ON | LVDS_BL_MOD_EN));
977 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
978 rinfo->init_state.lvds_gen_cntl |=
979 target_val & LVDS_STATE_MASK;
980 if (mode_switch) {
981 radeon_msleep(rinfo->panel_info.pwr_delay);
982 OUTREG(LVDS_GEN_CNTL, target_val);
983 }
984 else {
985 rinfo->pending_lvds_gen_cntl = target_val;
986 mod_timer(&rinfo->lvds_timer,
987 jiffies +
988 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
989 }
990 }
991 } else {
992 val |= LVDS_DISPLAY_DIS;
993 OUTREG(LVDS_GEN_CNTL, val);
994
995 /* We don't do a full switch-off on a simple mode switch */
996 if (mode_switch || blank == FB_BLANK_NORMAL)
997 break;
998
999 /* Asic bug, when turning off LVDS_ON, we have to make sure
1000 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1001 */
1002 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1003 if (rinfo->is_mobility || rinfo->is_IGP)
1004 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1005 val &= ~(LVDS_BL_MOD_EN);
1006 OUTREG(LVDS_GEN_CNTL, val);
1007 udelay(100);
1008 val &= ~(LVDS_ON | LVDS_EN);
1009 OUTREG(LVDS_GEN_CNTL, val);
1010 val &= ~LVDS_DIGON;
1011 rinfo->pending_lvds_gen_cntl = val;
1012 mod_timer(&rinfo->lvds_timer,
1013 jiffies +
1014 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1015 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1016 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1017 if (rinfo->is_mobility || rinfo->is_IGP)
1018 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1019 }
1020 break;
1021 case MT_CRT:
1022 // todo: powerdown DAC
1023 default:
1024 break;
1025 }
1026
1027 /* let fbcon do a soft blank for us */
1028 return (blank == FB_BLANK_NORMAL) ? -EINVAL : 0;
1029}
1030
1031static int radeonfb_blank (int blank, struct fb_info *info)
1032{
1033 struct radeonfb_info *rinfo = info->par;
1034
1035 if (rinfo->asleep)
1036 return 0;
1037
1038 return radeon_screen_blank(rinfo, blank, 0);
1039}
1040
Benjamin Herrenschmidt71494372005-05-01 08:59:22 -07001041static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1042 unsigned blue, unsigned transp,
1043 struct radeonfb_info *rinfo)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001045 u32 pindex;
1046 unsigned int i;
Benjamin Herrenschmidt71494372005-05-01 08:59:22 -07001047
1048
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049 if (regno > 255)
Alan Currydb77ec22006-03-27 01:17:30 -08001050 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051
1052 red >>= 8;
1053 green >>= 8;
1054 blue >>= 8;
1055 rinfo->palette[regno].red = red;
1056 rinfo->palette[regno].green = green;
1057 rinfo->palette[regno].blue = blue;
1058
1059 /* default */
1060 pindex = regno;
1061
1062 if (!rinfo->asleep) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001063 radeon_fifo_wait(9);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001064
1065 if (rinfo->bpp == 16) {
1066 pindex = regno * 8;
1067
1068 if (rinfo->depth == 16 && regno > 63)
Alan Currydb77ec22006-03-27 01:17:30 -08001069 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001070 if (rinfo->depth == 15 && regno > 31)
Alan Currydb77ec22006-03-27 01:17:30 -08001071 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072
Benjamin Herrenschmidt71494372005-05-01 08:59:22 -07001073 /* For 565, the green component is mixed one order
1074 * below
1075 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001076 if (rinfo->depth == 16) {
1077 OUTREG(PALETTE_INDEX, pindex>>1);
Benjamin Herrenschmidt71494372005-05-01 08:59:22 -07001078 OUTREG(PALETTE_DATA,
1079 (rinfo->palette[regno>>1].red << 16) |
1080 (green << 8) |
1081 (rinfo->palette[regno>>1].blue));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082 green = rinfo->palette[regno<<1].green;
1083 }
1084 }
1085
1086 if (rinfo->depth != 16 || regno < 32) {
1087 OUTREG(PALETTE_INDEX, pindex);
Benjamin Herrenschmidt71494372005-05-01 08:59:22 -07001088 OUTREG(PALETTE_DATA, (red << 16) |
1089 (green << 8) | blue);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001090 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001091 }
1092 if (regno < 16) {
Benjamin Herrenschmidt71494372005-05-01 08:59:22 -07001093 u32 *pal = rinfo->info->pseudo_palette;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094 switch (rinfo->depth) {
1095 case 15:
1096 pal[regno] = (regno << 10) | (regno << 5) | regno;
1097 break;
1098 case 16:
1099 pal[regno] = (regno << 11) | (regno << 5) | regno;
1100 break;
1101 case 24:
1102 pal[regno] = (regno << 16) | (regno << 8) | regno;
1103 break;
1104 case 32:
1105 i = (regno << 8) | regno;
1106 pal[regno] = (i << 16) | i;
1107 break;
1108 }
1109 }
1110 return 0;
1111}
1112
Benjamin Herrenschmidt71494372005-05-01 08:59:22 -07001113static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1114 unsigned blue, unsigned transp,
1115 struct fb_info *info)
1116{
1117 struct radeonfb_info *rinfo = info->par;
1118 u32 dac_cntl2, vclk_cntl = 0;
1119 int rc;
1120
1121 if (!rinfo->asleep) {
1122 if (rinfo->is_mobility) {
1123 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1124 OUTPLL(VCLK_ECP_CNTL,
1125 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1126 }
1127
1128 /* Make sure we are on first palette */
1129 if (rinfo->has_CRTC2) {
1130 dac_cntl2 = INREG(DAC_CNTL2);
1131 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1132 OUTREG(DAC_CNTL2, dac_cntl2);
1133 }
1134 }
1135
1136 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1137
1138 if (!rinfo->asleep && rinfo->is_mobility)
1139 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1140
1141 return rc;
1142}
1143
1144static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1145{
1146 struct radeonfb_info *rinfo = info->par;
1147 u16 *red, *green, *blue, *transp;
1148 u32 dac_cntl2, vclk_cntl = 0;
1149 int i, start, rc = 0;
1150
1151 if (!rinfo->asleep) {
1152 if (rinfo->is_mobility) {
1153 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1154 OUTPLL(VCLK_ECP_CNTL,
1155 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1156 }
1157
1158 /* Make sure we are on first palette */
1159 if (rinfo->has_CRTC2) {
1160 dac_cntl2 = INREG(DAC_CNTL2);
1161 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1162 OUTREG(DAC_CNTL2, dac_cntl2);
1163 }
1164 }
1165
1166 red = cmap->red;
1167 green = cmap->green;
1168 blue = cmap->blue;
1169 transp = cmap->transp;
1170 start = cmap->start;
1171
1172 for (i = 0; i < cmap->len; i++) {
1173 u_int hred, hgreen, hblue, htransp = 0xffff;
1174
1175 hred = *red++;
1176 hgreen = *green++;
1177 hblue = *blue++;
1178 if (transp)
1179 htransp = *transp++;
1180 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1181 rinfo);
1182 if (rc)
1183 break;
1184 }
1185
1186 if (!rinfo->asleep && rinfo->is_mobility)
1187 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1188
1189 return rc;
1190}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001191
1192static void radeon_save_state (struct radeonfb_info *rinfo,
1193 struct radeon_regs *save)
1194{
1195 /* CRTC regs */
1196 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1197 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1198 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1199 save->dac_cntl = INREG(DAC_CNTL);
1200 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1201 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1202 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1203 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1204 save->crtc_pitch = INREG(CRTC_PITCH);
1205 save->surface_cntl = INREG(SURFACE_CNTL);
1206
1207 /* FP regs */
1208 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1209 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1210 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1211 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1212 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1213 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1214 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1215 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1216 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1217 save->tmds_crc = INREG(TMDS_CRC);
1218 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1219 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1220
1221 /* PLL regs */
1222 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1223 radeon_pll_errata_after_index(rinfo);
1224 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1225 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1226}
1227
1228
1229static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1230{
1231 int i;
1232
1233 radeon_fifo_wait(20);
1234
1235 /* Workaround from XFree */
1236 if (rinfo->is_mobility) {
1237 /* A temporal workaround for the occational blanking on certain laptop
1238 * panels. This appears to related to the PLL divider registers
1239 * (fail to lock?). It occurs even when all dividers are the same
1240 * with their old settings. In this case we really don't need to
1241 * fiddle with PLL registers. By doing this we can avoid the blanking
1242 * problem with some panels.
1243 */
1244 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1245 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1246 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1247 /* We still have to force a switch to selected PPLL div thanks to
1248 * an XFree86 driver bug which will switch it away in some cases
1249 * even when using UseFDev */
1250 OUTREGP(CLOCK_CNTL_INDEX,
1251 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1252 ~PPLL_DIV_SEL_MASK);
1253 radeon_pll_errata_after_index(rinfo);
1254 radeon_pll_errata_after_data(rinfo);
1255 return;
1256 }
1257 }
1258
1259 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1260 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1261
1262 /* Reset PPLL & enable atomic update */
1263 OUTPLLP(PPLL_CNTL,
1264 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1265 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1266
1267 /* Switch to selected PPLL divider */
1268 OUTREGP(CLOCK_CNTL_INDEX,
1269 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1270 ~PPLL_DIV_SEL_MASK);
1271 radeon_pll_errata_after_index(rinfo);
1272 radeon_pll_errata_after_data(rinfo);
1273
1274 /* Set PPLL ref. div */
1275 if (rinfo->family == CHIP_FAMILY_R300 ||
1276 rinfo->family == CHIP_FAMILY_RS300 ||
1277 rinfo->family == CHIP_FAMILY_R350 ||
1278 rinfo->family == CHIP_FAMILY_RV350) {
1279 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1280 /* When restoring console mode, use saved PPLL_REF_DIV
1281 * setting.
1282 */
1283 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1284 } else {
1285 /* R300 uses ref_div_acc field as real ref divider */
1286 OUTPLLP(PPLL_REF_DIV,
1287 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1288 ~R300_PPLL_REF_DIV_ACC_MASK);
1289 }
1290 } else
1291 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1292
1293 /* Set PPLL divider 3 & post divider*/
1294 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1295 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1296
1297 /* Write update */
1298 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1299 ;
1300 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1301
1302 /* Wait read update complete */
1303 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1304 the cause yet, but this workaround will mask the problem for now.
1305 Other chips usually will pass at the very first test, so the
1306 workaround shouldn't have any effect on them. */
1307 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1308 ;
1309
1310 OUTPLL(HTOTAL_CNTL, 0);
1311
1312 /* Clear reset & atomic update */
1313 OUTPLLP(PPLL_CNTL, 0,
1314 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1315
1316 /* We may want some locking ... oh well */
1317 radeon_msleep(5);
1318
1319 /* Switch back VCLK source to PPLL */
1320 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1321}
1322
1323/*
1324 * Timer function for delayed LVDS panel power up/down
1325 */
1326static void radeon_lvds_timer_func(unsigned long data)
1327{
1328 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1329
1330 radeon_engine_idle();
1331
1332 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1333}
1334
1335/*
1336 * Apply a video mode. This will apply the whole register set, including
1337 * the PLL registers, to the card
1338 */
1339void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1340 int regs_only)
1341{
1342 int i;
1343 int primary_mon = PRIMARY_MONITOR(rinfo);
1344
1345 if (nomodeset)
1346 return;
1347
1348 if (!regs_only)
1349 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1350
1351 radeon_fifo_wait(31);
1352 for (i=0; i<10; i++)
1353 OUTREG(common_regs[i].reg, common_regs[i].val);
1354
1355 /* Apply surface registers */
1356 for (i=0; i<8; i++) {
1357 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1358 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1359 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1360 }
1361
1362 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1363 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1364 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1365 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1366 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1367 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1368 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1369 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1370 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1371 OUTREG(CRTC_OFFSET, 0);
1372 OUTREG(CRTC_OFFSET_CNTL, 0);
1373 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1374 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1375
1376 radeon_write_pll_regs(rinfo, mode);
1377
1378 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1379 radeon_fifo_wait(10);
1380 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1381 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1382 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1383 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1384 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1385 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1386 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1387 OUTREG(TMDS_CRC, mode->tmds_crc);
1388 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1389 }
1390
1391 if (!regs_only)
1392 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1393
1394 radeon_fifo_wait(2);
1395 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1396
1397 return;
1398}
1399
1400/*
1401 * Calculate the PLL values for a given mode
1402 */
1403static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1404 unsigned long freq)
1405{
1406 const struct {
1407 int divider;
1408 int bitvalue;
1409 } *post_div,
1410 post_divs[] = {
1411 { 1, 0 },
1412 { 2, 1 },
1413 { 4, 2 },
1414 { 8, 3 },
1415 { 3, 4 },
1416 { 16, 5 },
1417 { 6, 6 },
1418 { 12, 7 },
1419 { 0, 0 },
1420 };
1421 int fb_div, pll_output_freq = 0;
1422 int uses_dvo = 0;
1423
1424 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1425 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1426 * recent than an r(v)100...
1427 */
1428#if 1
1429 /* XXX I had reports of flicker happening with the cinema display
1430 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1431 * this case. This could just be a bandwidth calculation issue, I
1432 * haven't implemented the bandwidth code yet, but in the meantime,
1433 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1434 * I haven't seen a case were were absolutely needed an odd PLL
1435 * divider. I'll find a better fix once I have more infos on the
1436 * real cause of the problem.
1437 */
1438 while (rinfo->has_CRTC2) {
1439 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1440 u32 disp_output_cntl;
1441 int source;
1442
1443 /* FP2 path not enabled */
1444 if ((fp2_gen_cntl & FP2_ON) == 0)
1445 break;
1446 /* Not all chip revs have the same format for this register,
1447 * extract the source selection
1448 */
1449 if (rinfo->family == CHIP_FAMILY_R200 ||
1450 rinfo->family == CHIP_FAMILY_R300 ||
1451 rinfo->family == CHIP_FAMILY_R350 ||
1452 rinfo->family == CHIP_FAMILY_RV350) {
1453 source = (fp2_gen_cntl >> 10) & 0x3;
1454 /* sourced from transform unit, check for transform unit
1455 * own source
1456 */
1457 if (source == 3) {
1458 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1459 source = (disp_output_cntl >> 12) & 0x3;
1460 }
1461 } else
1462 source = (fp2_gen_cntl >> 13) & 0x1;
1463 /* sourced from CRTC2 -> exit */
1464 if (source == 1)
1465 break;
1466
1467 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1468 uses_dvo = 1;
1469 break;
1470 }
1471#else
1472 uses_dvo = 1;
1473#endif
1474 if (freq > rinfo->pll.ppll_max)
1475 freq = rinfo->pll.ppll_max;
1476 if (freq*12 < rinfo->pll.ppll_min)
1477 freq = rinfo->pll.ppll_min / 12;
1478 RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
1479 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1480
1481 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1482 pll_output_freq = post_div->divider * freq;
1483 /* If we output to the DVO port (external TMDS), we don't allow an
1484 * odd PLL divider as those aren't supported on this path
1485 */
1486 if (uses_dvo && (post_div->divider & 1))
1487 continue;
1488 if (pll_output_freq >= rinfo->pll.ppll_min &&
1489 pll_output_freq <= rinfo->pll.ppll_max)
1490 break;
1491 }
1492
1493 /* If we fall through the bottom, try the "default value"
1494 given by the terminal post_div->bitvalue */
1495 if ( !post_div->divider ) {
1496 post_div = &post_divs[post_div->bitvalue];
1497 pll_output_freq = post_div->divider * freq;
1498 }
1499 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1500 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1501 pll_output_freq);
1502
1503 /* If we fall through the bottom, try the "default value"
1504 given by the terminal post_div->bitvalue */
1505 if ( !post_div->divider ) {
1506 post_div = &post_divs[post_div->bitvalue];
1507 pll_output_freq = post_div->divider * freq;
1508 }
1509 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1510 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1511 pll_output_freq);
1512
1513 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1514 rinfo->pll.ref_clk);
1515 regs->ppll_ref_div = rinfo->pll.ref_div;
1516 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1517
1518 RTRACE("post div = 0x%x\n", post_div->bitvalue);
1519 RTRACE("fb_div = 0x%x\n", fb_div);
1520 RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1521}
1522
1523static int radeonfb_set_par(struct fb_info *info)
1524{
1525 struct radeonfb_info *rinfo = info->par;
1526 struct fb_var_screeninfo *mode = &info->var;
1527 struct radeon_regs *newmode;
1528 int hTotal, vTotal, hSyncStart, hSyncEnd,
1529 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1530 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1531 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1532 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1533 int i, freq;
1534 int format = 0;
1535 int nopllcalc = 0;
1536 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1537 int primary_mon = PRIMARY_MONITOR(rinfo);
1538 int depth = var_to_depth(mode);
1539 int use_rmx = 0;
1540
1541 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1542 if (!newmode)
1543 return -ENOMEM;
1544
1545 /* We always want engine to be idle on a mode switch, even
1546 * if we won't actually change the mode
1547 */
1548 radeon_engine_idle();
1549
1550 hSyncStart = mode->xres + mode->right_margin;
1551 hSyncEnd = hSyncStart + mode->hsync_len;
1552 hTotal = hSyncEnd + mode->left_margin;
1553
1554 vSyncStart = mode->yres + mode->lower_margin;
1555 vSyncEnd = vSyncStart + mode->vsync_len;
1556 vTotal = vSyncEnd + mode->upper_margin;
1557 pixClock = mode->pixclock;
1558
1559 sync = mode->sync;
1560 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1561 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1562
1563 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1564 if (rinfo->panel_info.xres < mode->xres)
1565 mode->xres = rinfo->panel_info.xres;
1566 if (rinfo->panel_info.yres < mode->yres)
1567 mode->yres = rinfo->panel_info.yres;
1568
1569 hTotal = mode->xres + rinfo->panel_info.hblank;
1570 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1571 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1572
1573 vTotal = mode->yres + rinfo->panel_info.vblank;
1574 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1575 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1576
1577 h_sync_pol = !rinfo->panel_info.hAct_high;
1578 v_sync_pol = !rinfo->panel_info.vAct_high;
1579
1580 pixClock = 100000000 / rinfo->panel_info.clock;
1581
1582 if (rinfo->panel_info.use_bios_dividers) {
1583 nopllcalc = 1;
1584 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1585 (rinfo->panel_info.post_divider << 16);
1586 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1587 }
1588 }
1589 dotClock = 1000000000 / pixClock;
1590 freq = dotClock / 10; /* x100 */
1591
1592 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1593 hSyncStart, hSyncEnd, hTotal);
1594 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1595 vSyncStart, vSyncEnd, vTotal);
1596
1597 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1598 vsync_wid = vSyncEnd - vSyncStart;
1599 if (hsync_wid == 0)
1600 hsync_wid = 1;
1601 else if (hsync_wid > 0x3f) /* max */
1602 hsync_wid = 0x3f;
1603
1604 if (vsync_wid == 0)
1605 vsync_wid = 1;
1606 else if (vsync_wid > 0x1f) /* max */
1607 vsync_wid = 0x1f;
1608
1609 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1610 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1611
1612 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1613
1614 format = radeon_get_dstbpp(depth);
1615 bytpp = mode->bits_per_pixel >> 3;
1616
1617 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1618 hsync_fudge = hsync_fudge_fp[format-1];
1619 else
1620 hsync_fudge = hsync_adj_tab[format-1];
1621
1622 hsync_start = hSyncStart - 8 + hsync_fudge;
1623
1624 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1625 (format << 8);
1626
1627 /* Clear auto-center etc... */
1628 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1629 newmode->crtc_more_cntl &= 0xfffffff0;
1630
1631 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1632 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1633 if (mirror)
1634 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1635
1636 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1637 CRTC_INTERLACE_EN);
1638 } else {
1639 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1640 CRTC_CRT_ON;
1641 }
1642
1643 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1644 DAC_8BIT_EN;
1645
1646 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1647 (((mode->xres / 8) - 1) << 16));
1648
1649 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1650 (hsync_wid << 16) | (h_sync_pol << 23));
1651
1652 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1653 ((mode->yres - 1) << 16);
1654
1655 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1656 (vsync_wid << 16) | (v_sync_pol << 23));
1657
1658 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1659 /* We first calculate the engine pitch */
1660 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1661 & ~(0x3f)) >> 6;
1662
1663 /* Then, re-multiply it to get the CRTC pitch */
1664 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1665 } else
1666 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1667
1668 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1669
1670 /*
1671 * It looks like recent chips have a problem with SURFACE_CNTL,
1672 * setting SURF_TRANSLATION_DIS completely disables the
1673 * swapper as well, so we leave it unset now.
1674 */
1675 newmode->surface_cntl = 0;
1676
1677#if defined(__BIG_ENDIAN)
1678
1679 /* Setup swapping on both apertures, though we currently
1680 * only use aperture 0, enabling swapper on aperture 1
1681 * won't harm
1682 */
1683 switch (mode->bits_per_pixel) {
1684 case 16:
1685 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1686 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1687 break;
1688 case 24:
1689 case 32:
1690 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1691 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1692 break;
1693 }
1694#endif
1695
1696 /* Clear surface registers */
1697 for (i=0; i<8; i++) {
1698 newmode->surf_lower_bound[i] = 0;
1699 newmode->surf_upper_bound[i] = 0x1f;
1700 newmode->surf_info[i] = 0;
1701 }
1702
1703 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1704 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1705 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1706 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1707
1708 rinfo->bpp = mode->bits_per_pixel;
1709 rinfo->depth = depth;
1710
1711 RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1712 RTRACE("freq = %lu\n", (unsigned long)freq);
1713
1714 /* We use PPLL_DIV_3 */
1715 newmode->clk_cntl_index = 0x300;
1716
1717 /* Calculate PPLL value if necessary */
1718 if (!nopllcalc)
1719 radeon_calc_pll_regs(rinfo, newmode, freq);
1720
1721 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1722
1723 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1724 unsigned int hRatio, vRatio;
1725
1726 if (mode->xres > rinfo->panel_info.xres)
1727 mode->xres = rinfo->panel_info.xres;
1728 if (mode->yres > rinfo->panel_info.yres)
1729 mode->yres = rinfo->panel_info.yres;
1730
1731 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1732 << HORZ_PANEL_SHIFT);
1733 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1734 << VERT_PANEL_SHIFT);
1735
1736 if (mode->xres != rinfo->panel_info.xres) {
1737 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1738 rinfo->panel_info.xres);
1739 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1740 (newmode->fp_horz_stretch &
1741 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1742 HORZ_AUTO_RATIO_INC)));
1743 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1744 HORZ_STRETCH_ENABLE);
1745 use_rmx = 1;
1746 }
1747 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1748
1749 if (mode->yres != rinfo->panel_info.yres) {
1750 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1751 rinfo->panel_info.yres);
1752 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1753 (newmode->fp_vert_stretch &
1754 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1755 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1756 VERT_STRETCH_ENABLE);
1757 use_rmx = 1;
1758 }
1759 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1760
1761 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1762 ~(FP_SEL_CRTC2 |
1763 FP_RMX_HVSYNC_CONTROL_EN |
1764 FP_DFP_SYNC_SEL |
1765 FP_CRT_SYNC_SEL |
1766 FP_CRTC_LOCK_8DOT |
1767 FP_USE_SHADOW_EN |
1768 FP_CRTC_USE_SHADOW_VEND |
1769 FP_CRT_SYNC_ALT));
1770
1771 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1772 FP_CRTC_DONT_SHADOW_HEND |
1773 FP_PANEL_FORMAT);
1774
1775 if (IS_R300_VARIANT(rinfo) ||
1776 (rinfo->family == CHIP_FAMILY_R200)) {
1777 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1778 if (use_rmx)
1779 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1780 else
1781 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1782 } else
1783 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1784
1785 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1786 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1787 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1788 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1789
1790 if (primary_mon == MT_LCD) {
1791 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1792 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1793 } else {
1794 /* DFP */
1795 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1796 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1797 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1798 if (IS_R300_VARIANT(rinfo) ||
1799 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1800 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1801 else
1802 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1803 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1804 }
1805
1806 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1807 (((mode->xres / 8) - 1) << 16));
1808 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1809 ((mode->yres - 1) << 16);
1810 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1811 (hsync_wid << 16) | (h_sync_pol << 23));
1812 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1813 (vsync_wid << 16) | (v_sync_pol << 23));
1814 }
1815
1816 /* do it! */
1817 if (!rinfo->asleep) {
1818 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1819 radeon_write_mode (rinfo, newmode, 0);
1820 /* (re)initialize the engine */
1821 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1822 radeonfb_engine_init (rinfo);
1823 }
1824 /* Update fix */
1825 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1826 info->fix.line_length = rinfo->pitch*64;
1827 else
1828 info->fix.line_length = mode->xres_virtual
1829 * ((mode->bits_per_pixel + 1) / 8);
1830 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1831 : FB_VISUAL_DIRECTCOLOR;
1832
1833#ifdef CONFIG_BOOTX_TEXT
1834 /* Update debug text engine */
1835 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1836 rinfo->depth, info->fix.line_length);
1837#endif
1838
1839 kfree(newmode);
1840 return 0;
1841}
1842
1843
1844static struct fb_ops radeonfb_ops = {
1845 .owner = THIS_MODULE,
1846 .fb_check_var = radeonfb_check_var,
1847 .fb_set_par = radeonfb_set_par,
1848 .fb_setcolreg = radeonfb_setcolreg,
Benjamin Herrenschmidt71494372005-05-01 08:59:22 -07001849 .fb_setcmap = radeonfb_setcmap,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001850 .fb_pan_display = radeonfb_pan_display,
1851 .fb_blank = radeonfb_blank,
1852 .fb_ioctl = radeonfb_ioctl,
1853 .fb_sync = radeonfb_sync,
1854 .fb_fillrect = radeonfb_fillrect,
1855 .fb_copyarea = radeonfb_copyarea,
1856 .fb_imageblit = radeonfb_imageblit,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001857};
1858
1859
1860static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1861{
1862 struct fb_info *info = rinfo->info;
1863
1864 info->par = rinfo;
1865 info->pseudo_palette = rinfo->pseudo_palette;
1866 info->flags = FBINFO_DEFAULT
1867 | FBINFO_HWACCEL_COPYAREA
1868 | FBINFO_HWACCEL_FILLRECT
1869 | FBINFO_HWACCEL_XPAN
1870 | FBINFO_HWACCEL_YPAN;
1871 info->fbops = &radeonfb_ops;
1872 info->screen_base = rinfo->fb_base;
1873 info->screen_size = rinfo->mapped_vram;
1874 /* Fill fix common fields */
1875 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1876 info->fix.smem_start = rinfo->fb_base_phys;
1877 info->fix.smem_len = rinfo->video_ram;
1878 info->fix.type = FB_TYPE_PACKED_PIXELS;
1879 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1880 info->fix.xpanstep = 8;
1881 info->fix.ypanstep = 1;
1882 info->fix.ywrapstep = 0;
1883 info->fix.type_aux = 0;
1884 info->fix.mmio_start = rinfo->mmio_base_phys;
1885 info->fix.mmio_len = RADEON_REGSIZE;
1886 info->fix.accel = FB_ACCEL_ATI_RADEON;
1887
1888 fb_alloc_cmap(&info->cmap, 256, 0);
1889
1890 if (noaccel)
1891 info->flags |= FBINFO_HWACCEL_DISABLED;
1892
1893 return 0;
1894}
1895
Linus Torvalds1da177e2005-04-16 15:20:36 -07001896/*
1897 * This reconfigure the card's internal memory map. In theory, we'd like
1898 * to setup the card's memory at the same address as it's PCI bus address,
1899 * and the AGP aperture right after that so that system RAM on 32 bits
1900 * machines at least, is directly accessible. However, doing so would
1901 * conflict with the current XFree drivers...
1902 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1903 * on the proper way to set this up and duplicate this here. In the meantime,
1904 * I put the card's memory at 0 in card space and AGP at some random high
1905 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1906 */
1907#ifdef CONFIG_PPC_OF
1908#undef SET_MC_FB_FROM_APERTURE
1909static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1910{
1911 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1912 u32 save_crtc_ext_cntl;
1913 u32 aper_base, aper_size;
1914 u32 agp_base;
1915
1916 /* First, we disable display to avoid interfering */
1917 if (rinfo->has_CRTC2) {
1918 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1919 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1920 }
1921 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1922 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1923
1924 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1925 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1926 mdelay(100);
1927
1928 aper_base = INREG(CONFIG_APER_0_BASE);
1929 aper_size = INREG(CONFIG_APER_SIZE);
1930
1931#ifdef SET_MC_FB_FROM_APERTURE
1932 /* Set framebuffer to be at the same address as set in PCI BAR */
1933 OUTREG(MC_FB_LOCATION,
1934 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1935 rinfo->fb_local_base = aper_base;
1936#else
1937 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1938 rinfo->fb_local_base = 0;
1939#endif
1940 agp_base = aper_base + aper_size;
1941 if (agp_base & 0xf0000000)
1942 agp_base = (aper_base | 0x0fffffff) + 1;
1943
1944 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1945 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1946 * always the case on PPCs afaik.
1947 */
1948#ifdef SET_MC_FB_FROM_APERTURE
1949 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1950#else
1951 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1952#endif
1953
1954 /* Fixup the display base addresses & engine offsets while we
1955 * are at it as well
1956 */
1957#ifdef SET_MC_FB_FROM_APERTURE
1958 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1959 if (rinfo->has_CRTC2)
1960 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1961 OUTREG(OV0_BASE_ADDR, aper_base);
1962#else
1963 OUTREG(DISPLAY_BASE_ADDR, 0);
1964 if (rinfo->has_CRTC2)
1965 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1966 OUTREG(OV0_BASE_ADDR, 0);
1967#endif
1968 mdelay(100);
1969
1970 /* Restore display settings */
1971 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1972 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1973 if (rinfo->has_CRTC2)
1974 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1975
1976 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1977 aper_base,
1978 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1979 0xffff0000 | (agp_base >> 16));
1980}
1981#endif /* CONFIG_PPC_OF */
1982
1983
1984static void radeon_identify_vram(struct radeonfb_info *rinfo)
1985{
1986 u32 tmp;
1987
1988 /* framebuffer size */
1989 if ((rinfo->family == CHIP_FAMILY_RS100) ||
1990 (rinfo->family == CHIP_FAMILY_RS200) ||
1991 (rinfo->family == CHIP_FAMILY_RS300)) {
1992 u32 tom = INREG(NB_TOM);
1993 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
1994
1995 radeon_fifo_wait(6);
1996 OUTREG(MC_FB_LOCATION, tom);
1997 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
1998 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
1999 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2000
2001 /* This is supposed to fix the crtc2 noise problem. */
2002 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2003
2004 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2005 (rinfo->family == CHIP_FAMILY_RS200)) {
2006 /* This is to workaround the asic bug for RMX, some versions
2007 of BIOS dosen't have this register initialized correctly.
2008 */
2009 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2010 ~CRTC_H_CUTOFF_ACTIVE_EN);
2011 }
2012 } else {
2013 tmp = INREG(CONFIG_MEMSIZE);
2014 }
2015
2016 /* mem size is bits [28:0], mask off the rest */
2017 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2018
2019 /*
2020 * Hack to get around some busted production M6's
2021 * reporting no ram
2022 */
2023 if (rinfo->video_ram == 0) {
2024 switch (rinfo->pdev->device) {
2025 case PCI_CHIP_RADEON_LY:
2026 case PCI_CHIP_RADEON_LZ:
2027 rinfo->video_ram = 8192 * 1024;
2028 break;
2029 default:
2030 break;
2031 }
2032 }
2033
2034
2035 /*
2036 * Now try to identify VRAM type
2037 */
2038 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2039 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2040 rinfo->vram_ddr = 1;
2041 else
2042 rinfo->vram_ddr = 0;
2043
2044 tmp = INREG(MEM_CNTL);
2045 if (IS_R300_VARIANT(rinfo)) {
2046 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2047 switch (tmp) {
2048 case 0: rinfo->vram_width = 64; break;
2049 case 1: rinfo->vram_width = 128; break;
2050 case 2: rinfo->vram_width = 256; break;
2051 default: rinfo->vram_width = 128; break;
2052 }
2053 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2054 (rinfo->family == CHIP_FAMILY_RS100) ||
2055 (rinfo->family == CHIP_FAMILY_RS200)){
2056 if (tmp & RV100_MEM_HALF_MODE)
2057 rinfo->vram_width = 32;
2058 else
2059 rinfo->vram_width = 64;
2060 } else {
2061 if (tmp & MEM_NUM_CHANNELS_MASK)
2062 rinfo->vram_width = 128;
2063 else
2064 rinfo->vram_width = 64;
2065 }
2066
2067 /* This may not be correct, as some cards can have half of channel disabled
2068 * ToDo: identify these cases
2069 */
2070
2071 RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2072 pci_name(rinfo->pdev),
2073 rinfo->video_ram / 1024,
2074 rinfo->vram_ddr ? "DDR" : "SDRAM",
2075 rinfo->vram_width);
2076}
2077
2078/*
2079 * Sysfs
2080 */
2081
2082static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2083{
2084 if (off > EDID_LENGTH)
2085 return 0;
2086
2087 if (off + count > EDID_LENGTH)
2088 count = EDID_LENGTH - off;
2089
2090 memcpy(buf, edid + off, count);
2091
2092 return count;
2093}
2094
2095
2096static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)
2097{
2098 struct device *dev = container_of(kobj, struct device, kobj);
2099 struct pci_dev *pdev = to_pci_dev(dev);
2100 struct fb_info *info = pci_get_drvdata(pdev);
2101 struct radeonfb_info *rinfo = info->par;
2102
2103 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2104}
2105
2106
2107static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)
2108{
2109 struct device *dev = container_of(kobj, struct device, kobj);
2110 struct pci_dev *pdev = to_pci_dev(dev);
2111 struct fb_info *info = pci_get_drvdata(pdev);
2112 struct radeonfb_info *rinfo = info->par;
2113
2114 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2115}
2116
2117static struct bin_attribute edid1_attr = {
2118 .attr = {
2119 .name = "edid1",
2120 .owner = THIS_MODULE,
2121 .mode = 0444,
2122 },
2123 .size = EDID_LENGTH,
2124 .read = radeon_show_edid1,
2125};
2126
2127static struct bin_attribute edid2_attr = {
2128 .attr = {
2129 .name = "edid2",
2130 .owner = THIS_MODULE,
2131 .mode = 0444,
2132 },
2133 .size = EDID_LENGTH,
2134 .read = radeon_show_edid2,
2135};
2136
2137
Randy Dunlap246846f2006-04-18 22:22:10 -07002138static int __devinit radeonfb_pci_register (struct pci_dev *pdev,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002139 const struct pci_device_id *ent)
2140{
2141 struct fb_info *info;
2142 struct radeonfb_info *rinfo;
2143 int ret;
2144
2145 RTRACE("radeonfb_pci_register BEGIN\n");
2146
2147 /* Enable device in PCI config */
2148 ret = pci_enable_device(pdev);
2149 if (ret < 0) {
2150 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2151 pci_name(pdev));
2152 goto err_out;
2153 }
2154
2155 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2156 if (!info) {
2157 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2158 pci_name(pdev));
2159 ret = -ENOMEM;
2160 goto err_disable;
2161 }
2162 rinfo = info->par;
2163 rinfo->info = info;
2164 rinfo->pdev = pdev;
2165
2166 spin_lock_init(&rinfo->reg_lock);
2167 init_timer(&rinfo->lvds_timer);
2168 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2169 rinfo->lvds_timer.data = (unsigned long)rinfo;
2170
2171 strcpy(rinfo->name, "ATI Radeon XX ");
2172 rinfo->name[11] = ent->device >> 8;
2173 rinfo->name[12] = ent->device & 0xFF;
2174 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2175 rinfo->chipset = pdev->device;
2176 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2177 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2178 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2179
2180 /* Set base addrs */
2181 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2182 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2183
2184 /* request the mem regions */
Daniel Burcaw5251bff2005-09-09 13:04:59 -07002185 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002186 if (ret < 0) {
Daniel Burcaw5251bff2005-09-09 13:04:59 -07002187 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2188 pci_name(rinfo->pdev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002189 goto err_release_fb;
2190 }
2191
Daniel Burcaw5251bff2005-09-09 13:04:59 -07002192 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2193 if (ret < 0) {
2194 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2195 pci_name(rinfo->pdev));
2196 goto err_release_pci0;
2197 }
2198
Linus Torvalds1da177e2005-04-16 15:20:36 -07002199 /* map the regions */
2200 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2201 if (!rinfo->mmio_base) {
Daniel Burcaw5251bff2005-09-09 13:04:59 -07002202 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2203 pci_name(rinfo->pdev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002204 ret = -EIO;
Daniel Burcaw5251bff2005-09-09 13:04:59 -07002205 goto err_release_pci2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002206 }
2207
2208 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2209
2210 /*
2211 * Check for errata
2212 */
2213 rinfo->errata = 0;
2214 if (rinfo->family == CHIP_FAMILY_R300 &&
2215 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2216 == CFG_ATI_REV_A11)
2217 rinfo->errata |= CHIP_ERRATA_R300_CG;
2218
2219 if (rinfo->family == CHIP_FAMILY_RV200 ||
2220 rinfo->family == CHIP_FAMILY_RS200)
2221 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2222
2223 if (rinfo->family == CHIP_FAMILY_RV100 ||
2224 rinfo->family == CHIP_FAMILY_RS100 ||
2225 rinfo->family == CHIP_FAMILY_RS200)
2226 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2227
2228#ifdef CONFIG_PPC_OF
2229 /* On PPC, we obtain the OF device-node pointer to the firmware
2230 * data for this chip
2231 */
2232 rinfo->of_node = pci_device_to_OF_node(pdev);
2233 if (rinfo->of_node == NULL)
2234 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2235 pci_name(rinfo->pdev));
2236
2237 /* On PPC, the firmware sets up a memory mapping that tends
2238 * to cause lockups when enabling the engine. We reconfigure
2239 * the card internal memory mappings properly
2240 */
2241 fixup_memory_mappings(rinfo);
2242#endif /* CONFIG_PPC_OF */
2243
2244 /* Get VRAM size and type */
2245 radeon_identify_vram(rinfo);
2246
2247 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2248
2249 do {
2250 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2251 rinfo->mapped_vram);
2252 } while ( rinfo->fb_base == 0 &&
2253 ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
2254
Benjamin Herrenschmidt8d5f7b42005-06-11 09:45:30 +10002255 if (rinfo->fb_base == NULL) {
2256 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2257 pci_name(rinfo->pdev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002258 ret = -EIO;
2259 goto err_unmap_rom;
2260 }
2261
2262 RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2263 rinfo->mapped_vram/1024);
2264
2265 /*
Matt Mackall4a4efbd2006-01-03 13:27:11 +01002266 * Map the BIOS ROM if any and retrieve PLL parameters from
Linus Torvalds1da177e2005-04-16 15:20:36 -07002267 * the BIOS. We skip that on mobility chips as the real panel
2268 * values we need aren't in the ROM but in the BIOS image in
2269 * memory. This is definitely not the best meacnism though,
2270 * we really need the arch code to tell us which is the "primary"
2271 * video adapter to use the memory image (or better, the arch
2272 * should provide us a copy of the BIOS image to shield us from
2273 * archs who would store that elsewhere and/or could initialize
2274 * more than one adapter during boot).
2275 */
2276 if (!rinfo->is_mobility)
2277 radeon_map_ROM(rinfo, pdev);
2278
2279 /*
2280 * On x86, the primary display on laptop may have it's BIOS
2281 * ROM elsewhere, try to locate it at the legacy memory hole.
2282 * We probably need to make sure this is the primary display,
2283 * but that is difficult without some arch support.
2284 */
2285#ifdef CONFIG_X86
2286 if (rinfo->bios_seg == NULL)
2287 radeon_find_mem_vbios(rinfo);
2288#endif
2289
2290 /* If both above failed, try the BIOS ROM again for mobility
2291 * chips
2292 */
2293 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2294 radeon_map_ROM(rinfo, pdev);
2295
2296 /* Get informations about the board's PLL */
2297 radeon_get_pllinfo(rinfo);
2298
2299#ifdef CONFIG_FB_RADEON_I2C
2300 /* Register I2C bus */
2301 radeon_create_i2c_busses(rinfo);
2302#endif
2303
2304 /* set all the vital stuff */
2305 radeon_set_fbinfo (rinfo);
2306
2307 /* Probe screen types */
2308 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2309
2310 /* Build mode list, check out panel native model */
2311 radeon_check_modes(rinfo, mode_option);
2312
2313 /* Register some sysfs stuff (should be done better) */
2314 if (rinfo->mon1_EDID)
2315 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2316 if (rinfo->mon2_EDID)
2317 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2318
2319 /* save current mode regs before we switch into the new one
2320 * so we can restore this upon __exit
2321 */
2322 radeon_save_state (rinfo, &rinfo->init_state);
2323 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2324
2325 /* Setup Power Management capabilities */
2326 if (default_dynclk < -1) {
2327 /* -2 is special: means ON on mobility chips and do not
2328 * change on others
2329 */
2330 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1);
2331 } else
2332 radeonfb_pm_init(rinfo, default_dynclk);
2333
2334 pci_set_drvdata(pdev, info);
2335
2336 /* Register with fbdev layer */
2337 ret = register_framebuffer(info);
2338 if (ret < 0) {
2339 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2340 pci_name(rinfo->pdev));
2341 goto err_unmap_fb;
2342 }
2343
2344#ifdef CONFIG_MTRR
2345 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2346 rinfo->video_ram,
2347 MTRR_TYPE_WRCOMB, 1);
2348#endif
2349
Michael Hanselmann5474c122006-06-25 05:47:08 -07002350 radeonfb_bl_init(rinfo);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002351
2352 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2353
2354 if (rinfo->bios_seg)
2355 radeon_unmap_ROM(rinfo, pdev);
2356 RTRACE("radeonfb_pci_register END\n");
2357
2358 return 0;
2359err_unmap_fb:
2360 iounmap(rinfo->fb_base);
2361err_unmap_rom:
2362 kfree(rinfo->mon1_EDID);
2363 kfree(rinfo->mon2_EDID);
2364 if (rinfo->mon1_modedb)
2365 fb_destroy_modedb(rinfo->mon1_modedb);
2366 fb_dealloc_cmap(&info->cmap);
2367#ifdef CONFIG_FB_RADEON_I2C
2368 radeon_delete_i2c_busses(rinfo);
2369#endif
2370 if (rinfo->bios_seg)
2371 radeon_unmap_ROM(rinfo, pdev);
2372 iounmap(rinfo->mmio_base);
Daniel Burcaw5251bff2005-09-09 13:04:59 -07002373err_release_pci2:
2374 pci_release_region(pdev, 2);
2375err_release_pci0:
2376 pci_release_region(pdev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002377err_release_fb:
Daniel Burcaw5251bff2005-09-09 13:04:59 -07002378 framebuffer_release(info);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002379err_disable:
Linus Torvalds1da177e2005-04-16 15:20:36 -07002380err_out:
2381 return ret;
2382}
2383
2384
2385
2386static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2387{
2388 struct fb_info *info = pci_get_drvdata(pdev);
2389 struct radeonfb_info *rinfo = info->par;
2390
2391 if (!rinfo)
2392 return;
Michael Hanselmann5474c122006-06-25 05:47:08 -07002393
2394 radeonfb_bl_exit(rinfo);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002395 radeonfb_pm_exit(rinfo);
2396
Jon Smirl3ca34fc2005-07-27 11:46:05 -07002397 if (rinfo->mon1_EDID)
2398 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2399 if (rinfo->mon2_EDID)
2400 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2401
Linus Torvalds1da177e2005-04-16 15:20:36 -07002402#if 0
2403 /* restore original state
2404 *
2405 * Doesn't quite work yet, I suspect if we come from a legacy
2406 * VGA mode (or worse, text mode), we need to do some VGA black
2407 * magic here that I know nothing about. --BenH
2408 */
2409 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2410 #endif
2411
2412 del_timer_sync(&rinfo->lvds_timer);
2413
2414#ifdef CONFIG_MTRR
2415 if (rinfo->mtrr_hdl >= 0)
2416 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2417#endif
2418
2419 unregister_framebuffer(info);
2420
2421 iounmap(rinfo->mmio_base);
2422 iounmap(rinfo->fb_base);
2423
Daniel Burcaw5251bff2005-09-09 13:04:59 -07002424 pci_release_region(pdev, 2);
2425 pci_release_region(pdev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002426
2427 kfree(rinfo->mon1_EDID);
2428 kfree(rinfo->mon2_EDID);
2429 if (rinfo->mon1_modedb)
2430 fb_destroy_modedb(rinfo->mon1_modedb);
2431#ifdef CONFIG_FB_RADEON_I2C
2432 radeon_delete_i2c_busses(rinfo);
2433#endif
2434 fb_dealloc_cmap(&info->cmap);
2435 framebuffer_release(info);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002436}
2437
2438
2439static struct pci_driver radeonfb_driver = {
2440 .name = "radeonfb",
2441 .id_table = radeonfb_pci_table,
2442 .probe = radeonfb_pci_register,
2443 .remove = __devexit_p(radeonfb_pci_unregister),
2444#ifdef CONFIG_PM
2445 .suspend = radeonfb_pci_suspend,
2446 .resume = radeonfb_pci_resume,
2447#endif /* CONFIG_PM */
2448};
2449
2450#ifndef MODULE
2451static int __init radeonfb_setup (char *options)
2452{
2453 char *this_opt;
2454
2455 if (!options || !*options)
2456 return 0;
2457
2458 while ((this_opt = strsep (&options, ",")) != NULL) {
2459 if (!*this_opt)
2460 continue;
2461
2462 if (!strncmp(this_opt, "noaccel", 7)) {
2463 noaccel = 1;
2464 } else if (!strncmp(this_opt, "mirror", 6)) {
2465 mirror = 1;
2466 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2467 force_dfp = 1;
2468 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2469 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2470#ifdef CONFIG_MTRR
2471 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2472 nomtrr = 1;
2473#endif
2474 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2475 nomodeset = 1;
2476 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2477 force_measure_pll = 1;
2478 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2479 ignore_edid = 1;
2480 } else
2481 mode_option = this_opt;
2482 }
2483 return 0;
2484}
2485#endif /* MODULE */
2486
2487static int __init radeonfb_init (void)
2488{
2489#ifndef MODULE
2490 char *option = NULL;
2491
2492 if (fb_get_options("radeonfb", &option))
2493 return -ENODEV;
2494 radeonfb_setup(option);
2495#endif
2496 return pci_register_driver (&radeonfb_driver);
2497}
2498
2499
2500static void __exit radeonfb_exit (void)
2501{
2502 pci_unregister_driver (&radeonfb_driver);
2503}
2504
2505module_init(radeonfb_init);
2506module_exit(radeonfb_exit);
2507
2508MODULE_AUTHOR("Ani Joshi");
2509MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2510MODULE_LICENSE("GPL");
2511module_param(noaccel, bool, 0);
2512module_param(default_dynclk, int, 0);
2513MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2514MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2515module_param(nomodeset, bool, 0);
2516MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2517module_param(mirror, bool, 0);
2518MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2519module_param(force_dfp, bool, 0);
2520MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2521module_param(ignore_edid, bool, 0);
2522MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2523module_param(monitor_layout, charp, 0);
2524MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2525module_param(force_measure_pll, bool, 0);
2526MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2527#ifdef CONFIG_MTRR
2528module_param(nomtrr, bool, 0);
2529MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2530#endif
2531module_param(panel_yres, int, 0);
2532MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2533module_param(mode_option, charp, 0);
2534MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");