Bjorn Helgaas | 8cfab3c | 2018-01-26 12:50:27 -0600 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 2 | /* |
Bjorn Helgaas | 96291d5 | 2017-09-01 16:35:50 -0500 | [diff] [blame] | 3 | * Synopsys DesignWare PCIe host controller driver |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 4 | * |
| 5 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. |
| 6 | * http://www.samsung.com |
| 7 | * |
| 8 | * Author: Jingoo Han <jg1.han@samsung.com> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 9 | */ |
| 10 | |
Joao Pinto | 886bc5c | 2016-03-10 14:44:35 -0600 | [diff] [blame] | 11 | #include <linux/delay.h> |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 12 | #include <linux/of.h> |
| 13 | #include <linux/types.h> |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 14 | |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 15 | #include "pcie-designware.h" |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 16 | |
Joao Pinto | dac29e6 | 2016-03-10 14:44:44 -0600 | [diff] [blame] | 17 | /* PCIe Port Logic registers */ |
| 18 | #define PLR_OFFSET 0x700 |
| 19 | #define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c) |
Jisheng Zhang | 01c0767 | 2016-08-17 15:57:37 -0500 | [diff] [blame] | 20 | #define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4) |
| 21 | #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29) |
Joao Pinto | dac29e6 | 2016-03-10 14:44:44 -0600 | [diff] [blame] | 22 | |
Kishon Vijay Abraham I | 19ce01cc | 2017-02-15 18:48:12 +0530 | [diff] [blame] | 23 | int dw_pcie_read(void __iomem *addr, int size, u32 *val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 24 | { |
Gabriele Paoloni | b6b18f5 | 2015-10-08 14:27:53 -0500 | [diff] [blame] | 25 | if ((uintptr_t)addr & (size - 1)) { |
| 26 | *val = 0; |
| 27 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 28 | } |
| 29 | |
Kishon Vijay Abraham I | 314fc85 | 2017-02-15 18:48:16 +0530 | [diff] [blame] | 30 | if (size == 4) { |
Gabriele Paoloni | c003ca9 | 2015-10-08 14:27:43 -0500 | [diff] [blame] | 31 | *val = readl(addr); |
Kishon Vijay Abraham I | 314fc85 | 2017-02-15 18:48:16 +0530 | [diff] [blame] | 32 | } else if (size == 2) { |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 33 | *val = readw(addr); |
Kishon Vijay Abraham I | 314fc85 | 2017-02-15 18:48:16 +0530 | [diff] [blame] | 34 | } else if (size == 1) { |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 35 | *val = readb(addr); |
Kishon Vijay Abraham I | 314fc85 | 2017-02-15 18:48:16 +0530 | [diff] [blame] | 36 | } else { |
Gabriele Paoloni | c003ca9 | 2015-10-08 14:27:43 -0500 | [diff] [blame] | 37 | *val = 0; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 38 | return PCIBIOS_BAD_REGISTER_NUMBER; |
Gabriele Paoloni | c003ca9 | 2015-10-08 14:27:43 -0500 | [diff] [blame] | 39 | } |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 40 | |
| 41 | return PCIBIOS_SUCCESSFUL; |
| 42 | } |
| 43 | |
Kishon Vijay Abraham I | 19ce01cc | 2017-02-15 18:48:12 +0530 | [diff] [blame] | 44 | int dw_pcie_write(void __iomem *addr, int size, u32 val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 45 | { |
Gabriele Paoloni | b6b18f5 | 2015-10-08 14:27:53 -0500 | [diff] [blame] | 46 | if ((uintptr_t)addr & (size - 1)) |
| 47 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 48 | |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 49 | if (size == 4) |
| 50 | writel(val, addr); |
| 51 | else if (size == 2) |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 52 | writew(val, addr); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 53 | else if (size == 1) |
Gabriele Paoloni | 4c45852 | 2015-10-08 14:27:48 -0500 | [diff] [blame] | 54 | writeb(val, addr); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 55 | else |
| 56 | return PCIBIOS_BAD_REGISTER_NUMBER; |
| 57 | |
| 58 | return PCIBIOS_SUCCESSFUL; |
| 59 | } |
| 60 | |
Kishon Vijay Abraham I | a509d7d | 2017-03-13 19:13:26 +0530 | [diff] [blame] | 61 | u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, |
| 62 | size_t size) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 63 | { |
Kishon Vijay Abraham I | a509d7d | 2017-03-13 19:13:26 +0530 | [diff] [blame] | 64 | int ret; |
| 65 | u32 val; |
Bjorn Helgaas | 446fc23 | 2016-08-17 14:17:58 -0500 | [diff] [blame] | 66 | |
Kishon Vijay Abraham I | a509d7d | 2017-03-13 19:13:26 +0530 | [diff] [blame] | 67 | if (pci->ops->read_dbi) |
| 68 | return pci->ops->read_dbi(pci, base, reg, size); |
| 69 | |
| 70 | ret = dw_pcie_read(base + reg, size, &val); |
| 71 | if (ret) |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 72 | dev_err(pci->dev, "Read DBI address failed\n"); |
Kishon Vijay Abraham I | a509d7d | 2017-03-13 19:13:26 +0530 | [diff] [blame] | 73 | |
| 74 | return val; |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 75 | } |
| 76 | |
Kishon Vijay Abraham I | a509d7d | 2017-03-13 19:13:26 +0530 | [diff] [blame] | 77 | void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, |
| 78 | size_t size, u32 val) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 79 | { |
Kishon Vijay Abraham I | a509d7d | 2017-03-13 19:13:26 +0530 | [diff] [blame] | 80 | int ret; |
| 81 | |
| 82 | if (pci->ops->write_dbi) { |
| 83 | pci->ops->write_dbi(pci, base, reg, size, val); |
| 84 | return; |
| 85 | } |
| 86 | |
| 87 | ret = dw_pcie_write(base + reg, size, val); |
| 88 | if (ret) |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 89 | dev_err(pci->dev, "Write DBI address failed\n"); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 90 | } |
| 91 | |
Kishon Vijay Abraham I | edd45e3 | 2017-03-13 19:13:27 +0530 | [diff] [blame] | 92 | static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg) |
Joao Pinto | a0601a4 | 2016-08-10 11:02:39 +0100 | [diff] [blame] | 93 | { |
| 94 | u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); |
| 95 | |
Kishon Vijay Abraham I | 442ec4c | 2017-02-15 18:48:14 +0530 | [diff] [blame] | 96 | return dw_pcie_readl_dbi(pci, offset + reg); |
Joao Pinto | a0601a4 | 2016-08-10 11:02:39 +0100 | [diff] [blame] | 97 | } |
| 98 | |
Kishon Vijay Abraham I | edd45e3 | 2017-03-13 19:13:27 +0530 | [diff] [blame] | 99 | static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg, |
| 100 | u32 val) |
Joao Pinto | a0601a4 | 2016-08-10 11:02:39 +0100 | [diff] [blame] | 101 | { |
| 102 | u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); |
| 103 | |
Kishon Vijay Abraham I | 442ec4c | 2017-02-15 18:48:14 +0530 | [diff] [blame] | 104 | dw_pcie_writel_dbi(pci, offset + reg, val); |
Joao Pinto | a0601a4 | 2016-08-10 11:02:39 +0100 | [diff] [blame] | 105 | } |
| 106 | |
Carlos Palminha | 684a3a9 | 2017-07-17 14:13:34 +0100 | [diff] [blame] | 107 | static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index, |
| 108 | int type, u64 cpu_addr, |
| 109 | u64 pci_addr, u32 size) |
Kishon Vijay Abraham I | edd45e3 | 2017-03-13 19:13:27 +0530 | [diff] [blame] | 110 | { |
| 111 | u32 retries, val; |
| 112 | |
| 113 | dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, |
| 114 | lower_32_bits(cpu_addr)); |
| 115 | dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, |
| 116 | upper_32_bits(cpu_addr)); |
| 117 | dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, |
| 118 | lower_32_bits(cpu_addr + size - 1)); |
| 119 | dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, |
| 120 | lower_32_bits(pci_addr)); |
| 121 | dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, |
| 122 | upper_32_bits(pci_addr)); |
| 123 | dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, |
| 124 | type); |
| 125 | dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, |
| 126 | PCIE_ATU_ENABLE); |
| 127 | |
| 128 | /* |
| 129 | * Make sure ATU enable takes effect before any subsequent config |
| 130 | * and I/O accesses. |
| 131 | */ |
| 132 | for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { |
| 133 | val = dw_pcie_readl_ob_unroll(pci, index, |
| 134 | PCIE_ATU_UNR_REGION_CTRL2); |
| 135 | if (val & PCIE_ATU_ENABLE) |
| 136 | return; |
| 137 | |
Jisheng Zhang | 9024143 | 2018-09-20 16:32:52 -0500 | [diff] [blame] | 138 | mdelay(LINK_WAIT_IATU); |
Kishon Vijay Abraham I | edd45e3 | 2017-03-13 19:13:27 +0530 | [diff] [blame] | 139 | } |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 140 | dev_err(pci->dev, "Outbound iATU is not being enabled\n"); |
Kishon Vijay Abraham I | edd45e3 | 2017-03-13 19:13:27 +0530 | [diff] [blame] | 141 | } |
| 142 | |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 143 | void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, |
| 144 | u64 cpu_addr, u64 pci_addr, u32 size) |
Jisheng Zhang | 63503c8 | 2015-04-30 16:22:28 +0800 | [diff] [blame] | 145 | { |
Joao Pinto | d8bbeb3 | 2016-08-17 13:26:07 -0500 | [diff] [blame] | 146 | u32 retries, val; |
Stanimir Varbanov | 17209df | 2015-12-18 14:38:55 +0200 | [diff] [blame] | 147 | |
Kishon Vijay Abraham I | a660083 | 2017-03-13 19:13:22 +0530 | [diff] [blame] | 148 | if (pci->ops->cpu_addr_fixup) |
Niklas Cassel | b6900ae | 2017-12-20 00:29:36 +0100 | [diff] [blame] | 149 | cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); |
Kishon Vijay Abraham I | a660083 | 2017-03-13 19:13:22 +0530 | [diff] [blame] | 150 | |
Kishon Vijay Abraham I | 442ec4c | 2017-02-15 18:48:14 +0530 | [diff] [blame] | 151 | if (pci->iatu_unroll_enabled) { |
Kishon Vijay Abraham I | edd45e3 | 2017-03-13 19:13:27 +0530 | [diff] [blame] | 152 | dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr, |
| 153 | pci_addr, size); |
| 154 | return; |
Joao Pinto | a0601a4 | 2016-08-10 11:02:39 +0100 | [diff] [blame] | 155 | } |
Stanimir Varbanov | 17209df | 2015-12-18 14:38:55 +0200 | [diff] [blame] | 156 | |
Kishon Vijay Abraham I | edd45e3 | 2017-03-13 19:13:27 +0530 | [diff] [blame] | 157 | dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, |
| 158 | PCIE_ATU_REGION_OUTBOUND | index); |
| 159 | dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE, |
| 160 | lower_32_bits(cpu_addr)); |
| 161 | dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE, |
| 162 | upper_32_bits(cpu_addr)); |
| 163 | dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT, |
| 164 | lower_32_bits(cpu_addr + size - 1)); |
| 165 | dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, |
| 166 | lower_32_bits(pci_addr)); |
| 167 | dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, |
| 168 | upper_32_bits(pci_addr)); |
| 169 | dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type); |
| 170 | dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE); |
| 171 | |
Stanimir Varbanov | 17209df | 2015-12-18 14:38:55 +0200 | [diff] [blame] | 172 | /* |
| 173 | * Make sure ATU enable takes effect before any subsequent config |
| 174 | * and I/O accesses. |
| 175 | */ |
Joao Pinto | d8bbeb3 | 2016-08-17 13:26:07 -0500 | [diff] [blame] | 176 | for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { |
Kishon Vijay Abraham I | edd45e3 | 2017-03-13 19:13:27 +0530 | [diff] [blame] | 177 | val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); |
Jisheng Zhang | e9be4d7 | 2017-07-18 14:48:21 +0800 | [diff] [blame] | 178 | if (val & PCIE_ATU_ENABLE) |
Joao Pinto | d8bbeb3 | 2016-08-17 13:26:07 -0500 | [diff] [blame] | 179 | return; |
| 180 | |
Jisheng Zhang | 9024143 | 2018-09-20 16:32:52 -0500 | [diff] [blame] | 181 | mdelay(LINK_WAIT_IATU); |
Joao Pinto | d8bbeb3 | 2016-08-17 13:26:07 -0500 | [diff] [blame] | 182 | } |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 183 | dev_err(pci->dev, "Outbound iATU is not being enabled\n"); |
Jisheng Zhang | 63503c8 | 2015-04-30 16:22:28 +0800 | [diff] [blame] | 184 | } |
| 185 | |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 186 | static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg) |
| 187 | { |
| 188 | u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index); |
| 189 | |
| 190 | return dw_pcie_readl_dbi(pci, offset + reg); |
| 191 | } |
| 192 | |
| 193 | static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg, |
| 194 | u32 val) |
| 195 | { |
| 196 | u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index); |
| 197 | |
| 198 | dw_pcie_writel_dbi(pci, offset + reg, val); |
| 199 | } |
| 200 | |
Carlos Palminha | 684a3a9 | 2017-07-17 14:13:34 +0100 | [diff] [blame] | 201 | static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index, |
| 202 | int bar, u64 cpu_addr, |
| 203 | enum dw_pcie_as_type as_type) |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 204 | { |
| 205 | int type; |
| 206 | u32 retries, val; |
| 207 | |
| 208 | dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, |
| 209 | lower_32_bits(cpu_addr)); |
| 210 | dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, |
| 211 | upper_32_bits(cpu_addr)); |
| 212 | |
| 213 | switch (as_type) { |
| 214 | case DW_PCIE_AS_MEM: |
| 215 | type = PCIE_ATU_TYPE_MEM; |
| 216 | break; |
| 217 | case DW_PCIE_AS_IO: |
| 218 | type = PCIE_ATU_TYPE_IO; |
| 219 | break; |
| 220 | default: |
| 221 | return -EINVAL; |
| 222 | } |
| 223 | |
| 224 | dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type); |
| 225 | dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, |
| 226 | PCIE_ATU_ENABLE | |
| 227 | PCIE_ATU_BAR_MODE_ENABLE | (bar << 8)); |
| 228 | |
| 229 | /* |
| 230 | * Make sure ATU enable takes effect before any subsequent config |
| 231 | * and I/O accesses. |
| 232 | */ |
| 233 | for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { |
| 234 | val = dw_pcie_readl_ib_unroll(pci, index, |
| 235 | PCIE_ATU_UNR_REGION_CTRL2); |
| 236 | if (val & PCIE_ATU_ENABLE) |
| 237 | return 0; |
| 238 | |
Jisheng Zhang | 9024143 | 2018-09-20 16:32:52 -0500 | [diff] [blame] | 239 | mdelay(LINK_WAIT_IATU); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 240 | } |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 241 | dev_err(pci->dev, "Inbound iATU is not being enabled\n"); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 242 | |
| 243 | return -EBUSY; |
| 244 | } |
| 245 | |
| 246 | int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar, |
| 247 | u64 cpu_addr, enum dw_pcie_as_type as_type) |
| 248 | { |
| 249 | int type; |
| 250 | u32 retries, val; |
| 251 | |
| 252 | if (pci->iatu_unroll_enabled) |
| 253 | return dw_pcie_prog_inbound_atu_unroll(pci, index, bar, |
| 254 | cpu_addr, as_type); |
| 255 | |
| 256 | dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND | |
| 257 | index); |
| 258 | dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr)); |
| 259 | dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr)); |
| 260 | |
| 261 | switch (as_type) { |
| 262 | case DW_PCIE_AS_MEM: |
| 263 | type = PCIE_ATU_TYPE_MEM; |
| 264 | break; |
| 265 | case DW_PCIE_AS_IO: |
| 266 | type = PCIE_ATU_TYPE_IO; |
| 267 | break; |
| 268 | default: |
| 269 | return -EINVAL; |
| 270 | } |
| 271 | |
| 272 | dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type); |
| 273 | dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE |
| 274 | | PCIE_ATU_BAR_MODE_ENABLE | (bar << 8)); |
| 275 | |
| 276 | /* |
| 277 | * Make sure ATU enable takes effect before any subsequent config |
| 278 | * and I/O accesses. |
| 279 | */ |
| 280 | for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { |
| 281 | val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); |
| 282 | if (val & PCIE_ATU_ENABLE) |
| 283 | return 0; |
| 284 | |
Jisheng Zhang | 9024143 | 2018-09-20 16:32:52 -0500 | [diff] [blame] | 285 | mdelay(LINK_WAIT_IATU); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 286 | } |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 287 | dev_err(pci->dev, "Inbound iATU is not being enabled\n"); |
Kishon Vijay Abraham I | f8aed6e | 2017-03-27 15:15:05 +0530 | [diff] [blame] | 288 | |
| 289 | return -EBUSY; |
| 290 | } |
| 291 | |
| 292 | void dw_pcie_disable_atu(struct dw_pcie *pci, int index, |
| 293 | enum dw_pcie_region_type type) |
| 294 | { |
| 295 | int region; |
| 296 | |
| 297 | switch (type) { |
| 298 | case DW_PCIE_REGION_INBOUND: |
| 299 | region = PCIE_ATU_REGION_INBOUND; |
| 300 | break; |
| 301 | case DW_PCIE_REGION_OUTBOUND: |
| 302 | region = PCIE_ATU_REGION_OUTBOUND; |
| 303 | break; |
| 304 | default: |
| 305 | return; |
| 306 | } |
| 307 | |
| 308 | dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index); |
| 309 | dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~PCIE_ATU_ENABLE); |
| 310 | } |
| 311 | |
Kishon Vijay Abraham I | 442ec4c | 2017-02-15 18:48:14 +0530 | [diff] [blame] | 312 | int dw_pcie_wait_for_link(struct dw_pcie *pci) |
Joao Pinto | 886bc5c | 2016-03-10 14:44:35 -0600 | [diff] [blame] | 313 | { |
| 314 | int retries; |
| 315 | |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 316 | /* Check if the link is up or not */ |
Joao Pinto | 886bc5c | 2016-03-10 14:44:35 -0600 | [diff] [blame] | 317 | for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { |
Kishon Vijay Abraham I | 442ec4c | 2017-02-15 18:48:14 +0530 | [diff] [blame] | 318 | if (dw_pcie_link_up(pci)) { |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 319 | dev_info(pci->dev, "Link up\n"); |
Joao Pinto | 886bc5c | 2016-03-10 14:44:35 -0600 | [diff] [blame] | 320 | return 0; |
| 321 | } |
| 322 | usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); |
| 323 | } |
| 324 | |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 325 | dev_err(pci->dev, "Phy link never came up\n"); |
Joao Pinto | 886bc5c | 2016-03-10 14:44:35 -0600 | [diff] [blame] | 326 | |
| 327 | return -ETIMEDOUT; |
| 328 | } |
| 329 | |
Kishon Vijay Abraham I | 442ec4c | 2017-02-15 18:48:14 +0530 | [diff] [blame] | 330 | int dw_pcie_link_up(struct dw_pcie *pci) |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 331 | { |
Joao Pinto | dac29e6 | 2016-03-10 14:44:44 -0600 | [diff] [blame] | 332 | u32 val; |
| 333 | |
Kishon Vijay Abraham I | 442ec4c | 2017-02-15 18:48:14 +0530 | [diff] [blame] | 334 | if (pci->ops->link_up) |
| 335 | return pci->ops->link_up(pci); |
Bjorn Helgaas | 116a489 | 2016-01-05 15:48:11 -0600 | [diff] [blame] | 336 | |
Kishon Vijay Abraham I | 442ec4c | 2017-02-15 18:48:14 +0530 | [diff] [blame] | 337 | val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1); |
Jisheng Zhang | 01c0767 | 2016-08-17 15:57:37 -0500 | [diff] [blame] | 338 | return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) && |
| 339 | (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))); |
Jingoo Han | 340cba6 | 2013-06-21 16:24:54 +0900 | [diff] [blame] | 340 | } |
| 341 | |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 342 | void dw_pcie_setup(struct dw_pcie *pci) |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 343 | { |
Kishon Vijay Abraham I | 5f334db | 2017-02-15 18:48:15 +0530 | [diff] [blame] | 344 | int ret; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 345 | u32 val; |
Kishon Vijay Abraham I | feb85d9 | 2017-02-15 18:48:17 +0530 | [diff] [blame] | 346 | u32 lanes; |
Kishon Vijay Abraham I | 5f334db | 2017-02-15 18:48:15 +0530 | [diff] [blame] | 347 | struct device *dev = pci->dev; |
| 348 | struct device_node *np = dev->of_node; |
| 349 | |
| 350 | ret = of_property_read_u32(np, "num-lanes", &lanes); |
| 351 | if (ret) |
| 352 | lanes = 0; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 353 | |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 354 | /* Set the number of lanes */ |
Kishon Vijay Abraham I | 442ec4c | 2017-02-15 18:48:14 +0530 | [diff] [blame] | 355 | val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 356 | val &= ~PORT_LINK_MODE_MASK; |
Kishon Vijay Abraham I | 5f334db | 2017-02-15 18:48:15 +0530 | [diff] [blame] | 357 | switch (lanes) { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 358 | case 1: |
| 359 | val |= PORT_LINK_MODE_1_LANES; |
| 360 | break; |
| 361 | case 2: |
| 362 | val |= PORT_LINK_MODE_2_LANES; |
| 363 | break; |
| 364 | case 4: |
| 365 | val |= PORT_LINK_MODE_4_LANES; |
| 366 | break; |
Zhou Wang | 5b0f073 | 2015-05-13 14:44:34 +0800 | [diff] [blame] | 367 | case 8: |
| 368 | val |= PORT_LINK_MODE_8_LANES; |
| 369 | break; |
Gabriele Paoloni | 907fce0 | 2015-09-29 00:03:10 +0800 | [diff] [blame] | 370 | default: |
Kishon Vijay Abraham I | 5f334db | 2017-02-15 18:48:15 +0530 | [diff] [blame] | 371 | dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes); |
Gabriele Paoloni | 907fce0 | 2015-09-29 00:03:10 +0800 | [diff] [blame] | 372 | return; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 373 | } |
Kishon Vijay Abraham I | 442ec4c | 2017-02-15 18:48:14 +0530 | [diff] [blame] | 374 | dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 375 | |
Gustavo Pimentel | b4a8a51 | 2018-05-14 16:09:48 +0100 | [diff] [blame] | 376 | /* Set link width speed control register */ |
Kishon Vijay Abraham I | 442ec4c | 2017-02-15 18:48:14 +0530 | [diff] [blame] | 377 | val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 378 | val &= ~PORT_LOGIC_LINK_WIDTH_MASK; |
Kishon Vijay Abraham I | 5f334db | 2017-02-15 18:48:15 +0530 | [diff] [blame] | 379 | switch (lanes) { |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 380 | case 1: |
| 381 | val |= PORT_LOGIC_LINK_WIDTH_1_LANES; |
| 382 | break; |
| 383 | case 2: |
| 384 | val |= PORT_LOGIC_LINK_WIDTH_2_LANES; |
| 385 | break; |
| 386 | case 4: |
| 387 | val |= PORT_LOGIC_LINK_WIDTH_4_LANES; |
| 388 | break; |
Zhou Wang | 5b0f073 | 2015-05-13 14:44:34 +0800 | [diff] [blame] | 389 | case 8: |
| 390 | val |= PORT_LOGIC_LINK_WIDTH_8_LANES; |
| 391 | break; |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 392 | } |
Kishon Vijay Abraham I | 442ec4c | 2017-02-15 18:48:14 +0530 | [diff] [blame] | 393 | dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); |
Jingoo Han | 4b1ced8 | 2013-07-31 17:14:10 +0900 | [diff] [blame] | 394 | } |