Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 2 | #ifndef DW_SPI_HEADER_H |
| 3 | #define DW_SPI_HEADER_H |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 4 | |
Serge Semin | cc760f3 | 2020-09-20 14:28:53 +0300 | [diff] [blame] | 5 | #include <linux/bits.h> |
Serge Semin | bdbdf0f | 2020-05-29 16:11:52 +0300 | [diff] [blame] | 6 | #include <linux/completion.h> |
Serge Semin | 8378449 | 2020-05-29 16:12:04 +0300 | [diff] [blame] | 7 | #include <linux/debugfs.h> |
Andy Shevchenko | e62a15d | 2020-05-06 18:30:21 +0300 | [diff] [blame] | 8 | #include <linux/irqreturn.h> |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 9 | #include <linux/io.h> |
Jiri Slaby | 46165a3d | 2011-03-18 10:41:17 +0100 | [diff] [blame] | 10 | #include <linux/scatterlist.h> |
Serge Semin | 6423207 | 2020-10-08 02:55:06 +0300 | [diff] [blame] | 11 | #include <linux/spi/spi-mem.h> |
Damien Le Moal | a51acc2 | 2020-12-06 10:18:16 +0900 | [diff] [blame] | 12 | #include <linux/bitfield.h> |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 13 | |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 14 | /* Register offsets */ |
Wan Ahmad Zainie | 299cb65 | 2020-05-05 21:06:12 +0800 | [diff] [blame] | 15 | #define DW_SPI_CTRLR0 0x00 |
| 16 | #define DW_SPI_CTRLR1 0x04 |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 17 | #define DW_SPI_SSIENR 0x08 |
| 18 | #define DW_SPI_MWCR 0x0c |
| 19 | #define DW_SPI_SER 0x10 |
| 20 | #define DW_SPI_BAUDR 0x14 |
Wan Ahmad Zainie | 299cb65 | 2020-05-05 21:06:12 +0800 | [diff] [blame] | 21 | #define DW_SPI_TXFTLR 0x18 |
| 22 | #define DW_SPI_RXFTLR 0x1c |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 23 | #define DW_SPI_TXFLR 0x20 |
| 24 | #define DW_SPI_RXFLR 0x24 |
| 25 | #define DW_SPI_SR 0x28 |
| 26 | #define DW_SPI_IMR 0x2c |
| 27 | #define DW_SPI_ISR 0x30 |
| 28 | #define DW_SPI_RISR 0x34 |
| 29 | #define DW_SPI_TXOICR 0x38 |
| 30 | #define DW_SPI_RXOICR 0x3c |
| 31 | #define DW_SPI_RXUICR 0x40 |
| 32 | #define DW_SPI_MSTICR 0x44 |
| 33 | #define DW_SPI_ICR 0x48 |
| 34 | #define DW_SPI_DMACR 0x4c |
| 35 | #define DW_SPI_DMATDLR 0x50 |
| 36 | #define DW_SPI_DMARDLR 0x54 |
| 37 | #define DW_SPI_IDR 0x58 |
| 38 | #define DW_SPI_VERSION 0x5c |
| 39 | #define DW_SPI_DR 0x60 |
Lars Povlsen | bac70b5 | 2020-08-24 22:30:05 +0200 | [diff] [blame] | 40 | #define DW_SPI_RX_SAMPLE_DLY 0xf0 |
Talel Shenhar | f2d7047 | 2018-10-11 14:20:07 +0300 | [diff] [blame] | 41 | #define DW_SPI_CS_OVERRIDE 0xf4 |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 42 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 43 | /* Bit fields in CTRLR0 */ |
| 44 | #define SPI_DFS_OFFSET 0 |
Damien Le Moal | a51acc2 | 2020-12-06 10:18:16 +0900 | [diff] [blame] | 45 | #define SPI_DFS_MASK GENMASK(3, 0) |
| 46 | #define SPI_DFS32_OFFSET 16 |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 47 | |
| 48 | #define SPI_FRF_OFFSET 4 |
| 49 | #define SPI_FRF_SPI 0x0 |
| 50 | #define SPI_FRF_SSP 0x1 |
| 51 | #define SPI_FRF_MICROWIRE 0x2 |
| 52 | #define SPI_FRF_RESV 0x3 |
| 53 | |
| 54 | #define SPI_MODE_OFFSET 6 |
| 55 | #define SPI_SCPH_OFFSET 6 |
| 56 | #define SPI_SCOL_OFFSET 7 |
Feng Tang | e3e55ff | 2010-09-07 15:52:06 +0800 | [diff] [blame] | 57 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 58 | #define SPI_TMOD_OFFSET 8 |
Feng Tang | e3e55ff | 2010-09-07 15:52:06 +0800 | [diff] [blame] | 59 | #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 60 | #define SPI_TMOD_TR 0x0 /* xmit & recv */ |
| 61 | #define SPI_TMOD_TO 0x1 /* xmit only */ |
| 62 | #define SPI_TMOD_RO 0x2 /* recv only */ |
| 63 | #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ |
| 64 | |
| 65 | #define SPI_SLVOE_OFFSET 10 |
| 66 | #define SPI_SRL_OFFSET 11 |
| 67 | #define SPI_CFS_OFFSET 12 |
| 68 | |
Wan Ahmad Zainie | e539f43 | 2020-05-05 21:06:14 +0800 | [diff] [blame] | 69 | /* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */ |
| 70 | #define DWC_SSI_CTRLR0_SRL_OFFSET 13 |
| 71 | #define DWC_SSI_CTRLR0_TMOD_OFFSET 10 |
| 72 | #define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10) |
| 73 | #define DWC_SSI_CTRLR0_SCPOL_OFFSET 9 |
| 74 | #define DWC_SSI_CTRLR0_SCPH_OFFSET 8 |
| 75 | #define DWC_SSI_CTRLR0_FRF_OFFSET 6 |
| 76 | #define DWC_SSI_CTRLR0_DFS_OFFSET 0 |
| 77 | |
Serge Semin | ffb7ca5 | 2020-09-20 14:28:54 +0300 | [diff] [blame] | 78 | /* |
| 79 | * For Keem Bay, CTRLR0[31] is used to select controller mode. |
| 80 | * 0: SSI is slave |
| 81 | * 1: SSI is master |
| 82 | */ |
| 83 | #define DWC_SSI_CTRLR0_KEEMBAY_MST BIT(31) |
| 84 | |
Serge Semin | 6423207 | 2020-10-08 02:55:06 +0300 | [diff] [blame] | 85 | /* Bit fields in CTRLR1 */ |
| 86 | #define SPI_NDF_MASK GENMASK(15, 0) |
| 87 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 88 | /* Bit fields in SR, 7 bits */ |
| 89 | #define SR_MASK 0x7f /* cover 7 bits */ |
| 90 | #define SR_BUSY (1 << 0) |
| 91 | #define SR_TF_NOT_FULL (1 << 1) |
| 92 | #define SR_TF_EMPT (1 << 2) |
| 93 | #define SR_RF_NOT_EMPT (1 << 3) |
| 94 | #define SR_RF_FULL (1 << 4) |
| 95 | #define SR_TX_ERR (1 << 5) |
| 96 | #define SR_DCOL (1 << 6) |
| 97 | |
| 98 | /* Bit fields in ISR, IMR, RISR, 7 bits */ |
| 99 | #define SPI_INT_TXEI (1 << 0) |
| 100 | #define SPI_INT_TXOI (1 << 1) |
| 101 | #define SPI_INT_RXUI (1 << 2) |
| 102 | #define SPI_INT_RXOI (1 << 3) |
| 103 | #define SPI_INT_RXFI (1 << 4) |
| 104 | #define SPI_INT_MSTI (1 << 5) |
| 105 | |
Andy Shevchenko | 15ee3be | 2014-10-02 16:31:07 +0300 | [diff] [blame] | 106 | /* Bit fields in DMACR */ |
| 107 | #define SPI_DMA_RDMAE (1 << 0) |
| 108 | #define SPI_DMA_TDMAE (1 << 1) |
| 109 | |
Serge Semin | cf75bae | 2020-10-08 02:55:04 +0300 | [diff] [blame] | 110 | #define SPI_WAIT_RETRIES 5 |
Serge Semin | 6423207 | 2020-10-08 02:55:06 +0300 | [diff] [blame] | 111 | #define SPI_BUF_SIZE \ |
| 112 | (sizeof_field(struct spi_mem_op, cmd.opcode) + \ |
| 113 | sizeof_field(struct spi_mem_op, addr.val) + 256) |
| 114 | #define SPI_GET_BYTE(_val, _idx) \ |
| 115 | ((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff) |
Serge Semin | cf75bae | 2020-10-08 02:55:04 +0300 | [diff] [blame] | 116 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 117 | enum dw_ssi_type { |
| 118 | SSI_MOTO_SPI = 0, |
| 119 | SSI_TI_SSP, |
| 120 | SSI_NS_MICROWIRE, |
| 121 | }; |
| 122 | |
Serge Semin | cc760f3 | 2020-09-20 14:28:53 +0300 | [diff] [blame] | 123 | /* DW SPI capabilities */ |
| 124 | #define DW_SPI_CAP_CS_OVERRIDE BIT(0) |
Serge Semin | ffb7ca5 | 2020-09-20 14:28:54 +0300 | [diff] [blame] | 125 | #define DW_SPI_CAP_KEEMBAY_MST BIT(1) |
Serge Semin | d6bbd11 | 2020-10-08 02:54:51 +0300 | [diff] [blame] | 126 | #define DW_SPI_CAP_DWC_SSI BIT(2) |
Damien Le Moal | a51acc2 | 2020-12-06 10:18:16 +0900 | [diff] [blame] | 127 | #define DW_SPI_CAP_DFS32 BIT(3) |
Serge Semin | cc760f3 | 2020-09-20 14:28:53 +0300 | [diff] [blame] | 128 | |
Serge Semin | 3ff60c6 | 2020-10-08 02:54:56 +0300 | [diff] [blame] | 129 | /* Slave spi_transfer/spi_mem_op related */ |
| 130 | struct dw_spi_cfg { |
| 131 | u8 tmode; |
| 132 | u8 dfs; |
| 133 | u32 ndf; |
| 134 | u32 freq; |
| 135 | }; |
| 136 | |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 137 | struct dw_spi; |
| 138 | struct dw_spi_dma_ops { |
Andy Shevchenko | 6370aba | 2020-05-06 18:30:24 +0300 | [diff] [blame] | 139 | int (*dma_init)(struct device *dev, struct dw_spi *dws); |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 140 | void (*dma_exit)(struct dw_spi *dws); |
Andy Shevchenko | f89a6d8 | 2015-03-09 16:48:49 +0200 | [diff] [blame] | 141 | int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer); |
Jarkko Nikula | 721483e | 2018-02-01 17:17:29 +0200 | [diff] [blame] | 142 | bool (*can_dma)(struct spi_controller *master, struct spi_device *spi, |
Andy Shevchenko | f89a6d8 | 2015-03-09 16:48:49 +0200 | [diff] [blame] | 143 | struct spi_transfer *xfer); |
| 144 | int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer); |
Andy Shevchenko | 4d5ac1e | 2015-03-09 16:48:48 +0200 | [diff] [blame] | 145 | void (*dma_stop)(struct dw_spi *dws); |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 146 | }; |
| 147 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 148 | struct dw_spi { |
Jarkko Nikula | 721483e | 2018-02-01 17:17:29 +0200 | [diff] [blame] | 149 | struct spi_controller *master; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 150 | |
| 151 | void __iomem *regs; |
| 152 | unsigned long paddr; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 153 | int irq; |
Feng Tang | 552e450 | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 154 | u32 fifo_len; /* depth of the FIFO buffer */ |
Damien Le Moal | a51acc2 | 2020-12-06 10:18:16 +0900 | [diff] [blame] | 155 | unsigned int dfs_offset; /* CTRLR0 DFS field offset */ |
Serge Semin | 84ecaf4 | 2020-10-08 02:55:07 +0300 | [diff] [blame] | 156 | u32 max_mem_freq; /* max mem-ops bus freq */ |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 157 | u32 max_freq; /* max bus freq supported */ |
| 158 | |
Serge Semin | cc760f3 | 2020-09-20 14:28:53 +0300 | [diff] [blame] | 159 | u32 caps; /* DW SPI capabilities */ |
| 160 | |
Michael van der Westhuizen | c4fe57f | 2015-08-18 22:21:53 +0200 | [diff] [blame] | 161 | u32 reg_io_width; /* DR I/O width in bytes */ |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 162 | u16 bus_num; |
| 163 | u16 num_cs; /* supported slave numbers */ |
Alexandre Belloni | 62dbbae | 2018-07-17 16:23:11 +0200 | [diff] [blame] | 164 | void (*set_cs)(struct spi_device *spi, bool enable); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 165 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 166 | /* Current message transfer state info */ |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 167 | void *tx; |
Serge Semin | 8dedbea | 2020-10-08 02:54:57 +0300 | [diff] [blame] | 168 | unsigned int tx_len; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 169 | void *rx; |
Serge Semin | 8dedbea | 2020-10-08 02:54:57 +0300 | [diff] [blame] | 170 | unsigned int rx_len; |
Serge Semin | 6423207 | 2020-10-08 02:55:06 +0300 | [diff] [blame] | 171 | u8 buf[SPI_BUF_SIZE]; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 172 | int dma_mapped; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 173 | u8 n_bytes; /* current is a 1/2 bytes op */ |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 174 | irqreturn_t (*transfer_handler)(struct dw_spi *dws); |
Matthias Seidel | 13b1030 | 2016-09-04 02:04:49 +0200 | [diff] [blame] | 175 | u32 current_freq; /* frequency in hz */ |
Lars Povlsen | bac70b5 | 2020-08-24 22:30:05 +0200 | [diff] [blame] | 176 | u32 cur_rx_sample_dly; |
| 177 | u32 def_rx_sample_dly_ns; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 178 | |
Serge Semin | 6423207 | 2020-10-08 02:55:06 +0300 | [diff] [blame] | 179 | /* Custom memory operations */ |
| 180 | struct spi_controller_mem_ops mem_ops; |
| 181 | |
Andy Shevchenko | f89a6d8 | 2015-03-09 16:48:49 +0200 | [diff] [blame] | 182 | /* DMA info */ |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 183 | struct dma_chan *txchan; |
Serge Semin | 0b2b665 | 2020-05-29 16:11:56 +0300 | [diff] [blame] | 184 | u32 txburst; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 185 | struct dma_chan *rxchan; |
Serge Semin | 0b2b665 | 2020-05-29 16:11:56 +0300 | [diff] [blame] | 186 | u32 rxburst; |
Serge Semin | ad4fe12 | 2020-09-20 14:23:22 +0300 | [diff] [blame] | 187 | u32 dma_sg_burst; |
Andy Shevchenko | 30c8eb5 | 2014-10-28 18:25:02 +0200 | [diff] [blame] | 188 | unsigned long dma_chan_busy; |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 189 | dma_addr_t dma_addr; /* phy address of the Data register */ |
Julia Lawall | 4fe338c | 2015-11-28 15:09:38 +0100 | [diff] [blame] | 190 | const struct dw_spi_dma_ops *dma_ops; |
Serge Semin | bdbdf0f | 2020-05-29 16:11:52 +0300 | [diff] [blame] | 191 | struct completion dma_completion; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 192 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 193 | #ifdef CONFIG_DEBUG_FS |
| 194 | struct dentry *debugfs; |
Serge Semin | 8378449 | 2020-05-29 16:12:04 +0300 | [diff] [blame] | 195 | struct debugfs_regset32 regset; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 196 | #endif |
| 197 | }; |
| 198 | |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 199 | static inline u32 dw_readl(struct dw_spi *dws, u32 offset) |
| 200 | { |
| 201 | return __raw_readl(dws->regs + offset); |
| 202 | } |
| 203 | |
| 204 | static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) |
| 205 | { |
| 206 | __raw_writel(val, dws->regs + offset); |
| 207 | } |
| 208 | |
Michael van der Westhuizen | c4fe57f | 2015-08-18 22:21:53 +0200 | [diff] [blame] | 209 | static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) |
| 210 | { |
| 211 | switch (dws->reg_io_width) { |
| 212 | case 2: |
Serge Semin | 7e31cea | 2020-09-20 14:28:51 +0300 | [diff] [blame] | 213 | return readw_relaxed(dws->regs + offset); |
Michael van der Westhuizen | c4fe57f | 2015-08-18 22:21:53 +0200 | [diff] [blame] | 214 | case 4: |
| 215 | default: |
Serge Semin | 7e31cea | 2020-09-20 14:28:51 +0300 | [diff] [blame] | 216 | return readl_relaxed(dws->regs + offset); |
Michael van der Westhuizen | c4fe57f | 2015-08-18 22:21:53 +0200 | [diff] [blame] | 217 | } |
| 218 | } |
| 219 | |
| 220 | static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) |
| 221 | { |
| 222 | switch (dws->reg_io_width) { |
| 223 | case 2: |
Serge Semin | 7e31cea | 2020-09-20 14:28:51 +0300 | [diff] [blame] | 224 | writew_relaxed(val, dws->regs + offset); |
Michael van der Westhuizen | c4fe57f | 2015-08-18 22:21:53 +0200 | [diff] [blame] | 225 | break; |
| 226 | case 4: |
| 227 | default: |
Serge Semin | 7e31cea | 2020-09-20 14:28:51 +0300 | [diff] [blame] | 228 | writel_relaxed(val, dws->regs + offset); |
Michael van der Westhuizen | c4fe57f | 2015-08-18 22:21:53 +0200 | [diff] [blame] | 229 | break; |
| 230 | } |
| 231 | } |
| 232 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 233 | static inline void spi_enable_chip(struct dw_spi *dws, int enable) |
| 234 | { |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 235 | dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 236 | } |
| 237 | |
| 238 | static inline void spi_set_clk(struct dw_spi *dws, u16 div) |
| 239 | { |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 240 | dw_writel(dws, DW_SPI_BAUDR, div); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 241 | } |
| 242 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 243 | /* Disable IRQ bits */ |
| 244 | static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) |
| 245 | { |
| 246 | u32 new_mask; |
| 247 | |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 248 | new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask; |
| 249 | dw_writel(dws, DW_SPI_IMR, new_mask); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 250 | } |
| 251 | |
| 252 | /* Enable IRQ bits */ |
| 253 | static inline void spi_umask_intr(struct dw_spi *dws, u32 mask) |
| 254 | { |
| 255 | u32 new_mask; |
| 256 | |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 257 | new_mask = dw_readl(dws, DW_SPI_IMR) | mask; |
| 258 | dw_writel(dws, DW_SPI_IMR, new_mask); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 259 | } |
| 260 | |
| 261 | /* |
Serge Semin | fbddc98 | 2020-10-08 02:55:02 +0300 | [diff] [blame] | 262 | * This disables the SPI controller, interrupts, clears the interrupts status |
| 263 | * and CS, then re-enables the controller back. Transmit and receive FIFO |
| 264 | * buffers are cleared when the device is disabled. |
Andy Shevchenko | 45746e8 | 2015-03-02 14:58:55 +0200 | [diff] [blame] | 265 | */ |
| 266 | static inline void spi_reset_chip(struct dw_spi *dws) |
| 267 | { |
| 268 | spi_enable_chip(dws, 0); |
| 269 | spi_mask_intr(dws, 0xff); |
Serge Semin | a128f6e | 2020-09-20 14:28:49 +0300 | [diff] [blame] | 270 | dw_readl(dws, DW_SPI_ICR); |
Serge Semin | fbddc98 | 2020-10-08 02:55:02 +0300 | [diff] [blame] | 271 | dw_writel(dws, DW_SPI_SER, 0); |
Andy Shevchenko | 45746e8 | 2015-03-02 14:58:55 +0200 | [diff] [blame] | 272 | spi_enable_chip(dws, 1); |
| 273 | } |
| 274 | |
Andy Shevchenko | 1cc3f14 | 2015-10-14 23:12:23 +0300 | [diff] [blame] | 275 | static inline void spi_shutdown_chip(struct dw_spi *dws) |
| 276 | { |
| 277 | spi_enable_chip(dws, 0); |
| 278 | spi_set_clk(dws, 0); |
| 279 | } |
| 280 | |
Alexandre Belloni | c79bdbb | 2018-07-27 21:53:54 +0200 | [diff] [blame] | 281 | extern void dw_spi_set_cs(struct spi_device *spi, bool enable); |
Serge Semin | 3ff60c6 | 2020-10-08 02:54:56 +0300 | [diff] [blame] | 282 | extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, |
| 283 | struct dw_spi_cfg *cfg); |
Serge Semin | bf64b66 | 2020-10-08 02:55:05 +0300 | [diff] [blame] | 284 | extern int dw_spi_check_status(struct dw_spi *dws, bool raw); |
Baruch Siach | 04f421e | 2013-12-30 20:30:44 +0200 | [diff] [blame] | 285 | extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 286 | extern void dw_spi_remove_host(struct dw_spi *dws); |
| 287 | extern int dw_spi_suspend_host(struct dw_spi *dws); |
| 288 | extern int dw_spi_resume_host(struct dw_spi *dws); |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 289 | |
Serge Semin | 6c710c0 | 2020-05-29 16:11:59 +0300 | [diff] [blame] | 290 | #ifdef CONFIG_SPI_DW_DMA |
| 291 | |
Serge Semin | 5778441 | 2020-05-29 16:12:02 +0300 | [diff] [blame] | 292 | extern void dw_spi_dma_setup_mfld(struct dw_spi *dws); |
| 293 | extern void dw_spi_dma_setup_generic(struct dw_spi *dws); |
Serge Semin | 6c710c0 | 2020-05-29 16:11:59 +0300 | [diff] [blame] | 294 | |
| 295 | #else |
| 296 | |
Serge Semin | 5778441 | 2020-05-29 16:12:02 +0300 | [diff] [blame] | 297 | static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {} |
| 298 | static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {} |
Serge Semin | 6c710c0 | 2020-05-29 16:11:59 +0300 | [diff] [blame] | 299 | |
| 300 | #endif /* !CONFIG_SPI_DW_DMA */ |
Andy Shevchenko | 37aa8aa | 2020-05-06 18:30:23 +0300 | [diff] [blame] | 301 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 302 | #endif /* DW_SPI_HEADER_H */ |