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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001/* SPDX-License-Identifier: GPL-2.0 */
Feng Tange24c7452009-12-14 14:20:22 -08002#ifndef DW_SPI_HEADER_H
3#define DW_SPI_HEADER_H
Feng Tang7063c0d2010-12-24 13:59:11 +08004
Serge Semincc760f32020-09-20 14:28:53 +03005#include <linux/bits.h>
Serge Seminbdbdf0f2020-05-29 16:11:52 +03006#include <linux/completion.h>
Serge Semin83784492020-05-29 16:12:04 +03007#include <linux/debugfs.h>
Andy Shevchenkoe62a15d2020-05-06 18:30:21 +03008#include <linux/irqreturn.h>
Feng Tange24c7452009-12-14 14:20:22 -08009#include <linux/io.h>
Jiri Slaby46165a3d2011-03-18 10:41:17 +010010#include <linux/scatterlist.h>
Serge Semin64232072020-10-08 02:55:06 +030011#include <linux/spi/spi-mem.h>
Damien Le Moala51acc22020-12-06 10:18:16 +090012#include <linux/bitfield.h>
Feng Tange24c7452009-12-14 14:20:22 -080013
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070014/* Register offsets */
Wan Ahmad Zainie299cb652020-05-05 21:06:12 +080015#define DW_SPI_CTRLR0 0x00
16#define DW_SPI_CTRLR1 0x04
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070017#define DW_SPI_SSIENR 0x08
18#define DW_SPI_MWCR 0x0c
19#define DW_SPI_SER 0x10
20#define DW_SPI_BAUDR 0x14
Wan Ahmad Zainie299cb652020-05-05 21:06:12 +080021#define DW_SPI_TXFTLR 0x18
22#define DW_SPI_RXFTLR 0x1c
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070023#define DW_SPI_TXFLR 0x20
24#define DW_SPI_RXFLR 0x24
25#define DW_SPI_SR 0x28
26#define DW_SPI_IMR 0x2c
27#define DW_SPI_ISR 0x30
28#define DW_SPI_RISR 0x34
29#define DW_SPI_TXOICR 0x38
30#define DW_SPI_RXOICR 0x3c
31#define DW_SPI_RXUICR 0x40
32#define DW_SPI_MSTICR 0x44
33#define DW_SPI_ICR 0x48
34#define DW_SPI_DMACR 0x4c
35#define DW_SPI_DMATDLR 0x50
36#define DW_SPI_DMARDLR 0x54
37#define DW_SPI_IDR 0x58
38#define DW_SPI_VERSION 0x5c
39#define DW_SPI_DR 0x60
Lars Povlsenbac70b52020-08-24 22:30:05 +020040#define DW_SPI_RX_SAMPLE_DLY 0xf0
Talel Shenharf2d70472018-10-11 14:20:07 +030041#define DW_SPI_CS_OVERRIDE 0xf4
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -070042
Feng Tange24c7452009-12-14 14:20:22 -080043/* Bit fields in CTRLR0 */
44#define SPI_DFS_OFFSET 0
Damien Le Moala51acc22020-12-06 10:18:16 +090045#define SPI_DFS_MASK GENMASK(3, 0)
46#define SPI_DFS32_OFFSET 16
Feng Tange24c7452009-12-14 14:20:22 -080047
48#define SPI_FRF_OFFSET 4
49#define SPI_FRF_SPI 0x0
50#define SPI_FRF_SSP 0x1
51#define SPI_FRF_MICROWIRE 0x2
52#define SPI_FRF_RESV 0x3
53
54#define SPI_MODE_OFFSET 6
55#define SPI_SCPH_OFFSET 6
56#define SPI_SCOL_OFFSET 7
Feng Tange3e55ff2010-09-07 15:52:06 +080057
Feng Tange24c7452009-12-14 14:20:22 -080058#define SPI_TMOD_OFFSET 8
Feng Tange3e55ff2010-09-07 15:52:06 +080059#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
Feng Tange24c7452009-12-14 14:20:22 -080060#define SPI_TMOD_TR 0x0 /* xmit & recv */
61#define SPI_TMOD_TO 0x1 /* xmit only */
62#define SPI_TMOD_RO 0x2 /* recv only */
63#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
64
65#define SPI_SLVOE_OFFSET 10
66#define SPI_SRL_OFFSET 11
67#define SPI_CFS_OFFSET 12
68
Wan Ahmad Zainiee539f432020-05-05 21:06:14 +080069/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
70#define DWC_SSI_CTRLR0_SRL_OFFSET 13
71#define DWC_SSI_CTRLR0_TMOD_OFFSET 10
72#define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
73#define DWC_SSI_CTRLR0_SCPOL_OFFSET 9
74#define DWC_SSI_CTRLR0_SCPH_OFFSET 8
75#define DWC_SSI_CTRLR0_FRF_OFFSET 6
76#define DWC_SSI_CTRLR0_DFS_OFFSET 0
77
Serge Seminffb7ca52020-09-20 14:28:54 +030078/*
79 * For Keem Bay, CTRLR0[31] is used to select controller mode.
80 * 0: SSI is slave
81 * 1: SSI is master
82 */
83#define DWC_SSI_CTRLR0_KEEMBAY_MST BIT(31)
84
Serge Semin64232072020-10-08 02:55:06 +030085/* Bit fields in CTRLR1 */
86#define SPI_NDF_MASK GENMASK(15, 0)
87
Feng Tange24c7452009-12-14 14:20:22 -080088/* Bit fields in SR, 7 bits */
89#define SR_MASK 0x7f /* cover 7 bits */
90#define SR_BUSY (1 << 0)
91#define SR_TF_NOT_FULL (1 << 1)
92#define SR_TF_EMPT (1 << 2)
93#define SR_RF_NOT_EMPT (1 << 3)
94#define SR_RF_FULL (1 << 4)
95#define SR_TX_ERR (1 << 5)
96#define SR_DCOL (1 << 6)
97
98/* Bit fields in ISR, IMR, RISR, 7 bits */
99#define SPI_INT_TXEI (1 << 0)
100#define SPI_INT_TXOI (1 << 1)
101#define SPI_INT_RXUI (1 << 2)
102#define SPI_INT_RXOI (1 << 3)
103#define SPI_INT_RXFI (1 << 4)
104#define SPI_INT_MSTI (1 << 5)
105
Andy Shevchenko15ee3be2014-10-02 16:31:07 +0300106/* Bit fields in DMACR */
107#define SPI_DMA_RDMAE (1 << 0)
108#define SPI_DMA_TDMAE (1 << 1)
109
Serge Semincf75bae2020-10-08 02:55:04 +0300110#define SPI_WAIT_RETRIES 5
Serge Semin64232072020-10-08 02:55:06 +0300111#define SPI_BUF_SIZE \
112 (sizeof_field(struct spi_mem_op, cmd.opcode) + \
113 sizeof_field(struct spi_mem_op, addr.val) + 256)
114#define SPI_GET_BYTE(_val, _idx) \
115 ((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)
Serge Semincf75bae2020-10-08 02:55:04 +0300116
Feng Tange24c7452009-12-14 14:20:22 -0800117enum dw_ssi_type {
118 SSI_MOTO_SPI = 0,
119 SSI_TI_SSP,
120 SSI_NS_MICROWIRE,
121};
122
Serge Semincc760f32020-09-20 14:28:53 +0300123/* DW SPI capabilities */
124#define DW_SPI_CAP_CS_OVERRIDE BIT(0)
Serge Seminffb7ca52020-09-20 14:28:54 +0300125#define DW_SPI_CAP_KEEMBAY_MST BIT(1)
Serge Semind6bbd112020-10-08 02:54:51 +0300126#define DW_SPI_CAP_DWC_SSI BIT(2)
Damien Le Moala51acc22020-12-06 10:18:16 +0900127#define DW_SPI_CAP_DFS32 BIT(3)
Serge Semincc760f32020-09-20 14:28:53 +0300128
Serge Semin3ff60c62020-10-08 02:54:56 +0300129/* Slave spi_transfer/spi_mem_op related */
130struct dw_spi_cfg {
131 u8 tmode;
132 u8 dfs;
133 u32 ndf;
134 u32 freq;
135};
136
Feng Tang7063c0d2010-12-24 13:59:11 +0800137struct dw_spi;
138struct dw_spi_dma_ops {
Andy Shevchenko6370aba2020-05-06 18:30:24 +0300139 int (*dma_init)(struct device *dev, struct dw_spi *dws);
Feng Tang7063c0d2010-12-24 13:59:11 +0800140 void (*dma_exit)(struct dw_spi *dws);
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200141 int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
Jarkko Nikula721483e2018-02-01 17:17:29 +0200142 bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200143 struct spi_transfer *xfer);
144 int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
Andy Shevchenko4d5ac1e2015-03-09 16:48:48 +0200145 void (*dma_stop)(struct dw_spi *dws);
Feng Tang7063c0d2010-12-24 13:59:11 +0800146};
147
Feng Tange24c7452009-12-14 14:20:22 -0800148struct dw_spi {
Jarkko Nikula721483e2018-02-01 17:17:29 +0200149 struct spi_controller *master;
Feng Tange24c7452009-12-14 14:20:22 -0800150
151 void __iomem *regs;
152 unsigned long paddr;
Feng Tange24c7452009-12-14 14:20:22 -0800153 int irq;
Feng Tang552e4502010-01-20 13:49:45 -0700154 u32 fifo_len; /* depth of the FIFO buffer */
Damien Le Moala51acc22020-12-06 10:18:16 +0900155 unsigned int dfs_offset; /* CTRLR0 DFS field offset */
Serge Semin84ecaf42020-10-08 02:55:07 +0300156 u32 max_mem_freq; /* max mem-ops bus freq */
Feng Tange24c7452009-12-14 14:20:22 -0800157 u32 max_freq; /* max bus freq supported */
158
Serge Semincc760f32020-09-20 14:28:53 +0300159 u32 caps; /* DW SPI capabilities */
160
Michael van der Westhuizenc4fe57f2015-08-18 22:21:53 +0200161 u32 reg_io_width; /* DR I/O width in bytes */
Feng Tange24c7452009-12-14 14:20:22 -0800162 u16 bus_num;
163 u16 num_cs; /* supported slave numbers */
Alexandre Belloni62dbbae2018-07-17 16:23:11 +0200164 void (*set_cs)(struct spi_device *spi, bool enable);
Feng Tange24c7452009-12-14 14:20:22 -0800165
Feng Tange24c7452009-12-14 14:20:22 -0800166 /* Current message transfer state info */
Feng Tange24c7452009-12-14 14:20:22 -0800167 void *tx;
Serge Semin8dedbea2020-10-08 02:54:57 +0300168 unsigned int tx_len;
Feng Tange24c7452009-12-14 14:20:22 -0800169 void *rx;
Serge Semin8dedbea2020-10-08 02:54:57 +0300170 unsigned int rx_len;
Serge Semin64232072020-10-08 02:55:06 +0300171 u8 buf[SPI_BUF_SIZE];
Feng Tange24c7452009-12-14 14:20:22 -0800172 int dma_mapped;
Feng Tange24c7452009-12-14 14:20:22 -0800173 u8 n_bytes; /* current is a 1/2 bytes op */
Feng Tange24c7452009-12-14 14:20:22 -0800174 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
Matthias Seidel13b10302016-09-04 02:04:49 +0200175 u32 current_freq; /* frequency in hz */
Lars Povlsenbac70b52020-08-24 22:30:05 +0200176 u32 cur_rx_sample_dly;
177 u32 def_rx_sample_dly_ns;
Feng Tange24c7452009-12-14 14:20:22 -0800178
Serge Semin64232072020-10-08 02:55:06 +0300179 /* Custom memory operations */
180 struct spi_controller_mem_ops mem_ops;
181
Andy Shevchenkof89a6d82015-03-09 16:48:49 +0200182 /* DMA info */
Feng Tange24c7452009-12-14 14:20:22 -0800183 struct dma_chan *txchan;
Serge Semin0b2b6652020-05-29 16:11:56 +0300184 u32 txburst;
Feng Tange24c7452009-12-14 14:20:22 -0800185 struct dma_chan *rxchan;
Serge Semin0b2b6652020-05-29 16:11:56 +0300186 u32 rxburst;
Serge Seminad4fe122020-09-20 14:23:22 +0300187 u32 dma_sg_burst;
Andy Shevchenko30c8eb52014-10-28 18:25:02 +0200188 unsigned long dma_chan_busy;
Feng Tang7063c0d2010-12-24 13:59:11 +0800189 dma_addr_t dma_addr; /* phy address of the Data register */
Julia Lawall4fe338c2015-11-28 15:09:38 +0100190 const struct dw_spi_dma_ops *dma_ops;
Serge Seminbdbdf0f2020-05-29 16:11:52 +0300191 struct completion dma_completion;
Feng Tange24c7452009-12-14 14:20:22 -0800192
Feng Tange24c7452009-12-14 14:20:22 -0800193#ifdef CONFIG_DEBUG_FS
194 struct dentry *debugfs;
Serge Semin83784492020-05-29 16:12:04 +0300195 struct debugfs_regset32 regset;
Feng Tange24c7452009-12-14 14:20:22 -0800196#endif
197};
198
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700199static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
200{
201 return __raw_readl(dws->regs + offset);
202}
203
204static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
205{
206 __raw_writel(val, dws->regs + offset);
207}
208
Michael van der Westhuizenc4fe57f2015-08-18 22:21:53 +0200209static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
210{
211 switch (dws->reg_io_width) {
212 case 2:
Serge Semin7e31cea2020-09-20 14:28:51 +0300213 return readw_relaxed(dws->regs + offset);
Michael van der Westhuizenc4fe57f2015-08-18 22:21:53 +0200214 case 4:
215 default:
Serge Semin7e31cea2020-09-20 14:28:51 +0300216 return readl_relaxed(dws->regs + offset);
Michael van der Westhuizenc4fe57f2015-08-18 22:21:53 +0200217 }
218}
219
220static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
221{
222 switch (dws->reg_io_width) {
223 case 2:
Serge Semin7e31cea2020-09-20 14:28:51 +0300224 writew_relaxed(val, dws->regs + offset);
Michael van der Westhuizenc4fe57f2015-08-18 22:21:53 +0200225 break;
226 case 4:
227 default:
Serge Semin7e31cea2020-09-20 14:28:51 +0300228 writel_relaxed(val, dws->regs + offset);
Michael van der Westhuizenc4fe57f2015-08-18 22:21:53 +0200229 break;
230 }
231}
232
Feng Tange24c7452009-12-14 14:20:22 -0800233static inline void spi_enable_chip(struct dw_spi *dws, int enable)
234{
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700235 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
Feng Tange24c7452009-12-14 14:20:22 -0800236}
237
238static inline void spi_set_clk(struct dw_spi *dws, u16 div)
239{
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700240 dw_writel(dws, DW_SPI_BAUDR, div);
Feng Tange24c7452009-12-14 14:20:22 -0800241}
242
Feng Tange24c7452009-12-14 14:20:22 -0800243/* Disable IRQ bits */
244static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
245{
246 u32 new_mask;
247
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700248 new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
249 dw_writel(dws, DW_SPI_IMR, new_mask);
Feng Tange24c7452009-12-14 14:20:22 -0800250}
251
252/* Enable IRQ bits */
253static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
254{
255 u32 new_mask;
256
H Hartley Sweeten7eb187b2011-09-20 11:06:17 -0700257 new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
258 dw_writel(dws, DW_SPI_IMR, new_mask);
Feng Tange24c7452009-12-14 14:20:22 -0800259}
260
261/*
Serge Seminfbddc982020-10-08 02:55:02 +0300262 * This disables the SPI controller, interrupts, clears the interrupts status
263 * and CS, then re-enables the controller back. Transmit and receive FIFO
264 * buffers are cleared when the device is disabled.
Andy Shevchenko45746e82015-03-02 14:58:55 +0200265 */
266static inline void spi_reset_chip(struct dw_spi *dws)
267{
268 spi_enable_chip(dws, 0);
269 spi_mask_intr(dws, 0xff);
Serge Semina128f6e2020-09-20 14:28:49 +0300270 dw_readl(dws, DW_SPI_ICR);
Serge Seminfbddc982020-10-08 02:55:02 +0300271 dw_writel(dws, DW_SPI_SER, 0);
Andy Shevchenko45746e82015-03-02 14:58:55 +0200272 spi_enable_chip(dws, 1);
273}
274
Andy Shevchenko1cc3f142015-10-14 23:12:23 +0300275static inline void spi_shutdown_chip(struct dw_spi *dws)
276{
277 spi_enable_chip(dws, 0);
278 spi_set_clk(dws, 0);
279}
280
Alexandre Bellonic79bdbb2018-07-27 21:53:54 +0200281extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
Serge Semin3ff60c62020-10-08 02:54:56 +0300282extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
283 struct dw_spi_cfg *cfg);
Serge Seminbf64b662020-10-08 02:55:05 +0300284extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
Baruch Siach04f421e2013-12-30 20:30:44 +0200285extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
Feng Tange24c7452009-12-14 14:20:22 -0800286extern void dw_spi_remove_host(struct dw_spi *dws);
287extern int dw_spi_suspend_host(struct dw_spi *dws);
288extern int dw_spi_resume_host(struct dw_spi *dws);
Feng Tang7063c0d2010-12-24 13:59:11 +0800289
Serge Semin6c710c02020-05-29 16:11:59 +0300290#ifdef CONFIG_SPI_DW_DMA
291
Serge Semin57784412020-05-29 16:12:02 +0300292extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
293extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
Serge Semin6c710c02020-05-29 16:11:59 +0300294
295#else
296
Serge Semin57784412020-05-29 16:12:02 +0300297static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
298static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
Serge Semin6c710c02020-05-29 16:11:59 +0300299
300#endif /* !CONFIG_SPI_DW_DMA */
Andy Shevchenko37aa8aa2020-05-06 18:30:23 +0300301
Feng Tange24c7452009-12-14 14:20:22 -0800302#endif /* DW_SPI_HEADER_H */