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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001// SPDX-License-Identifier: GPL-2.0
Ralf Baechle39b8d522008-04-28 17:14:26 +01002/*
3 * Count register synchronisation.
4 *
Tim Andersoneb9b5142009-06-17 16:40:34 -07005 * All CPUs will have their count registers synchronised to the CPU0 next time
Ralf Baechle39b8d522008-04-28 17:14:26 +01006 * value. This can cause a small timewarp for CPU0. All other CPU's should
7 * not have done anything significant (but they may have had interrupts
8 * enabled briefly - prom_smp_finish() should not be responsible for enabling
9 * interrupts...)
Ralf Baechle39b8d522008-04-28 17:14:26 +010010 */
11
12#include <linux/kernel.h>
Ralf Baechle39b8d522008-04-28 17:14:26 +010013#include <linux/irqflags.h>
Tim Andersoneb9b5142009-06-17 16:40:34 -070014#include <linux/cpumask.h>
Ralf Baechle39b8d522008-04-28 17:14:26 +010015
Tim Andersoneb9b5142009-06-17 16:40:34 -070016#include <asm/r4k-timer.h>
Arun Sharma600634972011-07-26 16:09:06 -070017#include <linux/atomic.h>
Ralf Baechle39b8d522008-04-28 17:14:26 +010018#include <asm/barrier.h>
Ralf Baechle39b8d522008-04-28 17:14:26 +010019#include <asm/mipsregs.h>
20
Huacai Chendb0dbd52016-01-21 21:09:51 +080021static unsigned int initcount = 0;
Paul Gortmaker078a55f2013-06-18 13:38:59 +000022static atomic_t count_count_start = ATOMIC_INIT(0);
23static atomic_t count_count_stop = ATOMIC_INIT(0);
Ralf Baechle39b8d522008-04-28 17:14:26 +010024
Ralf Baechle70342282013-01-22 12:59:30 +010025#define COUNTON 100
Huacai Chendb0dbd52016-01-21 21:09:51 +080026#define NR_LOOPS 3
Ralf Baechle39b8d522008-04-28 17:14:26 +010027
Paul Gortmaker078a55f2013-06-18 13:38:59 +000028void synchronise_count_master(int cpu)
Ralf Baechle39b8d522008-04-28 17:14:26 +010029{
30 int i;
31 unsigned long flags;
Ralf Baechle39b8d522008-04-28 17:14:26 +010032
Matt Redfearn4fb69af2017-02-02 13:22:04 +000033 pr_info("Synchronize counters for CPU %u: ", cpu);
Ralf Baechle39b8d522008-04-28 17:14:26 +010034
35 local_irq_save(flags);
36
37 /*
Ralf Baechle39b8d522008-04-28 17:14:26 +010038 * We loop a few times to get a primed instruction cache,
39 * then the last pass is more or less synchronised and
40 * the master and slaves each set their cycle counters to a known
41 * value all at once. This reduces the chance of having random offsets
42 * between the processors, and guarantees that the maximum
43 * delay between the cycle counters is never bigger than
44 * the latency of information-passing (cachelines) between
45 * two CPUs.
46 */
47
Ralf Baechle39b8d522008-04-28 17:14:26 +010048 for (i = 0; i < NR_LOOPS; i++) {
Jayachandran Ccf9bfe52012-08-14 18:56:13 +053049 /* slaves loop on '!= 2' */
50 while (atomic_read(&count_count_start) != 1)
Ralf Baechle39b8d522008-04-28 17:14:26 +010051 mb();
52 atomic_set(&count_count_stop, 0);
53 smp_wmb();
54
Huacai Chendb0dbd52016-01-21 21:09:51 +080055 /* Let the slave writes its count register */
Ralf Baechle39b8d522008-04-28 17:14:26 +010056 atomic_inc(&count_count_start);
57
Huacai Chendb0dbd52016-01-21 21:09:51 +080058 /* Count will be initialised to current timer */
59 if (i == 1)
60 initcount = read_c0_count();
61
Ralf Baechle39b8d522008-04-28 17:14:26 +010062 /*
63 * Everyone initialises count in the last loop:
64 */
65 if (i == NR_LOOPS-1)
66 write_c0_count(initcount);
67
68 /*
Huacai Chendb0dbd52016-01-21 21:09:51 +080069 * Wait for slave to leave the synchronization point:
Ralf Baechle39b8d522008-04-28 17:14:26 +010070 */
Jayachandran Ccf9bfe52012-08-14 18:56:13 +053071 while (atomic_read(&count_count_stop) != 1)
Ralf Baechle39b8d522008-04-28 17:14:26 +010072 mb();
73 atomic_set(&count_count_start, 0);
74 smp_wmb();
75 atomic_inc(&count_count_stop);
76 }
77 /* Arrange for an interrupt in a short while */
78 write_c0_compare(read_c0_count() + COUNTON);
79
80 local_irq_restore(flags);
81
82 /*
83 * i386 code reported the skew here, but the
84 * count registers were almost certainly out of sync
85 * so no point in alarming people
86 */
Matt Redfearn4fb69af2017-02-02 13:22:04 +000087 pr_cont("done.\n");
Ralf Baechle39b8d522008-04-28 17:14:26 +010088}
89
Paul Gortmaker078a55f2013-06-18 13:38:59 +000090void synchronise_count_slave(int cpu)
Ralf Baechle39b8d522008-04-28 17:14:26 +010091{
92 int i;
Ralf Baechle39b8d522008-04-28 17:14:26 +010093
Ralf Baechle39b8d522008-04-28 17:14:26 +010094 /*
95 * Not every cpu is online at the time this gets called,
96 * so we first wait for the master to say everyone is ready
97 */
98
Ralf Baechle39b8d522008-04-28 17:14:26 +010099 for (i = 0; i < NR_LOOPS; i++) {
100 atomic_inc(&count_count_start);
Jayachandran Ccf9bfe52012-08-14 18:56:13 +0530101 while (atomic_read(&count_count_start) != 2)
Ralf Baechle39b8d522008-04-28 17:14:26 +0100102 mb();
103
104 /*
105 * Everyone initialises count in the last loop:
106 */
107 if (i == NR_LOOPS-1)
108 write_c0_count(initcount);
109
110 atomic_inc(&count_count_stop);
Jayachandran Ccf9bfe52012-08-14 18:56:13 +0530111 while (atomic_read(&count_count_stop) != 2)
Ralf Baechle39b8d522008-04-28 17:14:26 +0100112 mb();
113 }
114 /* Arrange for an interrupt in a short while */
115 write_c0_compare(read_c0_count() + COUNTON);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100116}
117#undef NR_LOOPS