Alexander Shishkin | 52ca9ce | 2015-01-30 12:39:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Intel(R) Processor Trace PMU driver for perf |
| 3 | * Copyright (c) 2013-2014, Intel Corporation. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * Intel PT is specified in the Intel Architecture Instruction Set Extensions |
| 15 | * Programming Reference: |
| 16 | * http://software.intel.com/en-us/intel-isa-extensions |
| 17 | */ |
| 18 | |
| 19 | #ifndef __INTEL_PT_H__ |
| 20 | #define __INTEL_PT_H__ |
| 21 | |
| 22 | /* |
| 23 | * Single-entry ToPA: when this close to region boundary, switch |
| 24 | * buffers to avoid losing data. |
| 25 | */ |
| 26 | #define TOPA_PMI_MARGIN 512 |
| 27 | |
Takao Indoh | 709bc87 | 2015-08-04 18:36:55 +0900 | [diff] [blame] | 28 | #define TOPA_SHIFT 12 |
Alexander Shishkin | 52ca9ce | 2015-01-30 12:39:52 +0200 | [diff] [blame] | 29 | |
Takao Indoh | 709bc87 | 2015-08-04 18:36:55 +0900 | [diff] [blame] | 30 | static inline unsigned int sizes(unsigned int tsz) |
Alexander Shishkin | 52ca9ce | 2015-01-30 12:39:52 +0200 | [diff] [blame] | 31 | { |
Takao Indoh | 709bc87 | 2015-08-04 18:36:55 +0900 | [diff] [blame] | 32 | return 1 << (tsz + TOPA_SHIFT); |
Alexander Shishkin | 52ca9ce | 2015-01-30 12:39:52 +0200 | [diff] [blame] | 33 | }; |
| 34 | |
| 35 | struct topa_entry { |
| 36 | u64 end : 1; |
| 37 | u64 rsvd0 : 1; |
| 38 | u64 intr : 1; |
| 39 | u64 rsvd1 : 1; |
| 40 | u64 stop : 1; |
| 41 | u64 rsvd2 : 1; |
| 42 | u64 size : 4; |
| 43 | u64 rsvd3 : 2; |
| 44 | u64 base : 36; |
| 45 | u64 rsvd4 : 16; |
| 46 | }; |
| 47 | |
Takao Indoh | 709bc87 | 2015-08-04 18:36:55 +0900 | [diff] [blame] | 48 | #define PT_CPUID_LEAVES 2 |
| 49 | #define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */ |
Alexander Shishkin | 52ca9ce | 2015-01-30 12:39:52 +0200 | [diff] [blame] | 50 | |
| 51 | enum pt_capabilities { |
| 52 | PT_CAP_max_subleaf = 0, |
| 53 | PT_CAP_cr3_filtering, |
Alexander Shishkin | b1bf72d | 2015-07-30 16:15:31 +0300 | [diff] [blame] | 54 | PT_CAP_psb_cyc, |
| 55 | PT_CAP_mtc, |
Alexander Shishkin | 52ca9ce | 2015-01-30 12:39:52 +0200 | [diff] [blame] | 56 | PT_CAP_topa_output, |
| 57 | PT_CAP_topa_multiple_entries, |
Alexander Shishkin | b1bf72d | 2015-07-30 16:15:31 +0300 | [diff] [blame] | 58 | PT_CAP_single_range_output, |
Alexander Shishkin | 52ca9ce | 2015-01-30 12:39:52 +0200 | [diff] [blame] | 59 | PT_CAP_payloads_lip, |
Alexander Shishkin | b1bf72d | 2015-07-30 16:15:31 +0300 | [diff] [blame] | 60 | PT_CAP_mtc_periods, |
| 61 | PT_CAP_cycle_thresholds, |
| 62 | PT_CAP_psb_periods, |
Alexander Shishkin | 52ca9ce | 2015-01-30 12:39:52 +0200 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | struct pt_pmu { |
| 66 | struct pmu pmu; |
Takao Indoh | 709bc87 | 2015-08-04 18:36:55 +0900 | [diff] [blame] | 67 | u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; |
Alexander Shishkin | 52ca9ce | 2015-01-30 12:39:52 +0200 | [diff] [blame] | 68 | }; |
| 69 | |
| 70 | /** |
| 71 | * struct pt_buffer - buffer configuration; one buffer per task_struct or |
| 72 | * cpu, depending on perf event configuration |
| 73 | * @cpu: cpu for per-cpu allocation |
| 74 | * @tables: list of ToPA tables in this buffer |
| 75 | * @first: shorthand for first topa table |
| 76 | * @last: shorthand for last topa table |
| 77 | * @cur: current topa table |
| 78 | * @nr_pages: buffer size in pages |
| 79 | * @cur_idx: current output region's index within @cur table |
| 80 | * @output_off: offset within the current output region |
| 81 | * @data_size: running total of the amount of data in this buffer |
| 82 | * @lost: if data was lost/truncated |
| 83 | * @head: logical write offset inside the buffer |
| 84 | * @snapshot: if this is for a snapshot/overwrite counter |
| 85 | * @stop_pos: STOP topa entry in the buffer |
| 86 | * @intr_pos: INT topa entry in the buffer |
| 87 | * @data_pages: array of pages from perf |
| 88 | * @topa_index: table of topa entries indexed by page offset |
| 89 | */ |
| 90 | struct pt_buffer { |
| 91 | int cpu; |
| 92 | struct list_head tables; |
| 93 | struct topa *first, *last, *cur; |
| 94 | unsigned int cur_idx; |
| 95 | size_t output_off; |
| 96 | unsigned long nr_pages; |
| 97 | local_t data_size; |
| 98 | local_t lost; |
| 99 | local64_t head; |
| 100 | bool snapshot; |
| 101 | unsigned long stop_pos, intr_pos; |
| 102 | void **data_pages; |
| 103 | struct topa_entry *topa_index[0]; |
| 104 | }; |
| 105 | |
| 106 | /** |
| 107 | * struct pt - per-cpu pt context |
| 108 | * @handle: perf output handle |
| 109 | * @handle_nmi: do handle PT PMI on this cpu, there's an active event |
| 110 | */ |
| 111 | struct pt { |
| 112 | struct perf_output_handle handle; |
| 113 | int handle_nmi; |
| 114 | }; |
| 115 | |
| 116 | #endif /* __INTEL_PT_H__ */ |