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Laxman Dewangandc4dc362012-10-30 12:34:05 +05301/*
2 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
3 *
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/clk.h>
20#include <linux/completion.h>
21#include <linux/delay.h>
22#include <linux/dmaengine.h>
23#include <linux/dma-mapping.h>
24#include <linux/dmapool.h>
25#include <linux/err.h>
Laxman Dewangandc4dc362012-10-30 12:34:05 +053026#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kernel.h>
29#include <linux/kthread.h>
30#include <linux/module.h>
31#include <linux/platform_device.h>
32#include <linux/pm_runtime.h>
33#include <linux/of.h>
34#include <linux/of_device.h>
Stephen Warrenff2251e2013-11-06 16:31:24 -070035#include <linux/reset.h>
Laxman Dewangandc4dc362012-10-30 12:34:05 +053036#include <linux/spi/spi.h>
Laxman Dewangandc4dc362012-10-30 12:34:05 +053037
38#define SLINK_COMMAND 0x000
39#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
40#define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
41#define SLINK_BOTH_EN (1 << 10)
42#define SLINK_CS_SW (1 << 11)
43#define SLINK_CS_VALUE (1 << 12)
44#define SLINK_CS_POLARITY (1 << 13)
45#define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
46#define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
47#define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
48#define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
49#define SLINK_IDLE_SDA_MASK (3 << 16)
50#define SLINK_CS_POLARITY1 (1 << 20)
51#define SLINK_CK_SDA (1 << 21)
52#define SLINK_CS_POLARITY2 (1 << 22)
53#define SLINK_CS_POLARITY3 (1 << 23)
54#define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
55#define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
56#define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
57#define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
58#define SLINK_IDLE_SCLK_MASK (3 << 24)
59#define SLINK_M_S (1 << 28)
60#define SLINK_WAIT (1 << 29)
61#define SLINK_GO (1 << 30)
62#define SLINK_ENB (1 << 31)
63
64#define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA)
65
66#define SLINK_COMMAND2 0x004
67#define SLINK_LSBFE (1 << 0)
68#define SLINK_SSOE (1 << 1)
69#define SLINK_SPIE (1 << 4)
70#define SLINK_BIDIROE (1 << 6)
71#define SLINK_MODFEN (1 << 7)
72#define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
73#define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
74#define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
75#define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
76#define SLINK_FIFO_REFILLS_0 (0 << 22)
77#define SLINK_FIFO_REFILLS_1 (1 << 22)
78#define SLINK_FIFO_REFILLS_2 (2 << 22)
79#define SLINK_FIFO_REFILLS_3 (3 << 22)
80#define SLINK_FIFO_REFILLS_MASK (3 << 22)
81#define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
82#define SLINK_SPC0 (1 << 29)
83#define SLINK_TXEN (1 << 30)
84#define SLINK_RXEN (1 << 31)
85
86#define SLINK_STATUS 0x008
87#define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
88#define SLINK_WORD(val) (((val) >> 5) & 0x1f)
89#define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
90#define SLINK_MODF (1 << 16)
91#define SLINK_RX_UNF (1 << 18)
92#define SLINK_TX_OVF (1 << 19)
93#define SLINK_TX_FULL (1 << 20)
94#define SLINK_TX_EMPTY (1 << 21)
95#define SLINK_RX_FULL (1 << 22)
96#define SLINK_RX_EMPTY (1 << 23)
97#define SLINK_TX_UNF (1 << 24)
98#define SLINK_RX_OVF (1 << 25)
99#define SLINK_TX_FLUSH (1 << 26)
100#define SLINK_RX_FLUSH (1 << 27)
101#define SLINK_SCLK (1 << 28)
102#define SLINK_ERR (1 << 29)
103#define SLINK_RDY (1 << 30)
104#define SLINK_BSY (1 << 31)
105#define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \
106 SLINK_TX_UNF | SLINK_RX_OVF)
107
108#define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY)
109
110#define SLINK_MAS_DATA 0x010
111#define SLINK_SLAVE_DATA 0x014
112
113#define SLINK_DMA_CTL 0x018
114#define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
115#define SLINK_TX_TRIG_1 (0 << 16)
116#define SLINK_TX_TRIG_4 (1 << 16)
117#define SLINK_TX_TRIG_8 (2 << 16)
118#define SLINK_TX_TRIG_16 (3 << 16)
119#define SLINK_TX_TRIG_MASK (3 << 16)
120#define SLINK_RX_TRIG_1 (0 << 18)
121#define SLINK_RX_TRIG_4 (1 << 18)
122#define SLINK_RX_TRIG_8 (2 << 18)
123#define SLINK_RX_TRIG_16 (3 << 18)
124#define SLINK_RX_TRIG_MASK (3 << 18)
125#define SLINK_PACKED (1 << 20)
126#define SLINK_PACK_SIZE_4 (0 << 21)
127#define SLINK_PACK_SIZE_8 (1 << 21)
128#define SLINK_PACK_SIZE_16 (2 << 21)
129#define SLINK_PACK_SIZE_32 (3 << 21)
130#define SLINK_PACK_SIZE_MASK (3 << 21)
131#define SLINK_IE_TXC (1 << 26)
132#define SLINK_IE_RXC (1 << 27)
133#define SLINK_DMA_EN (1 << 31)
134
135#define SLINK_STATUS2 0x01c
136#define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
137#define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16)
138#define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6)
139
140#define SLINK_TX_FIFO 0x100
141#define SLINK_RX_FIFO 0x180
142
143#define DATA_DIR_TX (1 << 0)
144#define DATA_DIR_RX (1 << 1)
145
146#define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000))
147
148#define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
149#define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20)
150#define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0)
151
152#define SLINK_STATUS2_RESET \
153 (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16)
154
155#define MAX_CHIP_SELECT 4
156#define SLINK_FIFO_DEPTH 32
157
158struct tegra_slink_chip_data {
159 bool cs_hold_time;
160};
161
162struct tegra_slink_data {
163 struct device *dev;
164 struct spi_master *master;
165 const struct tegra_slink_chip_data *chip_data;
166 spinlock_t lock;
167
168 struct clk *clk;
Stephen Warrenff2251e2013-11-06 16:31:24 -0700169 struct reset_control *rst;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530170 void __iomem *base;
171 phys_addr_t phys;
172 unsigned irq;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530173 u32 cur_speed;
174
175 struct spi_device *cur_spi;
176 unsigned cur_pos;
177 unsigned cur_len;
178 unsigned words_per_32bit;
179 unsigned bytes_per_word;
180 unsigned curr_dma_words;
181 unsigned cur_direction;
182
183 unsigned cur_rx_pos;
184 unsigned cur_tx_pos;
185
186 unsigned dma_buf_size;
187 unsigned max_buf_size;
188 bool is_curr_dma_xfer;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530189
190 struct completion rx_dma_complete;
191 struct completion tx_dma_complete;
192
193 u32 tx_status;
194 u32 rx_status;
195 u32 status_reg;
196 bool is_packed;
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100197 u32 packed_size;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530198
199 u32 command_reg;
200 u32 command2_reg;
201 u32 dma_control_reg;
202 u32 def_command_reg;
203 u32 def_command2_reg;
204
205 struct completion xfer_completion;
206 struct spi_transfer *curr_xfer;
207 struct dma_chan *rx_dma_chan;
208 u32 *rx_dma_buf;
209 dma_addr_t rx_dma_phys;
210 struct dma_async_tx_descriptor *rx_dma_desc;
211
212 struct dma_chan *tx_dma_chan;
213 u32 *tx_dma_buf;
214 dma_addr_t tx_dma_phys;
215 struct dma_async_tx_descriptor *tx_dma_desc;
216};
217
218static int tegra_slink_runtime_suspend(struct device *dev);
219static int tegra_slink_runtime_resume(struct device *dev);
220
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100221static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi,
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530222 unsigned long reg)
223{
224 return readl(tspi->base + reg);
225}
226
227static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100228 u32 val, unsigned long reg)
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530229{
230 writel(val, tspi->base + reg);
231
232 /* Read back register to make sure that register writes completed */
233 if (reg != SLINK_TX_FIFO)
234 readl(tspi->base + SLINK_MAS_DATA);
235}
236
237static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
238{
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100239 u32 val_write;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530240
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100241 tegra_slink_readl(tspi, SLINK_STATUS);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530242
243 /* Write 1 to clear status register */
244 val_write = SLINK_RDY | SLINK_FIFO_ERROR;
245 tegra_slink_writel(tspi, val_write, SLINK_STATUS);
246}
247
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100248static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530249 struct spi_transfer *t)
250{
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530251 switch (tspi->bytes_per_word) {
252 case 0:
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100253 return SLINK_PACK_SIZE_4;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530254 case 1:
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100255 return SLINK_PACK_SIZE_8;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530256 case 2:
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100257 return SLINK_PACK_SIZE_16;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530258 case 4:
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100259 return SLINK_PACK_SIZE_32;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530260 default:
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100261 return 0;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530262 }
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530263}
264
265static unsigned tegra_slink_calculate_curr_xfer_param(
266 struct spi_device *spi, struct tegra_slink_data *tspi,
267 struct spi_transfer *t)
268{
269 unsigned remain_len = t->len - tspi->cur_pos;
270 unsigned max_word;
Jingoo Han3cb7b402013-10-14 10:36:10 +0900271 unsigned bits_per_word;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530272 unsigned max_len;
273 unsigned total_fifo_words;
274
Laxman Dewangan766ed702012-12-18 14:25:43 +0530275 bits_per_word = t->bits_per_word;
Axel Line91d2352013-08-30 11:00:23 +0800276 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530277
278 if (bits_per_word == 8 || bits_per_word == 16) {
Gustavo A. R. Silva2172a332018-03-05 17:53:39 -0600279 tspi->is_packed = true;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530280 tspi->words_per_32bit = 32/bits_per_word;
281 } else {
Gustavo A. R. Silva2172a332018-03-05 17:53:39 -0600282 tspi->is_packed = false;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530283 tspi->words_per_32bit = 1;
284 }
285 tspi->packed_size = tegra_slink_get_packed_size(tspi, t);
286
287 if (tspi->is_packed) {
288 max_len = min(remain_len, tspi->max_buf_size);
289 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
290 total_fifo_words = max_len/4;
291 } else {
292 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
293 max_word = min(max_word, tspi->max_buf_size/4);
294 tspi->curr_dma_words = max_word;
295 total_fifo_words = max_word;
296 }
297 return total_fifo_words;
298}
299
300static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
301 struct tegra_slink_data *tspi, struct spi_transfer *t)
302{
303 unsigned nbytes;
304 unsigned tx_empty_count;
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100305 u32 fifo_status;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530306 unsigned max_n_32bit;
307 unsigned i, count;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530308 unsigned int written_words;
309 unsigned fifo_words_left;
310 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
311
312 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
313 tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
314
315 if (tspi->is_packed) {
316 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
317 written_words = min(fifo_words_left, tspi->curr_dma_words);
318 nbytes = written_words * tspi->bytes_per_word;
319 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
320 for (count = 0; count < max_n_32bit; count++) {
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100321 u32 x = 0;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530322 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100323 x |= (u32)(*tx_buf++) << (i * 8);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530324 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
325 }
326 } else {
327 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
328 written_words = max_n_32bit;
329 nbytes = written_words * tspi->bytes_per_word;
330 for (count = 0; count < max_n_32bit; count++) {
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100331 u32 x = 0;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530332 for (i = 0; nbytes && (i < tspi->bytes_per_word);
333 i++, nbytes--)
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100334 x |= (u32)(*tx_buf++) << (i * 8);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530335 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
336 }
337 }
338 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
339 return written_words;
340}
341
342static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
343 struct tegra_slink_data *tspi, struct spi_transfer *t)
344{
345 unsigned rx_full_count;
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100346 u32 fifo_status;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530347 unsigned i, count;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530348 unsigned int read_words = 0;
349 unsigned len;
350 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
351
352 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
353 rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
354 if (tspi->is_packed) {
355 len = tspi->curr_dma_words * tspi->bytes_per_word;
356 for (count = 0; count < rx_full_count; count++) {
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100357 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530358 for (i = 0; len && (i < 4); i++, len--)
359 *rx_buf++ = (x >> i*8) & 0xFF;
360 }
361 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
362 read_words += tspi->curr_dma_words;
363 } else {
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530364 for (count = 0; count < rx_full_count; count++) {
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100365 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530366 for (i = 0; (i < tspi->bytes_per_word); i++)
367 *rx_buf++ = (x >> (i*8)) & 0xFF;
368 }
369 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
370 read_words += rx_full_count;
371 }
372 return read_words;
373}
374
375static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
376 struct tegra_slink_data *tspi, struct spi_transfer *t)
377{
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530378 /* Make the dma buffer to read by cpu */
379 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
380 tspi->dma_buf_size, DMA_TO_DEVICE);
381
382 if (tspi->is_packed) {
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100383 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530384 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
385 } else {
386 unsigned int i;
387 unsigned int count;
388 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
389 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530390
391 for (count = 0; count < tspi->curr_dma_words; count++) {
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100392 u32 x = 0;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530393 for (i = 0; consume && (i < tspi->bytes_per_word);
394 i++, consume--)
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100395 x |= (u32)(*tx_buf++) << (i * 8);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530396 tspi->tx_dma_buf[count] = x;
397 }
398 }
399 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
400
401 /* Make the dma buffer to read by dma */
402 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
403 tspi->dma_buf_size, DMA_TO_DEVICE);
404}
405
406static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
407 struct tegra_slink_data *tspi, struct spi_transfer *t)
408{
409 unsigned len;
410
411 /* Make the dma buffer to read by cpu */
412 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
413 tspi->dma_buf_size, DMA_FROM_DEVICE);
414
415 if (tspi->is_packed) {
416 len = tspi->curr_dma_words * tspi->bytes_per_word;
417 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
418 } else {
419 unsigned int i;
420 unsigned int count;
421 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100422 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530423
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530424 for (count = 0; count < tspi->curr_dma_words; count++) {
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100425 u32 x = tspi->rx_dma_buf[count] & rx_mask;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530426 for (i = 0; (i < tspi->bytes_per_word); i++)
427 *rx_buf++ = (x >> (i*8)) & 0xFF;
428 }
429 }
430 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
431
432 /* Make the dma buffer to read by dma */
433 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
434 tspi->dma_buf_size, DMA_FROM_DEVICE);
435}
436
437static void tegra_slink_dma_complete(void *args)
438{
439 struct completion *dma_complete = args;
440
441 complete(dma_complete);
442}
443
444static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len)
445{
Wolfram Sang16735d02013-11-14 14:32:02 -0800446 reinit_completion(&tspi->tx_dma_complete);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530447 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
448 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
Mark Brown72919f32013-04-03 18:30:31 +0100449 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530450 if (!tspi->tx_dma_desc) {
451 dev_err(tspi->dev, "Not able to get desc for Tx\n");
452 return -EIO;
453 }
454
455 tspi->tx_dma_desc->callback = tegra_slink_dma_complete;
456 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
457
458 dmaengine_submit(tspi->tx_dma_desc);
459 dma_async_issue_pending(tspi->tx_dma_chan);
460 return 0;
461}
462
463static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len)
464{
Wolfram Sang16735d02013-11-14 14:32:02 -0800465 reinit_completion(&tspi->rx_dma_complete);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530466 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
467 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
Mark Brown72919f32013-04-03 18:30:31 +0100468 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530469 if (!tspi->rx_dma_desc) {
470 dev_err(tspi->dev, "Not able to get desc for Rx\n");
471 return -EIO;
472 }
473
474 tspi->rx_dma_desc->callback = tegra_slink_dma_complete;
475 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
476
477 dmaengine_submit(tspi->rx_dma_desc);
478 dma_async_issue_pending(tspi->rx_dma_chan);
479 return 0;
480}
481
482static int tegra_slink_start_dma_based_transfer(
483 struct tegra_slink_data *tspi, struct spi_transfer *t)
484{
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100485 u32 val;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530486 unsigned int len;
487 int ret = 0;
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100488 u32 status;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530489
490 /* Make sure that Rx and Tx fifo are empty */
491 status = tegra_slink_readl(tspi, SLINK_STATUS);
492 if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) {
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100493 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
494 (unsigned)status);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530495 return -EIO;
496 }
497
498 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
499 val |= tspi->packed_size;
500 if (tspi->is_packed)
501 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
502 4) * 4;
503 else
504 len = tspi->curr_dma_words * 4;
505
506 /* Set attention level based on length of transfer */
507 if (len & 0xF)
508 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
509 else if (((len) >> 4) & 0x1)
510 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
511 else
512 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
513
514 if (tspi->cur_direction & DATA_DIR_TX)
515 val |= SLINK_IE_TXC;
516
517 if (tspi->cur_direction & DATA_DIR_RX)
518 val |= SLINK_IE_RXC;
519
520 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
521 tspi->dma_control_reg = val;
522
523 if (tspi->cur_direction & DATA_DIR_TX) {
524 tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t);
525 wmb();
526 ret = tegra_slink_start_tx_dma(tspi, len);
527 if (ret < 0) {
528 dev_err(tspi->dev,
529 "Starting tx dma failed, err %d\n", ret);
530 return ret;
531 }
532
533 /* Wait for tx fifo to be fill before starting slink */
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100534 status = tegra_slink_readl(tspi, SLINK_STATUS);
535 while (!(status & SLINK_TX_FULL))
536 status = tegra_slink_readl(tspi, SLINK_STATUS);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530537 }
538
539 if (tspi->cur_direction & DATA_DIR_RX) {
540 /* Make the dma buffer to read by dma */
541 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
542 tspi->dma_buf_size, DMA_FROM_DEVICE);
543
544 ret = tegra_slink_start_rx_dma(tspi, len);
545 if (ret < 0) {
546 dev_err(tspi->dev,
547 "Starting rx dma failed, err %d\n", ret);
548 if (tspi->cur_direction & DATA_DIR_TX)
549 dmaengine_terminate_all(tspi->tx_dma_chan);
550 return ret;
551 }
552 }
553 tspi->is_curr_dma_xfer = true;
554 if (tspi->is_packed) {
555 val |= SLINK_PACKED;
556 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
557 /* HW need small delay after settign Packed mode */
558 udelay(1);
559 }
560 tspi->dma_control_reg = val;
561
562 val |= SLINK_DMA_EN;
563 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
564 return ret;
565}
566
567static int tegra_slink_start_cpu_based_transfer(
568 struct tegra_slink_data *tspi, struct spi_transfer *t)
569{
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100570 u32 val;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530571 unsigned cur_words;
572
573 val = tspi->packed_size;
574 if (tspi->cur_direction & DATA_DIR_TX)
575 val |= SLINK_IE_TXC;
576
577 if (tspi->cur_direction & DATA_DIR_RX)
578 val |= SLINK_IE_RXC;
579
580 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
581 tspi->dma_control_reg = val;
582
583 if (tspi->cur_direction & DATA_DIR_TX)
584 cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t);
585 else
586 cur_words = tspi->curr_dma_words;
587 val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1);
588 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
589 tspi->dma_control_reg = val;
590
591 tspi->is_curr_dma_xfer = false;
592 if (tspi->is_packed) {
593 val |= SLINK_PACKED;
594 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
595 udelay(1);
596 wmb();
597 }
598 tspi->dma_control_reg = val;
599 val |= SLINK_DMA_EN;
600 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
601 return 0;
602}
603
604static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
605 bool dma_to_memory)
606{
607 struct dma_chan *dma_chan;
608 u32 *dma_buf;
609 dma_addr_t dma_phys;
610 int ret;
611 struct dma_slave_config dma_sconfig;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530612
Dan Carpenter8a0a1af2013-12-16 17:02:10 +0300613 dma_chan = dma_request_slave_channel_reason(tspi->dev,
614 dma_to_memory ? "rx" : "tx");
Stephen Warrena915d152013-11-11 13:13:47 -0700615 if (IS_ERR(dma_chan)) {
616 ret = PTR_ERR(dma_chan);
617 if (ret != -EPROBE_DEFER)
618 dev_err(tspi->dev,
619 "Dma channel is not available: %d\n", ret);
620 return ret;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530621 }
622
623 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
624 &dma_phys, GFP_KERNEL);
625 if (!dma_buf) {
626 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
627 dma_release_channel(dma_chan);
628 return -ENOMEM;
629 }
630
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530631 if (dma_to_memory) {
632 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
633 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
634 dma_sconfig.src_maxburst = 0;
635 } else {
636 dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO;
637 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
638 dma_sconfig.dst_maxburst = 0;
639 }
640
641 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
642 if (ret)
643 goto scrub;
644 if (dma_to_memory) {
645 tspi->rx_dma_chan = dma_chan;
646 tspi->rx_dma_buf = dma_buf;
647 tspi->rx_dma_phys = dma_phys;
648 } else {
649 tspi->tx_dma_chan = dma_chan;
650 tspi->tx_dma_buf = dma_buf;
651 tspi->tx_dma_phys = dma_phys;
652 }
653 return 0;
654
655scrub:
656 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
657 dma_release_channel(dma_chan);
658 return ret;
659}
660
661static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi,
662 bool dma_to_memory)
663{
664 u32 *dma_buf;
665 dma_addr_t dma_phys;
666 struct dma_chan *dma_chan;
667
668 if (dma_to_memory) {
669 dma_buf = tspi->rx_dma_buf;
670 dma_chan = tspi->rx_dma_chan;
671 dma_phys = tspi->rx_dma_phys;
672 tspi->rx_dma_chan = NULL;
673 tspi->rx_dma_buf = NULL;
674 } else {
675 dma_buf = tspi->tx_dma_buf;
676 dma_chan = tspi->tx_dma_chan;
677 dma_phys = tspi->tx_dma_phys;
678 tspi->tx_dma_buf = NULL;
679 tspi->tx_dma_chan = NULL;
680 }
681 if (!dma_chan)
682 return;
683
684 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
685 dma_release_channel(dma_chan);
686}
687
688static int tegra_slink_start_transfer_one(struct spi_device *spi,
Mark Brownf178e3d2013-10-05 12:30:42 +0100689 struct spi_transfer *t)
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530690{
691 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
692 u32 speed;
693 u8 bits_per_word;
694 unsigned total_fifo_words;
695 int ret;
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100696 u32 command;
697 u32 command2;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530698
Laxman Dewangane6811d12012-11-09 14:36:45 +0530699 bits_per_word = t->bits_per_word;
Laxman Dewanganbeb96c22013-01-05 00:17:15 +0530700 speed = t->speed_hz;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530701 if (speed != tspi->cur_speed) {
702 clk_set_rate(tspi->clk, speed * 4);
703 tspi->cur_speed = speed;
704 }
705
706 tspi->cur_spi = spi;
707 tspi->cur_pos = 0;
708 tspi->cur_rx_pos = 0;
709 tspi->cur_tx_pos = 0;
710 tspi->curr_xfer = t;
711 total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t);
712
Mark Brownf178e3d2013-10-05 12:30:42 +0100713 command = tspi->command_reg;
714 command &= ~SLINK_BIT_LENGTH(~0);
715 command |= SLINK_BIT_LENGTH(bits_per_word - 1);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530716
Mark Brownf178e3d2013-10-05 12:30:42 +0100717 command2 = tspi->command2_reg;
718 command2 &= ~(SLINK_RXEN | SLINK_TXEN);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530719
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530720 tspi->cur_direction = 0;
721 if (t->rx_buf) {
722 command2 |= SLINK_RXEN;
723 tspi->cur_direction |= DATA_DIR_RX;
724 }
725 if (t->tx_buf) {
726 command2 |= SLINK_TXEN;
727 tspi->cur_direction |= DATA_DIR_TX;
728 }
Randolph Maaßen0e694df2019-03-26 15:30:50 +0100729
730 /*
731 * Writing to the command2 register bevore the command register prevents
732 * a spike in chip_select line 0. This selects the chip_select line
733 * before changing the chip_select value.
734 */
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530735 tegra_slink_writel(tspi, command2, SLINK_COMMAND2);
736 tspi->command2_reg = command2;
737
Randolph Maaßen0e694df2019-03-26 15:30:50 +0100738 tegra_slink_writel(tspi, command, SLINK_COMMAND);
739 tspi->command_reg = command;
740
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530741 if (total_fifo_words > SLINK_FIFO_DEPTH)
742 ret = tegra_slink_start_dma_based_transfer(tspi, t);
743 else
744 ret = tegra_slink_start_cpu_based_transfer(tspi, t);
745 return ret;
746}
747
748static int tegra_slink_setup(struct spi_device *spi)
749{
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100750 static const u32 cs_pol_bit[MAX_CHIP_SELECT] = {
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530751 SLINK_CS_POLARITY,
752 SLINK_CS_POLARITY1,
753 SLINK_CS_POLARITY2,
754 SLINK_CS_POLARITY3,
755 };
756
Michal Nazarewicz5fd38672013-12-08 16:35:10 +0100757 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
758 u32 val;
759 unsigned long flags;
760 int ret;
761
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530762 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
763 spi->bits_per_word,
764 spi->mode & SPI_CPOL ? "" : "~",
765 spi->mode & SPI_CPHA ? "" : "~",
766 spi->max_speed_hz);
767
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530768 ret = pm_runtime_get_sync(tspi->dev);
769 if (ret < 0) {
770 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
771 return ret;
772 }
773
774 spin_lock_irqsave(&tspi->lock, flags);
775 val = tspi->def_command_reg;
776 if (spi->mode & SPI_CS_HIGH)
777 val |= cs_pol_bit[spi->chip_select];
778 else
779 val &= ~cs_pol_bit[spi->chip_select];
780 tspi->def_command_reg = val;
781 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
782 spin_unlock_irqrestore(&tspi->lock, flags);
783
784 pm_runtime_put(tspi->dev);
785 return 0;
786}
787
Mark Brown63fc1842013-10-05 12:23:38 +0100788static int tegra_slink_prepare_message(struct spi_master *master,
789 struct spi_message *msg)
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530790{
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530791 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530792 struct spi_device *spi = msg->spi;
Mark Brown63fc1842013-10-05 12:23:38 +0100793
Mark Brownf178e3d2013-10-05 12:30:42 +0100794 tegra_slink_clear_status(tspi);
795
796 tspi->command_reg = tspi->def_command_reg;
797 tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE;
798
799 tspi->command2_reg = tspi->def_command2_reg;
800 tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select);
801
802 tspi->command_reg &= ~SLINK_MODES;
803 if (spi->mode & SPI_CPHA)
804 tspi->command_reg |= SLINK_CK_SDA;
805
806 if (spi->mode & SPI_CPOL)
807 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH;
808 else
809 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW;
Mark Brown63fc1842013-10-05 12:23:38 +0100810
811 return 0;
812}
813
814static int tegra_slink_transfer_one(struct spi_master *master,
815 struct spi_device *spi,
816 struct spi_transfer *xfer)
817{
818 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530819 int ret;
820
Wolfram Sang16735d02013-11-14 14:32:02 -0800821 reinit_completion(&tspi->xfer_completion);
Mark Brownf178e3d2013-10-05 12:30:42 +0100822 ret = tegra_slink_start_transfer_one(spi, xfer);
Mark Brown63fc1842013-10-05 12:23:38 +0100823 if (ret < 0) {
824 dev_err(tspi->dev,
825 "spi can not start transfer, err %d\n", ret);
826 return ret;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530827 }
Mark Brownf178e3d2013-10-05 12:30:42 +0100828
Mark Brown63fc1842013-10-05 12:23:38 +0100829 ret = wait_for_completion_timeout(&tspi->xfer_completion,
830 SLINK_DMA_TIMEOUT);
831 if (WARN_ON(ret == 0)) {
832 dev_err(tspi->dev,
Colin Ian Kingbfca7612017-04-23 18:14:36 +0100833 "spi transfer timeout, err %d\n", ret);
Mark Brown63fc1842013-10-05 12:23:38 +0100834 return -EIO;
835 }
836
837 if (tspi->tx_status)
838 return tspi->tx_status;
839 if (tspi->rx_status)
840 return tspi->rx_status;
841
842 return 0;
843}
844
845static int tegra_slink_unprepare_message(struct spi_master *master,
846 struct spi_message *msg)
847{
848 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
849
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530850 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
851 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
Mark Brown63fc1842013-10-05 12:23:38 +0100852
853 return 0;
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530854}
855
856static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
857{
858 struct spi_transfer *t = tspi->curr_xfer;
859 unsigned long flags;
860
861 spin_lock_irqsave(&tspi->lock, flags);
862 if (tspi->tx_status || tspi->rx_status ||
863 (tspi->status_reg & SLINK_BSY)) {
864 dev_err(tspi->dev,
865 "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg);
866 dev_err(tspi->dev,
867 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
868 tspi->command2_reg, tspi->dma_control_reg);
Stephen Warrenff2251e2013-11-06 16:31:24 -0700869 reset_control_assert(tspi->rst);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530870 udelay(2);
Stephen Warrenff2251e2013-11-06 16:31:24 -0700871 reset_control_deassert(tspi->rst);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530872 complete(&tspi->xfer_completion);
873 goto exit;
874 }
875
876 if (tspi->cur_direction & DATA_DIR_RX)
877 tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t);
878
879 if (tspi->cur_direction & DATA_DIR_TX)
880 tspi->cur_pos = tspi->cur_tx_pos;
881 else
882 tspi->cur_pos = tspi->cur_rx_pos;
883
884 if (tspi->cur_pos == t->len) {
885 complete(&tspi->xfer_completion);
886 goto exit;
887 }
888
889 tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
890 tegra_slink_start_cpu_based_transfer(tspi, t);
891exit:
892 spin_unlock_irqrestore(&tspi->lock, flags);
893 return IRQ_HANDLED;
894}
895
896static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
897{
898 struct spi_transfer *t = tspi->curr_xfer;
899 long wait_status;
900 int err = 0;
901 unsigned total_fifo_words;
902 unsigned long flags;
903
904 /* Abort dmas if any error */
905 if (tspi->cur_direction & DATA_DIR_TX) {
906 if (tspi->tx_status) {
907 dmaengine_terminate_all(tspi->tx_dma_chan);
908 err += 1;
909 } else {
910 wait_status = wait_for_completion_interruptible_timeout(
911 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
912 if (wait_status <= 0) {
913 dmaengine_terminate_all(tspi->tx_dma_chan);
914 dev_err(tspi->dev, "TxDma Xfer failed\n");
915 err += 1;
916 }
917 }
918 }
919
920 if (tspi->cur_direction & DATA_DIR_RX) {
921 if (tspi->rx_status) {
922 dmaengine_terminate_all(tspi->rx_dma_chan);
923 err += 2;
924 } else {
925 wait_status = wait_for_completion_interruptible_timeout(
926 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
927 if (wait_status <= 0) {
928 dmaengine_terminate_all(tspi->rx_dma_chan);
929 dev_err(tspi->dev, "RxDma Xfer failed\n");
930 err += 2;
931 }
932 }
933 }
934
935 spin_lock_irqsave(&tspi->lock, flags);
936 if (err) {
937 dev_err(tspi->dev,
938 "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg);
939 dev_err(tspi->dev,
940 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
941 tspi->command2_reg, tspi->dma_control_reg);
Stephen Warrenff2251e2013-11-06 16:31:24 -0700942 reset_control_assert(tspi->rst);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530943 udelay(2);
Stephen Warrenff2251e2013-11-06 16:31:24 -0700944 reset_control_assert(tspi->rst);
Laxman Dewangandc4dc362012-10-30 12:34:05 +0530945 complete(&tspi->xfer_completion);
946 spin_unlock_irqrestore(&tspi->lock, flags);
947 return IRQ_HANDLED;
948 }
949
950 if (tspi->cur_direction & DATA_DIR_RX)
951 tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
952
953 if (tspi->cur_direction & DATA_DIR_TX)
954 tspi->cur_pos = tspi->cur_tx_pos;
955 else
956 tspi->cur_pos = tspi->cur_rx_pos;
957
958 if (tspi->cur_pos == t->len) {
959 complete(&tspi->xfer_completion);
960 goto exit;
961 }
962
963 /* Continue transfer in current message */
964 total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi,
965 tspi, t);
966 if (total_fifo_words > SLINK_FIFO_DEPTH)
967 err = tegra_slink_start_dma_based_transfer(tspi, t);
968 else
969 err = tegra_slink_start_cpu_based_transfer(tspi, t);
970
971exit:
972 spin_unlock_irqrestore(&tspi->lock, flags);
973 return IRQ_HANDLED;
974}
975
976static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data)
977{
978 struct tegra_slink_data *tspi = context_data;
979
980 if (!tspi->is_curr_dma_xfer)
981 return handle_cpu_based_xfer(tspi);
982 return handle_dma_based_xfer(tspi);
983}
984
985static irqreturn_t tegra_slink_isr(int irq, void *context_data)
986{
987 struct tegra_slink_data *tspi = context_data;
988
989 tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS);
990 if (tspi->cur_direction & DATA_DIR_TX)
991 tspi->tx_status = tspi->status_reg &
992 (SLINK_TX_OVF | SLINK_TX_UNF);
993
994 if (tspi->cur_direction & DATA_DIR_RX)
995 tspi->rx_status = tspi->status_reg &
996 (SLINK_RX_OVF | SLINK_RX_UNF);
997 tegra_slink_clear_status(tspi);
998
999 return IRQ_WAKE_THREAD;
1000}
1001
Wei Yongjun8b0bebe2013-04-05 21:45:36 +08001002static const struct tegra_slink_chip_data tegra30_spi_cdata = {
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301003 .cs_hold_time = true,
1004};
1005
Wei Yongjun8b0bebe2013-04-05 21:45:36 +08001006static const struct tegra_slink_chip_data tegra20_spi_cdata = {
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301007 .cs_hold_time = false,
1008};
1009
Jingoo Hanb2fb1872014-05-07 16:52:36 +09001010static const struct of_device_id tegra_slink_of_match[] = {
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301011 { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, },
Laxman Dewangan24bc8972012-11-09 14:37:32 +05301012 { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, },
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301013 {}
1014};
1015MODULE_DEVICE_TABLE(of, tegra_slink_of_match);
1016
Grant Likelyfd4a3192012-12-07 16:57:14 +00001017static int tegra_slink_probe(struct platform_device *pdev)
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301018{
1019 struct spi_master *master;
1020 struct tegra_slink_data *tspi;
1021 struct resource *r;
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301022 int ret, spi_irq;
1023 const struct tegra_slink_chip_data *cdata = NULL;
1024 const struct of_device_id *match;
1025
Stephen Warrenc60fea02013-02-15 15:03:49 -07001026 match = of_match_device(tegra_slink_of_match, &pdev->dev);
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301027 if (!match) {
1028 dev_err(&pdev->dev, "Error: No device match found\n");
1029 return -ENODEV;
1030 }
1031 cdata = match->data;
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301032
1033 master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1034 if (!master) {
1035 dev_err(&pdev->dev, "master allocation failed\n");
1036 return -ENOMEM;
1037 }
1038
1039 /* the spi->mode bits understood by this driver: */
1040 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1041 master->setup = tegra_slink_setup;
Mark Brown63fc1842013-10-05 12:23:38 +01001042 master->prepare_message = tegra_slink_prepare_message;
1043 master->transfer_one = tegra_slink_transfer_one;
1044 master->unprepare_message = tegra_slink_unprepare_message;
Mark Brownce74ac82013-07-28 15:37:59 +01001045 master->auto_runtime_pm = true;
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301046 master->num_chipselect = MAX_CHIP_SELECT;
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301047
Jingoo Han24b5a822013-05-23 19:20:40 +09001048 platform_set_drvdata(pdev, master);
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301049 tspi = spi_master_get_devdata(master);
1050 tspi->master = master;
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301051 tspi->dev = &pdev->dev;
1052 tspi->chip_data = cdata;
1053 spin_lock_init(&tspi->lock);
1054
Axel Lin3c604de2014-02-10 21:51:13 +08001055 if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency",
1056 &master->max_speed_hz))
1057 master->max_speed_hz = 25000000; /* 25MHz */
Stephen Warrenc60fea02013-02-15 15:03:49 -07001058
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301059 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1060 if (!r) {
1061 dev_err(&pdev->dev, "No IO memory resource\n");
1062 ret = -ENODEV;
1063 goto exit_free_master;
1064 }
1065 tspi->phys = r->start;
Thierry Redingb0ee5602013-01-21 11:09:18 +01001066 tspi->base = devm_ioremap_resource(&pdev->dev, r);
1067 if (IS_ERR(tspi->base)) {
1068 ret = PTR_ERR(tspi->base);
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301069 goto exit_free_master;
1070 }
1071
Marcel Ziswiler7001cab2018-08-29 08:47:57 +02001072 /* disabled clock may cause interrupt storm upon request */
1073 tspi->clk = devm_clk_get(&pdev->dev, NULL);
1074 if (IS_ERR(tspi->clk)) {
1075 ret = PTR_ERR(tspi->clk);
1076 dev_err(&pdev->dev, "Can not get clock %d\n", ret);
1077 goto exit_free_master;
1078 }
1079 ret = clk_prepare(tspi->clk);
1080 if (ret < 0) {
1081 dev_err(&pdev->dev, "Clock prepare failed %d\n", ret);
1082 goto exit_free_master;
1083 }
1084 ret = clk_enable(tspi->clk);
1085 if (ret < 0) {
1086 dev_err(&pdev->dev, "Clock enable failed %d\n", ret);
1087 goto exit_free_master;
1088 }
1089
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301090 spi_irq = platform_get_irq(pdev, 0);
1091 tspi->irq = spi_irq;
1092 ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
1093 tegra_slink_isr_thread, IRQF_ONESHOT,
1094 dev_name(&pdev->dev), tspi);
1095 if (ret < 0) {
1096 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1097 tspi->irq);
Marcel Ziswiler7001cab2018-08-29 08:47:57 +02001098 goto exit_clk_disable;
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301099 }
1100
Philipp Zabel73b32752017-07-19 17:26:22 +02001101 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
Stephen Warrenff2251e2013-11-06 16:31:24 -07001102 if (IS_ERR(tspi->rst)) {
1103 dev_err(&pdev->dev, "can not get reset\n");
1104 ret = PTR_ERR(tspi->rst);
1105 goto exit_free_irq;
1106 }
1107
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301108 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1109 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301110
Stephen Warrena915d152013-11-11 13:13:47 -07001111 ret = tegra_slink_init_dma_param(tspi, true);
1112 if (ret < 0)
1113 goto exit_free_irq;
1114 ret = tegra_slink_init_dma_param(tspi, false);
1115 if (ret < 0)
1116 goto exit_rx_dma_free;
1117 tspi->max_buf_size = tspi->dma_buf_size;
1118 init_completion(&tspi->tx_dma_complete);
1119 init_completion(&tspi->rx_dma_complete);
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301120
1121 init_completion(&tspi->xfer_completion);
1122
1123 pm_runtime_enable(&pdev->dev);
1124 if (!pm_runtime_enabled(&pdev->dev)) {
1125 ret = tegra_slink_runtime_resume(&pdev->dev);
1126 if (ret)
1127 goto exit_pm_disable;
1128 }
1129
1130 ret = pm_runtime_get_sync(&pdev->dev);
1131 if (ret < 0) {
1132 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1133 goto exit_pm_disable;
1134 }
1135 tspi->def_command_reg = SLINK_M_S;
1136 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
1137 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
1138 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
1139 pm_runtime_put(&pdev->dev);
1140
1141 master->dev.of_node = pdev->dev.of_node;
Jingoo Han716db5d2013-09-24 13:51:32 +09001142 ret = devm_spi_register_master(&pdev->dev, master);
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301143 if (ret < 0) {
1144 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1145 goto exit_pm_disable;
1146 }
1147 return ret;
1148
1149exit_pm_disable:
1150 pm_runtime_disable(&pdev->dev);
1151 if (!pm_runtime_status_suspended(&pdev->dev))
1152 tegra_slink_runtime_suspend(&pdev->dev);
1153 tegra_slink_deinit_dma_param(tspi, false);
1154exit_rx_dma_free:
1155 tegra_slink_deinit_dma_param(tspi, true);
1156exit_free_irq:
1157 free_irq(spi_irq, tspi);
Marcel Ziswiler7001cab2018-08-29 08:47:57 +02001158exit_clk_disable:
1159 clk_disable(tspi->clk);
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301160exit_free_master:
1161 spi_master_put(master);
1162 return ret;
1163}
1164
Grant Likelyfd4a3192012-12-07 16:57:14 +00001165static int tegra_slink_remove(struct platform_device *pdev)
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301166{
Jingoo Han24b5a822013-05-23 19:20:40 +09001167 struct spi_master *master = platform_get_drvdata(pdev);
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301168 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1169
1170 free_irq(tspi->irq, tspi);
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301171
Marcel Ziswiler7001cab2018-08-29 08:47:57 +02001172 clk_disable(tspi->clk);
1173
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301174 if (tspi->tx_dma_chan)
1175 tegra_slink_deinit_dma_param(tspi, false);
1176
1177 if (tspi->rx_dma_chan)
1178 tegra_slink_deinit_dma_param(tspi, true);
1179
1180 pm_runtime_disable(&pdev->dev);
1181 if (!pm_runtime_status_suspended(&pdev->dev))
1182 tegra_slink_runtime_suspend(&pdev->dev);
1183
1184 return 0;
1185}
1186
1187#ifdef CONFIG_PM_SLEEP
1188static int tegra_slink_suspend(struct device *dev)
1189{
1190 struct spi_master *master = dev_get_drvdata(dev);
1191
1192 return spi_master_suspend(master);
1193}
1194
1195static int tegra_slink_resume(struct device *dev)
1196{
1197 struct spi_master *master = dev_get_drvdata(dev);
1198 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1199 int ret;
1200
1201 ret = pm_runtime_get_sync(dev);
1202 if (ret < 0) {
1203 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1204 return ret;
1205 }
1206 tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND);
1207 tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2);
1208 pm_runtime_put(dev);
1209
1210 return spi_master_resume(master);
1211}
1212#endif
1213
1214static int tegra_slink_runtime_suspend(struct device *dev)
1215{
1216 struct spi_master *master = dev_get_drvdata(dev);
1217 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1218
1219 /* Flush all write which are in PPSB queue by reading back */
1220 tegra_slink_readl(tspi, SLINK_MAS_DATA);
1221
1222 clk_disable_unprepare(tspi->clk);
1223 return 0;
1224}
1225
1226static int tegra_slink_runtime_resume(struct device *dev)
1227{
1228 struct spi_master *master = dev_get_drvdata(dev);
1229 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1230 int ret;
1231
1232 ret = clk_prepare_enable(tspi->clk);
1233 if (ret < 0) {
1234 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1235 return ret;
1236 }
1237 return 0;
1238}
1239
1240static const struct dev_pm_ops slink_pm_ops = {
1241 SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend,
1242 tegra_slink_runtime_resume, NULL)
1243 SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume)
1244};
1245static struct platform_driver tegra_slink_driver = {
1246 .driver = {
1247 .name = "spi-tegra-slink",
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301248 .pm = &slink_pm_ops,
Stephen Warrenc60fea02013-02-15 15:03:49 -07001249 .of_match_table = tegra_slink_of_match,
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301250 },
1251 .probe = tegra_slink_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +00001252 .remove = tegra_slink_remove,
Laxman Dewangandc4dc362012-10-30 12:34:05 +05301253};
1254module_platform_driver(tegra_slink_driver);
1255
1256MODULE_ALIAS("platform:spi-tegra-slink");
1257MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");
1258MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1259MODULE_LICENSE("GPL v2");