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Andy Gross71e88312011-12-05 19:19:21 -06001/*
Andy Gross71e88312011-12-05 19:19:21 -06002 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 * Author: Rob Clark <rob@ti.com>
4 * Andy Gross <andy.gross@ti.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
Andrew F. Davisbb5cdf82017-12-05 14:29:31 -060015
Andy Gross71e88312011-12-05 19:19:21 -060016#ifndef OMAP_DMM_PRIV_H
17#define OMAP_DMM_PRIV_H
18
19#define DMM_REVISION 0x000
20#define DMM_HWINFO 0x004
21#define DMM_LISA_HWINFO 0x008
22#define DMM_DMM_SYSCONFIG 0x010
23#define DMM_LISA_LOCK 0x01C
24#define DMM_LISA_MAP__0 0x040
25#define DMM_LISA_MAP__1 0x044
26#define DMM_TILER_HWINFO 0x208
27#define DMM_TILER_OR__0 0x220
28#define DMM_TILER_OR__1 0x224
29#define DMM_PAT_HWINFO 0x408
30#define DMM_PAT_GEOMETRY 0x40C
31#define DMM_PAT_CONFIG 0x410
32#define DMM_PAT_VIEW__0 0x420
33#define DMM_PAT_VIEW__1 0x424
34#define DMM_PAT_VIEW_MAP__0 0x440
35#define DMM_PAT_VIEW_MAP_BASE 0x460
36#define DMM_PAT_IRQ_EOI 0x478
37#define DMM_PAT_IRQSTATUS_RAW 0x480
38#define DMM_PAT_IRQSTATUS 0x490
39#define DMM_PAT_IRQENABLE_SET 0x4A0
40#define DMM_PAT_IRQENABLE_CLR 0x4B0
41#define DMM_PAT_STATUS__0 0x4C0
42#define DMM_PAT_STATUS__1 0x4C4
43#define DMM_PAT_STATUS__2 0x4C8
44#define DMM_PAT_STATUS__3 0x4CC
45#define DMM_PAT_DESCR__0 0x500
46#define DMM_PAT_DESCR__1 0x510
47#define DMM_PAT_DESCR__2 0x520
48#define DMM_PAT_DESCR__3 0x530
49#define DMM_PEG_HWINFO 0x608
50#define DMM_PEG_PRIO 0x620
51#define DMM_PEG_PRIO_PAT 0x640
52
53#define DMM_IRQSTAT_DST (1<<0)
54#define DMM_IRQSTAT_LST (1<<1)
55#define DMM_IRQSTAT_ERR_INV_DSC (1<<2)
56#define DMM_IRQSTAT_ERR_INV_DATA (1<<3)
57#define DMM_IRQSTAT_ERR_UPD_AREA (1<<4)
58#define DMM_IRQSTAT_ERR_UPD_CTRL (1<<5)
59#define DMM_IRQSTAT_ERR_UPD_DATA (1<<6)
60#define DMM_IRQSTAT_ERR_LUT_MISS (1<<7)
61
Peter Ujfalusib3d5a8d2017-09-29 14:49:46 +030062#define DMM_IRQSTAT_ERR_MASK (DMM_IRQSTAT_ERR_INV_DSC | \
63 DMM_IRQSTAT_ERR_INV_DATA | \
64 DMM_IRQSTAT_ERR_UPD_AREA | \
65 DMM_IRQSTAT_ERR_UPD_CTRL | \
66 DMM_IRQSTAT_ERR_UPD_DATA | \
67 DMM_IRQSTAT_ERR_LUT_MISS)
Andy Gross71e88312011-12-05 19:19:21 -060068
69#define DMM_PATSTATUS_READY (1<<0)
70#define DMM_PATSTATUS_VALID (1<<1)
71#define DMM_PATSTATUS_RUN (1<<2)
72#define DMM_PATSTATUS_DONE (1<<3)
73#define DMM_PATSTATUS_LINKED (1<<4)
74#define DMM_PATSTATUS_BYPASSED (1<<7)
75#define DMM_PATSTATUS_ERR_INV_DESCR (1<<10)
76#define DMM_PATSTATUS_ERR_INV_DATA (1<<11)
77#define DMM_PATSTATUS_ERR_UPD_AREA (1<<12)
78#define DMM_PATSTATUS_ERR_UPD_CTRL (1<<13)
79#define DMM_PATSTATUS_ERR_UPD_DATA (1<<14)
80#define DMM_PATSTATUS_ERR_ACCESS (1<<15)
81
Rob Clarka6a91822011-12-09 23:26:08 -060082/* note: don't treat DMM_PATSTATUS_ERR_ACCESS as an error */
Andy Gross71e88312011-12-05 19:19:21 -060083#define DMM_PATSTATUS_ERR (DMM_PATSTATUS_ERR_INV_DESCR | \
84 DMM_PATSTATUS_ERR_INV_DATA | \
85 DMM_PATSTATUS_ERR_UPD_AREA | \
86 DMM_PATSTATUS_ERR_UPD_CTRL | \
Rob Clarka6a91822011-12-09 23:26:08 -060087 DMM_PATSTATUS_ERR_UPD_DATA)
Andy Gross71e88312011-12-05 19:19:21 -060088
89
90
91enum {
92 PAT_STATUS,
93 PAT_DESCR
94};
95
96struct pat_ctrl {
97 u32 start:4;
98 u32 dir:4;
99 u32 lut_id:8;
100 u32 sync:12;
101 u32 ini:4;
102};
103
104struct pat {
Laurent Pinchartdfe9cfc2018-02-11 15:07:33 +0200105 u32 next_pa;
Andy Gross71e88312011-12-05 19:19:21 -0600106 struct pat_area area;
107 struct pat_ctrl ctrl;
Laurent Pinchartdfe9cfc2018-02-11 15:07:33 +0200108 u32 data_pa;
Andy Gross71e88312011-12-05 19:19:21 -0600109};
110
111#define DMM_FIXED_RETRY_COUNT 1000
112
113/* create refill buffer big enough to refill all slots, plus 3 descriptors..
114 * 3 descriptors is probably the worst-case for # of 2d-slices in a 1d area,
115 * but I guess you don't hit that worst case at the same time as full area
116 * refill
117 */
118#define DESCR_SIZE 128
119#define REFILL_BUFFER_SIZE ((4 * 128 * 256) + (3 * DESCR_SIZE))
120
Andy Gross238083a2012-12-19 14:53:38 -0600121/* For OMAP5, a fixed offset is added to all Y coordinates for 1D buffers.
122 * This is used in programming to address the upper portion of the LUT
123*/
124#define OMAP5_LUT_OFFSET 128
125
Andy Gross71e88312011-12-05 19:19:21 -0600126struct dmm;
127
128struct dmm_txn {
129 void *engine_handle;
130 struct tcm *tcm;
131
Laurent Pinchartdfe9cfc2018-02-11 15:07:33 +0200132 u8 *current_va;
Andy Gross71e88312011-12-05 19:19:21 -0600133 dma_addr_t current_pa;
134
135 struct pat *last_pat;
136};
137
138struct refill_engine {
139 int id;
140 struct dmm *dmm;
141 struct tcm *tcm;
142
Laurent Pinchartdfe9cfc2018-02-11 15:07:33 +0200143 u8 *refill_va;
Andy Gross71e88312011-12-05 19:19:21 -0600144 dma_addr_t refill_pa;
145
146 /* only one trans per engine for now */
147 struct dmm_txn txn;
148
Andy Grossfaaa0542012-10-12 11:18:11 -0500149 bool async;
150
Tomi Valkeinen74395072014-12-17 14:34:23 +0200151 struct completion compl;
Andy Gross71e88312011-12-05 19:19:21 -0600152
153 struct list_head idle_node;
154};
155
Tomi Valkeinen7cb0d6c2014-09-25 19:24:29 +0000156struct dmm_platform_data {
Laurent Pinchartdfe9cfc2018-02-11 15:07:33 +0200157 u32 cpu_cache_flags;
Tomi Valkeinen7cb0d6c2014-09-25 19:24:29 +0000158};
159
Andy Gross71e88312011-12-05 19:19:21 -0600160struct dmm {
161 struct device *dev;
162 void __iomem *base;
163 int irq;
164
165 struct page *dummy_page;
166 dma_addr_t dummy_pa;
167
168 void *refill_va;
169 dma_addr_t refill_pa;
170
171 /* refill engines */
Andy Grossfaaa0542012-10-12 11:18:11 -0500172 wait_queue_head_t engine_queue;
Andy Gross71e88312011-12-05 19:19:21 -0600173 struct list_head idle_head;
174 struct refill_engine *engines;
175 int num_engines;
Andy Grossfaaa0542012-10-12 11:18:11 -0500176 atomic_t engine_counter;
Andy Gross71e88312011-12-05 19:19:21 -0600177
178 /* container information */
179 int container_width;
180 int container_height;
181 int lut_width;
182 int lut_height;
183 int num_lut;
184
185 /* array of LUT - TCM containers */
186 struct tcm **tcm;
187
Andy Gross71e88312011-12-05 19:19:21 -0600188 /* allocation list and lock */
189 struct list_head alloc_head;
Tomi Valkeinen7cb0d6c2014-09-25 19:24:29 +0000190
191 const struct dmm_platform_data *plat_data;
Andy Gross71e88312011-12-05 19:19:21 -0600192};
193
194#endif