| Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Carlo Caione | d8a0091 | 2014-09-09 21:38:00 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2014 Carlo Caione |
| 4 | * Carlo Caione <carlo@caione.org> |
| Carlo Caione | d8a0091 | 2014-09-09 21:38:00 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #define MESON_AO_UART_WFIFO 0x0 |
| 8 | #define MESON_AO_UART_STATUS 0xc |
| 9 | |
| 10 | #define MESON_AO_UART_TX_FIFO_EMPTY (1 << 22) |
| 11 | #define MESON_AO_UART_TX_FIFO_FULL (1 << 21) |
| 12 | |
| 13 | .macro addruart, rp, rv, tmp |
| 14 | ldr \rp, =(CONFIG_DEBUG_UART_PHYS) @ physical |
| 15 | ldr \rv, =(CONFIG_DEBUG_UART_VIRT) @ virtual |
| 16 | .endm |
| 17 | |
| 18 | .macro senduart,rd,rx |
| 19 | str \rd, [\rx, #MESON_AO_UART_WFIFO] |
| 20 | .endm |
| 21 | |
| 22 | .macro busyuart,rd,rx |
| 23 | 1002: ldr \rd, [\rx, #MESON_AO_UART_STATUS] |
| 24 | tst \rd, #MESON_AO_UART_TX_FIFO_EMPTY |
| 25 | beq 1002b |
| 26 | .endm |
| 27 | |
| Linus Walleij | 2c50a57 | 2020-08-27 23:25:37 +0100 | [diff] [blame] | 28 | .macro waituartcts,rd,rx |
| 29 | .endm |
| 30 | |
| 31 | .macro waituarttxrdy,rd,rx |
| Carlo Caione | d8a0091 | 2014-09-09 21:38:00 +0200 | [diff] [blame] | 32 | 1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS] |
| 33 | tst \rd, #MESON_AO_UART_TX_FIFO_FULL |
| 34 | bne 1001b |
| 35 | .endm |
