David Gibson | 26ef5c0 | 2005-11-10 11:50:16 +1100 | [diff] [blame] | 1 | #ifndef _ASM_POWERPC_CACHE_H |
| 2 | #define _ASM_POWERPC_CACHE_H |
| 3 | |
| 4 | #ifdef __KERNEL__ |
| 5 | |
David Gibson | 26ef5c0 | 2005-11-10 11:50:16 +1100 | [diff] [blame] | 6 | |
| 7 | /* bytes per L1 cache line */ |
Christophe Leroy | 968159c | 2017-08-08 13:58:54 +0200 | [diff] [blame] | 8 | #if defined(CONFIG_PPC_8xx) || defined(CONFIG_403GCX) |
David Gibson | 26ef5c0 | 2005-11-10 11:50:16 +1100 | [diff] [blame] | 9 | #define L1_CACHE_SHIFT 4 |
| 10 | #define MAX_COPY_PREFETCH 1 |
Kumar Gala | 3dfa877 | 2008-06-16 09:41:32 -0500 | [diff] [blame] | 11 | #elif defined(CONFIG_PPC_E500MC) |
| 12 | #define L1_CACHE_SHIFT 6 |
| 13 | #define MAX_COPY_PREFETCH 4 |
David Gibson | 26ef5c0 | 2005-11-10 11:50:16 +1100 | [diff] [blame] | 14 | #elif defined(CONFIG_PPC32) |
David Gibson | 26ef5c0 | 2005-11-10 11:50:16 +1100 | [diff] [blame] | 15 | #define MAX_COPY_PREFETCH 4 |
Dave Kleikamp | e7f75ad | 2010-03-05 10:43:12 +0000 | [diff] [blame] | 16 | #if defined(CONFIG_PPC_47x) |
| 17 | #define L1_CACHE_SHIFT 7 |
| 18 | #else |
| 19 | #define L1_CACHE_SHIFT 5 |
| 20 | #endif |
David Gibson | 26ef5c0 | 2005-11-10 11:50:16 +1100 | [diff] [blame] | 21 | #else /* CONFIG_PPC64 */ |
| 22 | #define L1_CACHE_SHIFT 7 |
Nicholas Piggin | f4329f2 | 2016-10-13 14:43:52 +1100 | [diff] [blame] | 23 | #define IFETCH_ALIGN_SHIFT 4 /* POWER8,9 */ |
David Gibson | 26ef5c0 | 2005-11-10 11:50:16 +1100 | [diff] [blame] | 24 | #endif |
| 25 | |
| 26 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
| 27 | |
| 28 | #define SMP_CACHE_BYTES L1_CACHE_BYTES |
David Gibson | 26ef5c0 | 2005-11-10 11:50:16 +1100 | [diff] [blame] | 29 | |
Nicholas Piggin | f4329f2 | 2016-10-13 14:43:52 +1100 | [diff] [blame] | 30 | #define IFETCH_ALIGN_BYTES (1 << IFETCH_ALIGN_SHIFT) |
| 31 | |
David Gibson | 26ef5c0 | 2005-11-10 11:50:16 +1100 | [diff] [blame] | 32 | #if defined(__powerpc64__) && !defined(__ASSEMBLY__) |
Benjamin Herrenschmidt | e2827fe | 2017-01-08 17:31:47 -0600 | [diff] [blame] | 33 | |
| 34 | struct ppc_cache_info { |
| 35 | u32 size; |
| 36 | u32 line_size; |
| 37 | u32 block_size; /* L1 only */ |
| 38 | u32 log_block_size; |
| 39 | u32 blocks_per_page; |
| 40 | u32 sets; |
Benjamin Herrenschmidt | 98a5f36 | 2017-02-03 17:20:07 +1100 | [diff] [blame] | 41 | u32 assoc; |
Benjamin Herrenschmidt | e2827fe | 2017-01-08 17:31:47 -0600 | [diff] [blame] | 42 | }; |
| 43 | |
David Gibson | 26ef5c0 | 2005-11-10 11:50:16 +1100 | [diff] [blame] | 44 | struct ppc64_caches { |
Benjamin Herrenschmidt | e2827fe | 2017-01-08 17:31:47 -0600 | [diff] [blame] | 45 | struct ppc_cache_info l1d; |
| 46 | struct ppc_cache_info l1i; |
Benjamin Herrenschmidt | 65e01f3 | 2017-01-08 17:31:48 -0600 | [diff] [blame] | 47 | struct ppc_cache_info l2; |
| 48 | struct ppc_cache_info l3; |
David Gibson | 26ef5c0 | 2005-11-10 11:50:16 +1100 | [diff] [blame] | 49 | }; |
| 50 | |
| 51 | extern struct ppc64_caches ppc64_caches; |
| 52 | #endif /* __powerpc64__ && ! __ASSEMBLY__ */ |
| 53 | |
Kevin Hao | 0ce6367 | 2013-08-22 09:30:35 +0800 | [diff] [blame] | 54 | #if defined(__ASSEMBLY__) |
| 55 | /* |
| 56 | * For a snooping icache, we still need a dummy icbi to purge all the |
| 57 | * prefetched instructions from the ifetch buffers. We also need a sync |
| 58 | * before the icbi to order the the actual stores to memory that might |
| 59 | * have modified instructions with the icbi. |
| 60 | */ |
| 61 | #define PURGE_PREFETCHED_INS \ |
| 62 | sync; \ |
| 63 | icbi 0,r3; \ |
| 64 | sync; \ |
| 65 | isync |
David Howells | ae3a197e | 2012-03-28 18:30:02 +0100 | [diff] [blame] | 66 | |
Kevin Hao | 0ce6367 | 2013-08-22 09:30:35 +0800 | [diff] [blame] | 67 | #else |
Denys Vlasenko | 54cb27a | 2010-02-20 01:03:44 +0100 | [diff] [blame] | 68 | #define __read_mostly __attribute__((__section__(".data..read_mostly"))) |
David Howells | ae3a197e | 2012-03-28 18:30:02 +0100 | [diff] [blame] | 69 | |
| 70 | #ifdef CONFIG_6xx |
| 71 | extern long _get_L2CR(void); |
| 72 | extern long _get_L3CR(void); |
| 73 | extern void _set_L2CR(unsigned long); |
| 74 | extern void _set_L3CR(unsigned long); |
| 75 | #else |
| 76 | #define _get_L2CR() 0L |
| 77 | #define _get_L3CR() 0L |
| 78 | #define _set_L2CR(val) do { } while(0) |
| 79 | #define _set_L3CR(val) do { } while(0) |
Tony Breeds | bd67fcf | 2007-07-04 14:04:31 +1000 | [diff] [blame] | 80 | #endif |
| 81 | |
Christophe Leroy | d6bfa02 | 2016-02-09 17:08:23 +0100 | [diff] [blame] | 82 | static inline void dcbz(void *addr) |
| 83 | { |
| 84 | __asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory"); |
| 85 | } |
| 86 | |
| 87 | static inline void dcbi(void *addr) |
| 88 | { |
| 89 | __asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory"); |
| 90 | } |
| 91 | |
| 92 | static inline void dcbf(void *addr) |
| 93 | { |
| 94 | __asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory"); |
| 95 | } |
| 96 | |
| 97 | static inline void dcbst(void *addr) |
| 98 | { |
| 99 | __asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory"); |
| 100 | } |
David Howells | ae3a197e | 2012-03-28 18:30:02 +0100 | [diff] [blame] | 101 | #endif /* !__ASSEMBLY__ */ |
David Gibson | 26ef5c0 | 2005-11-10 11:50:16 +1100 | [diff] [blame] | 102 | #endif /* __KERNEL__ */ |
| 103 | #endif /* _ASM_POWERPC_CACHE_H */ |