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Jiaxun Yang632dcc22020-05-28 23:27:53 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
4 * Loongson PCH MSI support
5 */
6
7#define pr_fmt(fmt) "pch-msi: " fmt
8
9#include <linux/irqchip.h>
10#include <linux/msi.h>
11#include <linux/of.h>
12#include <linux/of_address.h>
13#include <linux/of_irq.h>
14#include <linux/of_pci.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17
Huacai Chen02308732022-07-20 18:51:28 +080018static int nr_pics;
19
Jiaxun Yang632dcc22020-05-28 23:27:53 +080020struct pch_msi_data {
21 struct mutex msi_map_lock;
22 phys_addr_t doorbell;
23 u32 irq_first; /* The vector number that MSIs starts */
24 u32 num_irqs; /* The number of vectors for MSIs */
25 unsigned long *msi_map;
26};
27
Huacai Chen02308732022-07-20 18:51:28 +080028static struct fwnode_handle *pch_msi_handle[MAX_IO_PICS];
29
Jiaxun Yang632dcc22020-05-28 23:27:53 +080030static void pch_msi_mask_msi_irq(struct irq_data *d)
31{
32 pci_msi_mask_irq(d);
33 irq_chip_mask_parent(d);
34}
35
36static void pch_msi_unmask_msi_irq(struct irq_data *d)
37{
38 irq_chip_unmask_parent(d);
39 pci_msi_unmask_irq(d);
40}
41
42static struct irq_chip pch_msi_irq_chip = {
43 .name = "PCH PCI MSI",
44 .irq_mask = pch_msi_mask_msi_irq,
45 .irq_unmask = pch_msi_unmask_msi_irq,
46 .irq_ack = irq_chip_ack_parent,
47 .irq_set_affinity = irq_chip_set_affinity_parent,
48};
49
50static int pch_msi_allocate_hwirq(struct pch_msi_data *priv, int num_req)
51{
52 int first;
53
54 mutex_lock(&priv->msi_map_lock);
55
56 first = bitmap_find_free_region(priv->msi_map, priv->num_irqs,
57 get_count_order(num_req));
58 if (first < 0) {
59 mutex_unlock(&priv->msi_map_lock);
60 return -ENOSPC;
61 }
62
63 mutex_unlock(&priv->msi_map_lock);
64
65 return priv->irq_first + first;
66}
67
68static void pch_msi_free_hwirq(struct pch_msi_data *priv,
69 int hwirq, int num_req)
70{
71 int first = hwirq - priv->irq_first;
72
73 mutex_lock(&priv->msi_map_lock);
74 bitmap_release_region(priv->msi_map, first, get_count_order(num_req));
75 mutex_unlock(&priv->msi_map_lock);
76}
77
78static void pch_msi_compose_msi_msg(struct irq_data *data,
79 struct msi_msg *msg)
80{
81 struct pch_msi_data *priv = irq_data_get_irq_chip_data(data);
82
83 msg->address_hi = upper_32_bits(priv->doorbell);
84 msg->address_lo = lower_32_bits(priv->doorbell);
85 msg->data = data->hwirq;
86}
87
88static struct msi_domain_info pch_msi_domain_info = {
89 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
90 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
91 .chip = &pch_msi_irq_chip,
92};
93
94static struct irq_chip middle_irq_chip = {
95 .name = "PCH MSI",
96 .irq_mask = irq_chip_mask_parent,
97 .irq_unmask = irq_chip_unmask_parent,
98 .irq_ack = irq_chip_ack_parent,
99 .irq_set_affinity = irq_chip_set_affinity_parent,
100 .irq_compose_msi_msg = pch_msi_compose_msi_msg,
101};
102
103static int pch_msi_parent_domain_alloc(struct irq_domain *domain,
104 unsigned int virq, int hwirq)
105{
106 struct irq_fwspec fwspec;
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800107
108 fwspec.fwnode = domain->parent->fwnode;
109 fwspec.param_count = 1;
110 fwspec.param[0] = hwirq;
111
Tiezhu Yangb10cbca2020-07-07 10:12:50 +0800112 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800113}
114
115static int pch_msi_middle_domain_alloc(struct irq_domain *domain,
116 unsigned int virq,
117 unsigned int nr_irqs, void *args)
118{
119 struct pch_msi_data *priv = domain->host_data;
120 int hwirq, err, i;
121
122 hwirq = pch_msi_allocate_hwirq(priv, nr_irqs);
123 if (hwirq < 0)
124 return hwirq;
125
126 for (i = 0; i < nr_irqs; i++) {
127 err = pch_msi_parent_domain_alloc(domain, virq + i, hwirq + i);
128 if (err)
129 goto err_hwirq;
130
131 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
132 &middle_irq_chip, priv);
133 }
134
135 return 0;
136
137err_hwirq:
138 pch_msi_free_hwirq(priv, hwirq, nr_irqs);
139 irq_domain_free_irqs_parent(domain, virq, i - 1);
140
141 return err;
142}
143
144static void pch_msi_middle_domain_free(struct irq_domain *domain,
145 unsigned int virq,
146 unsigned int nr_irqs)
147{
148 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
149 struct pch_msi_data *priv = irq_data_get_irq_chip_data(d);
150
151 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
152 pch_msi_free_hwirq(priv, d->hwirq, nr_irqs);
153}
154
155static const struct irq_domain_ops pch_msi_middle_domain_ops = {
156 .alloc = pch_msi_middle_domain_alloc,
157 .free = pch_msi_middle_domain_free,
158};
159
160static int pch_msi_init_domains(struct pch_msi_data *priv,
Huacai Chen02308732022-07-20 18:51:28 +0800161 struct irq_domain *parent,
162 struct fwnode_handle *domain_handle)
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800163{
164 struct irq_domain *middle_domain, *msi_domain;
165
Huacai Chen02308732022-07-20 18:51:28 +0800166 middle_domain = irq_domain_create_linear(domain_handle,
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800167 priv->num_irqs,
168 &pch_msi_middle_domain_ops,
169 priv);
170 if (!middle_domain) {
171 pr_err("Failed to create the MSI middle domain\n");
172 return -ENOMEM;
173 }
174
175 middle_domain->parent = parent;
176 irq_domain_update_bus_token(middle_domain, DOMAIN_BUS_NEXUS);
177
Huacai Chen02308732022-07-20 18:51:28 +0800178 msi_domain = pci_msi_create_irq_domain(domain_handle,
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800179 &pch_msi_domain_info,
180 middle_domain);
181 if (!msi_domain) {
182 pr_err("Failed to create PCI MSI domain\n");
183 irq_domain_remove(middle_domain);
184 return -ENOMEM;
185 }
186
187 return 0;
188}
189
Huacai Chen02308732022-07-20 18:51:28 +0800190static int pch_msi_init(phys_addr_t msg_address, int irq_base, int irq_count,
191 struct irq_domain *parent_domain, struct fwnode_handle *domain_handle)
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800192{
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800193 int ret;
Huacai Chen02308732022-07-20 18:51:28 +0800194 struct pch_msi_data *priv;
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800195
196 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
197 if (!priv)
198 return -ENOMEM;
199
200 mutex_init(&priv->msi_map_lock);
201
Huacai Chen02308732022-07-20 18:51:28 +0800202 priv->doorbell = msg_address;
203 priv->irq_first = irq_base;
204 priv->num_irqs = irq_count;
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800205
Huacai Chenc1f664d2021-02-09 15:10:51 +0800206 priv->msi_map = bitmap_zalloc(priv->num_irqs, GFP_KERNEL);
Huacai Chen02308732022-07-20 18:51:28 +0800207 if (!priv->msi_map)
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800208 goto err_priv;
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800209
210 pr_debug("Registering %d MSIs, starting at %d\n",
211 priv->num_irqs, priv->irq_first);
212
Huacai Chen02308732022-07-20 18:51:28 +0800213 ret = pch_msi_init_domains(priv, parent_domain, domain_handle);
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800214 if (ret)
215 goto err_map;
216
Huacai Chen02308732022-07-20 18:51:28 +0800217 pch_msi_handle[nr_pics++] = domain_handle;
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800218 return 0;
219
220err_map:
Christophe JAILLETc831d922021-12-26 15:46:21 +0100221 bitmap_free(priv->msi_map);
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800222err_priv:
223 kfree(priv);
Huacai Chen02308732022-07-20 18:51:28 +0800224
225 return -EINVAL;
Jiaxun Yang632dcc22020-05-28 23:27:53 +0800226}
227
Huacai Chen02308732022-07-20 18:51:28 +0800228#ifdef CONFIG_OF
229static int pch_msi_of_init(struct device_node *node, struct device_node *parent)
230{
231 int err;
232 int irq_base, irq_count;
233 struct resource res;
234 struct irq_domain *parent_domain;
235
236 parent_domain = irq_find_host(parent);
237 if (!parent_domain) {
238 pr_err("Failed to find the parent domain\n");
239 return -ENXIO;
240 }
241
242 if (of_address_to_resource(node, 0, &res)) {
243 pr_err("Failed to allocate resource\n");
244 return -EINVAL;
245 }
246
247 if (of_property_read_u32(node, "loongson,msi-base-vec", &irq_base)) {
248 pr_err("Unable to parse MSI vec base\n");
249 return -EINVAL;
250 }
251
252 if (of_property_read_u32(node, "loongson,msi-num-vecs", &irq_count)) {
253 pr_err("Unable to parse MSI vec number\n");
254 return -EINVAL;
255 }
256
257 err = pch_msi_init(res.start, irq_base, irq_count, parent_domain, of_node_to_fwnode(node));
258 if (err < 0)
259 return err;
260
261 return 0;
262}
263
264IRQCHIP_DECLARE(pch_msi, "loongson,pch-msi-1.0", pch_msi_of_init);
265#endif
266
267#ifdef CONFIG_ACPI
268struct fwnode_handle *get_pch_msi_handle(int pci_segment)
269{
270 int i;
271
272 for (i = 0; i < MAX_IO_PICS; i++) {
273 if (msi_group[i].pci_segment == pci_segment)
274 return pch_msi_handle[i];
275 }
276 return NULL;
277}
278
279int __init pch_msi_acpi_init(struct irq_domain *parent,
280 struct acpi_madt_msi_pic *acpi_pchmsi)
281{
282 int ret;
283 struct fwnode_handle *domain_handle;
284
285 domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_pchmsi);
286 ret = pch_msi_init(acpi_pchmsi->msg_address, acpi_pchmsi->start,
287 acpi_pchmsi->count, parent, domain_handle);
288 if (ret < 0)
289 irq_domain_free_fwnode(domain_handle);
290
291 return ret;
292}
293#endif