Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 1 | /* |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 2 | * This program is free software; you can distribute it and/or modify it |
| 3 | * under the terms of the GNU General Public License (Version 2) as |
| 4 | * published by the Free Software Foundation. |
| 5 | * |
| 6 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 7 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 8 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 9 | * for more details. |
| 10 | * |
| 11 | * You should have received a copy of the GNU General Public License along |
| 12 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 13 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 14 | * |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 15 | * Copyright (C) 2004, 05, 06 MIPS Technologies, Inc. |
| 16 | * Elizabeth Clarke (beth@mips.com) |
| 17 | * Ralf Baechle (ralf@linux-mips.org) |
| 18 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 19 | */ |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/sched.h> |
| 22 | #include <linux/cpumask.h> |
| 23 | #include <linux/interrupt.h> |
Andrew Bresticker | 4060bbe | 2014-10-20 12:03:53 -0700 | [diff] [blame] | 24 | #include <linux/irqchip/mips-gic.h> |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 25 | #include <linux/compiler.h> |
Ralf Baechle | 0ab7aef | 2007-03-02 20:42:04 +0000 | [diff] [blame] | 26 | #include <linux/smp.h> |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 27 | |
Arun Sharma | 60063497 | 2011-07-26 16:09:06 -0700 | [diff] [blame] | 28 | #include <linux/atomic.h> |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 29 | #include <asm/cacheflush.h> |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 30 | #include <asm/cpu.h> |
| 31 | #include <asm/processor.h> |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 32 | #include <asm/hardirq.h> |
| 33 | #include <asm/mmu_context.h> |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 34 | #include <asm/time.h> |
| 35 | #include <asm/mipsregs.h> |
| 36 | #include <asm/mipsmtregs.h> |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 37 | #include <asm/mips_mt.h> |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 38 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 39 | static void __init smvp_copy_vpe_config(void) |
Ralf Baechle | 781b0f8 | 2006-10-31 18:25:10 +0000 | [diff] [blame] | 40 | { |
| 41 | write_vpe_c0_status( |
| 42 | (read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0); |
| 43 | |
| 44 | /* set config to be the same as vpe0, particularly kseg0 coherency alg */ |
| 45 | write_vpe_c0_config( read_c0_config()); |
| 46 | |
| 47 | /* make sure there are no software interrupts pending */ |
| 48 | write_vpe_c0_cause(0); |
| 49 | |
| 50 | /* Propagate Config7 */ |
| 51 | write_vpe_c0_config7(read_c0_config7()); |
Ralf Baechle | 70e46f4 | 2006-10-31 18:33:09 +0000 | [diff] [blame] | 52 | |
| 53 | write_vpe_c0_count(read_c0_count()); |
Ralf Baechle | 781b0f8 | 2006-10-31 18:25:10 +0000 | [diff] [blame] | 54 | } |
| 55 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 56 | static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0, |
Ralf Baechle | 781b0f8 | 2006-10-31 18:25:10 +0000 | [diff] [blame] | 57 | unsigned int ncpu) |
| 58 | { |
| 59 | if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) |
| 60 | return ncpu; |
| 61 | |
| 62 | /* Deactivate all but VPE 0 */ |
| 63 | if (tc != 0) { |
| 64 | unsigned long tmp = read_vpe_c0_vpeconf0(); |
| 65 | |
| 66 | tmp &= ~VPECONF0_VPA; |
| 67 | |
| 68 | /* master VPE */ |
| 69 | tmp |= VPECONF0_MVP; |
| 70 | write_vpe_c0_vpeconf0(tmp); |
| 71 | |
| 72 | /* Record this as available CPU */ |
Rusty Russell | 4037ac6 | 2009-09-24 09:34:47 -0600 | [diff] [blame] | 73 | set_cpu_possible(tc, true); |
Markos Chandras | c2c2a64 | 2013-10-09 16:16:25 +0100 | [diff] [blame] | 74 | set_cpu_present(tc, true); |
Ralf Baechle | 781b0f8 | 2006-10-31 18:25:10 +0000 | [diff] [blame] | 75 | __cpu_number_map[tc] = ++ncpu; |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 76 | __cpu_logical_map[ncpu] = tc; |
Ralf Baechle | 781b0f8 | 2006-10-31 18:25:10 +0000 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | /* Disable multi-threading with TC's */ |
| 80 | write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); |
| 81 | |
| 82 | if (tc != 0) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 83 | smvp_copy_vpe_config(); |
Ralf Baechle | 781b0f8 | 2006-10-31 18:25:10 +0000 | [diff] [blame] | 84 | |
| 85 | return ncpu; |
| 86 | } |
| 87 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 88 | static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0) |
Ralf Baechle | 781b0f8 | 2006-10-31 18:25:10 +0000 | [diff] [blame] | 89 | { |
| 90 | unsigned long tmp; |
| 91 | |
| 92 | if (!tc) |
| 93 | return; |
| 94 | |
| 95 | /* bind a TC to each VPE, May as well put all excess TC's |
| 96 | on the last VPE */ |
| 97 | if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1)) |
| 98 | write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)); |
| 99 | else { |
| 100 | write_tc_c0_tcbind(read_tc_c0_tcbind() | tc); |
| 101 | |
| 102 | /* and set XTC */ |
| 103 | write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT)); |
| 104 | } |
| 105 | |
| 106 | tmp = read_tc_c0_tcstatus(); |
| 107 | |
| 108 | /* mark not allocated and not dynamically allocatable */ |
| 109 | tmp &= ~(TCSTATUS_A | TCSTATUS_DA); |
| 110 | tmp |= TCSTATUS_IXMT; /* interrupt exempt */ |
| 111 | write_tc_c0_tcstatus(tmp); |
| 112 | |
| 113 | write_tc_c0_tchalt(TCHALT_H); |
| 114 | } |
| 115 | |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 116 | static void vsmp_send_ipi_single(int cpu, unsigned int action) |
| 117 | { |
| 118 | int i; |
| 119 | unsigned long flags; |
| 120 | int vpflags; |
| 121 | |
Andrew Bresticker | 8a19b8f | 2014-09-18 14:47:19 -0700 | [diff] [blame] | 122 | #ifdef CONFIG_MIPS_GIC |
Steven J. Hill | 5cf8b24 | 2013-10-09 16:47:23 +0100 | [diff] [blame] | 123 | if (gic_present) { |
Paul Burton | 0c2cb00 | 2014-03-24 10:19:31 +0000 | [diff] [blame] | 124 | gic_send_ipi_single(cpu, action); |
Steven J. Hill | 5cf8b24 | 2013-10-09 16:47:23 +0100 | [diff] [blame] | 125 | return; |
| 126 | } |
| 127 | #endif |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 128 | local_irq_save(flags); |
| 129 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 130 | vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */ |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 131 | |
| 132 | switch (action) { |
| 133 | case SMP_CALL_FUNCTION: |
| 134 | i = C_SW1; |
| 135 | break; |
| 136 | |
| 137 | case SMP_RESCHEDULE_YOURSELF: |
| 138 | default: |
| 139 | i = C_SW0; |
| 140 | break; |
| 141 | } |
| 142 | |
| 143 | /* 1:1 mapping of vpe and tc... */ |
| 144 | settc(cpu); |
| 145 | write_vpe_c0_cause(read_vpe_c0_cause() | i); |
| 146 | evpe(vpflags); |
| 147 | |
| 148 | local_irq_restore(flags); |
| 149 | } |
| 150 | |
Rusty Russell | 48a048f | 2009-09-24 09:34:44 -0600 | [diff] [blame] | 151 | static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 152 | { |
| 153 | unsigned int i; |
| 154 | |
Rusty Russell | 48a048f | 2009-09-24 09:34:44 -0600 | [diff] [blame] | 155 | for_each_cpu(i, mask) |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 156 | vsmp_send_ipi_single(i, action); |
| 157 | } |
| 158 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 159 | static void vsmp_init_secondary(void) |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 160 | { |
Andrew Bresticker | 8a19b8f | 2014-09-18 14:47:19 -0700 | [diff] [blame] | 161 | #ifdef CONFIG_MIPS_GIC |
Ralf Baechle | d002aaa | 2010-12-01 17:33:17 +0000 | [diff] [blame] | 162 | /* This is Malta specific: IPI,performance and timer interrupts */ |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 163 | if (gic_present) |
James Hogan | c3f134f | 2015-01-16 11:10:46 +0000 | [diff] [blame] | 164 | change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | |
| 165 | STATUSF_IP4 | STATUSF_IP5 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 166 | STATUSF_IP6 | STATUSF_IP7); |
| 167 | else |
Anoop P A | 1c599242 | 2011-01-25 19:27:26 +0530 | [diff] [blame] | 168 | #endif |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 169 | change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 | |
| 170 | STATUSF_IP6 | STATUSF_IP7); |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 171 | } |
| 172 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 173 | static void vsmp_smp_finish(void) |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 174 | { |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 175 | /* CDFIXME: remove this? */ |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 176 | write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); |
| 177 | |
| 178 | #ifdef CONFIG_MIPS_MT_FPAFF |
| 179 | /* If we have an FPU, enroll ourselves in the FPU-full mask */ |
| 180 | if (cpu_has_fpu) |
Rusty Russell | 8dd9289 | 2015-03-05 10:49:17 +1030 | [diff] [blame] | 181 | cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask); |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 182 | #endif /* CONFIG_MIPS_MT_FPAFF */ |
| 183 | |
| 184 | local_irq_enable(); |
| 185 | } |
| 186 | |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 187 | /* |
| 188 | * Setup the PC, SP, and GP of a secondary processor and start it |
| 189 | * running! |
| 190 | * smp_bootstrap is the place to resume from |
| 191 | * __KSTK_TOS(idle) is apparently the stack pointer |
| 192 | * (unsigned long)idle->thread_info the gp |
| 193 | * assumes a 1:1 mapping of TC => VPE |
| 194 | */ |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 195 | static void vsmp_boot_secondary(int cpu, struct task_struct *idle) |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 196 | { |
| 197 | struct thread_info *gp = task_thread_info(idle); |
| 198 | dvpe(); |
| 199 | set_c0_mvpcontrol(MVPCONTROL_VPC); |
| 200 | |
| 201 | settc(cpu); |
| 202 | |
| 203 | /* restart */ |
| 204 | write_tc_c0_tcrestart((unsigned long)&smp_bootstrap); |
| 205 | |
| 206 | /* enable the tc this vpe/cpu will be running */ |
| 207 | write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A); |
| 208 | |
| 209 | write_tc_c0_tchalt(0); |
| 210 | |
| 211 | /* enable the VPE */ |
| 212 | write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); |
| 213 | |
| 214 | /* stack pointer */ |
| 215 | write_tc_gpr_sp( __KSTK_TOS(idle)); |
| 216 | |
| 217 | /* global pointer */ |
| 218 | write_tc_gpr_gp((unsigned long)gp); |
| 219 | |
| 220 | flush_icache_range((unsigned long)gp, |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 221 | (unsigned long)(gp + sizeof(struct thread_info))); |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 222 | |
| 223 | /* finally out of configuration and into chaos */ |
| 224 | clear_c0_mvpcontrol(MVPCONTROL_VPC); |
| 225 | |
| 226 | evpe(EVPE_ENABLE); |
| 227 | } |
| 228 | |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 229 | /* |
| 230 | * Common setup before any secondaries are started |
| 231 | * Make sure all CPU's are in a sensible state before we boot any of the |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 232 | * secondaries |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 233 | */ |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 234 | static void __init vsmp_smp_setup(void) |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 235 | { |
Ralf Baechle | 781b0f8 | 2006-10-31 18:25:10 +0000 | [diff] [blame] | 236 | unsigned int mvpconf0, ntc, tc, ncpu = 0; |
Ralf Baechle | 0ab7aef | 2007-03-02 20:42:04 +0000 | [diff] [blame] | 237 | unsigned int nvpe; |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 238 | |
Ralf Baechle | f088fc8 | 2006-04-05 09:45:47 +0100 | [diff] [blame] | 239 | #ifdef CONFIG_MIPS_MT_FPAFF |
| 240 | /* If we have an FPU, enroll ourselves in the FPU-full mask */ |
| 241 | if (cpu_has_fpu) |
Rusty Russell | 8dd9289 | 2015-03-05 10:49:17 +1030 | [diff] [blame] | 242 | cpumask_set_cpu(0, &mt_fpu_cpumask); |
Ralf Baechle | f088fc8 | 2006-04-05 09:45:47 +0100 | [diff] [blame] | 243 | #endif /* CONFIG_MIPS_MT_FPAFF */ |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 244 | if (!cpu_has_mipsmt) |
| 245 | return; |
| 246 | |
| 247 | /* disable MT so we can configure */ |
| 248 | dvpe(); |
| 249 | dmt(); |
| 250 | |
| 251 | /* Put MVPE's into 'configuration state' */ |
| 252 | set_c0_mvpcontrol(MVPCONTROL_VPC); |
| 253 | |
Ralf Baechle | 781b0f8 | 2006-10-31 18:25:10 +0000 | [diff] [blame] | 254 | mvpconf0 = read_c0_mvpconf0(); |
| 255 | ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT; |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 256 | |
Ralf Baechle | 0ab7aef | 2007-03-02 20:42:04 +0000 | [diff] [blame] | 257 | nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; |
| 258 | smp_num_siblings = nvpe; |
| 259 | |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 260 | /* we'll always have more TC's than VPE's, so loop setting everything |
| 261 | to a sensible state */ |
Ralf Baechle | 781b0f8 | 2006-10-31 18:25:10 +0000 | [diff] [blame] | 262 | for (tc = 0; tc <= ntc; tc++) { |
| 263 | settc(tc); |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 264 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 265 | smvp_tc_init(tc, mvpconf0); |
| 266 | ncpu = smvp_vpe_init(tc, mvpconf0, ncpu); |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 267 | } |
| 268 | |
| 269 | /* Release config state */ |
| 270 | clear_c0_mvpcontrol(MVPCONTROL_VPC); |
| 271 | |
| 272 | /* We'll wait until starting the secondaries before starting MVPE */ |
| 273 | |
Ralf Baechle | 781b0f8 | 2006-10-31 18:25:10 +0000 | [diff] [blame] | 274 | printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 275 | } |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 276 | |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 277 | static void __init vsmp_prepare_cpus(unsigned int max_cpus) |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 278 | { |
Ralf Baechle | 8c976e3 | 2007-07-03 18:25:58 +0200 | [diff] [blame] | 279 | mips_mt_set_cpuoptions(); |
Ralf Baechle | 340ee4b | 2005-08-17 17:44:08 +0000 | [diff] [blame] | 280 | } |
| 281 | |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 282 | struct plat_smp_ops vsmp_smp_ops = { |
| 283 | .send_ipi_single = vsmp_send_ipi_single, |
| 284 | .send_ipi_mask = vsmp_send_ipi_mask, |
| 285 | .init_secondary = vsmp_init_secondary, |
| 286 | .smp_finish = vsmp_smp_finish, |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 287 | .boot_secondary = vsmp_boot_secondary, |
| 288 | .smp_setup = vsmp_smp_setup, |
| 289 | .prepare_cpus = vsmp_prepare_cpus, |
| 290 | }; |
Ralf Baechle | d6d3c9a | 2013-10-16 17:10:07 +0200 | [diff] [blame] | 291 | |
James Hogan | 7d907fa | 2014-07-04 11:59:46 +0100 | [diff] [blame] | 292 | #ifdef CONFIG_PROC_FS |
Ralf Baechle | d6d3c9a | 2013-10-16 17:10:07 +0200 | [diff] [blame] | 293 | static int proc_cpuinfo_chain_call(struct notifier_block *nfb, |
| 294 | unsigned long action_unused, void *data) |
| 295 | { |
| 296 | struct proc_cpuinfo_notifier_args *pcn = data; |
| 297 | struct seq_file *m = pcn->m; |
| 298 | unsigned long n = pcn->n; |
| 299 | |
| 300 | if (!cpu_has_mipsmt) |
| 301 | return NOTIFY_OK; |
| 302 | |
| 303 | seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id); |
| 304 | |
| 305 | return NOTIFY_OK; |
| 306 | } |
| 307 | |
| 308 | static int __init proc_cpuinfo_notifier_init(void) |
| 309 | { |
| 310 | return proc_cpuinfo_notifier(proc_cpuinfo_chain_call, 0); |
| 311 | } |
| 312 | |
| 313 | subsys_initcall(proc_cpuinfo_notifier_init); |
James Hogan | 7d907fa | 2014-07-04 11:59:46 +0100 | [diff] [blame] | 314 | #endif |