blob: 48d8dff05a3ad881a908cf770bc05d70ee2d3e8e [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Grant Likelyca632f52011-06-06 01:16:30 -06002/*
Ben Dooks7fba5342006-05-20 15:00:18 -07003 * Copyright (c) 2006 Ben Dooks
Ben Dooksbec08062009-12-14 22:20:24 -08004 * Copyright 2006-2009 Simtec Electronics
Ben Dooks7fba5342006-05-20 15:00:18 -07005 * Ben Dooks <ben@simtec.co.uk>
Ben Dooks7fba5342006-05-20 15:00:18 -07006*/
7
Ben Dooks7fba5342006-05-20 15:00:18 -07008#include <linux/spinlock.h>
Ben Dooks7fba5342006-05-20 15:00:18 -07009#include <linux/interrupt.h>
10#include <linux/delay.h>
11#include <linux/errno.h>
12#include <linux/err.h>
13#include <linux/clk.h>
14#include <linux/platform_device.h>
Ben Dooksee9c1fb2009-01-06 14:41:44 -080015#include <linux/gpio.h>
Ben Dooks1a0c2202009-09-22 16:46:12 -070016#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090017#include <linux/slab.h>
Ben Dooks7fba5342006-05-20 15:00:18 -070018
19#include <linux/spi/spi.h>
20#include <linux/spi/spi_bitbang.h>
Heiko Stuebnerf35ef7c2012-01-31 20:06:07 +090021#include <linux/spi/s3c24xx.h>
Paul Gortmakerd7614de2011-07-03 15:44:29 -040022#include <linux/module.h>
Ben Dooks7fba5342006-05-20 15:00:18 -070023
Ben Dooks13622702008-10-30 10:14:38 +000024#include <plat/regs-spi.h>
Ben Dooks7fba5342006-05-20 15:00:18 -070025
Ben Dooksbec08062009-12-14 22:20:24 -080026#include <asm/fiq.h>
27
Grant Likelyca632f52011-06-06 01:16:30 -060028#include "spi-s3c24xx-fiq.h"
Ben Dooksbec08062009-12-14 22:20:24 -080029
Ben Dooks570327d2009-09-22 16:46:14 -070030/**
31 * s3c24xx_spi_devstate - per device data
32 * @hz: Last frequency calculated for @sppre field.
33 * @mode: Last mode setting for the @spcon field.
34 * @spcon: Value to write to the SPCON register.
35 * @sppre: Value to write to the SPPRE register.
36 */
37struct s3c24xx_spi_devstate {
38 unsigned int hz;
39 unsigned int mode;
40 u8 spcon;
41 u8 sppre;
42};
43
Ben Dooksbec08062009-12-14 22:20:24 -080044enum spi_fiq_mode {
45 FIQ_MODE_NONE = 0,
46 FIQ_MODE_TX = 1,
47 FIQ_MODE_RX = 2,
48 FIQ_MODE_TXRX = 3,
49};
50
Ben Dooks7fba5342006-05-20 15:00:18 -070051struct s3c24xx_spi {
52 /* bitbang has to be first */
53 struct spi_bitbang bitbang;
54 struct completion done;
55
56 void __iomem *regs;
57 int irq;
58 int len;
59 int count;
60
Ben Dooksbec08062009-12-14 22:20:24 -080061 struct fiq_handler fiq_handler;
62 enum spi_fiq_mode fiq_mode;
63 unsigned char fiq_inuse;
64 unsigned char fiq_claimed;
65
Arnaud Patard (Rtp6c912a32007-03-16 13:38:36 -080066 void (*set_cs)(struct s3c2410_spi_info *spi,
Ben Dooks8736b922007-01-26 00:56:43 -080067 int cs, int pol);
68
Ben Dooks7fba5342006-05-20 15:00:18 -070069 /* data buffers */
70 const unsigned char *tx;
71 unsigned char *rx;
72
73 struct clk *clk;
Ben Dooks7fba5342006-05-20 15:00:18 -070074 struct spi_master *master;
75 struct spi_device *curdev;
76 struct device *dev;
77 struct s3c2410_spi_info *pdata;
78};
79
80#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
81#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
82
83static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
84{
85 return spi_master_get_devdata(sdev->master);
86}
87
Ben Dooks8736b922007-01-26 00:56:43 -080088static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
89{
Ben Dooksee9c1fb2009-01-06 14:41:44 -080090 gpio_set_value(spi->pin_cs, pol);
Ben Dooks8736b922007-01-26 00:56:43 -080091}
92
Ben Dooks7fba5342006-05-20 15:00:18 -070093static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
94{
Ben Dooks570327d2009-09-22 16:46:14 -070095 struct s3c24xx_spi_devstate *cs = spi->controller_state;
Ben Dooks7fba5342006-05-20 15:00:18 -070096 struct s3c24xx_spi *hw = to_hw(spi);
97 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
Ben Dooks570327d2009-09-22 16:46:14 -070098
99 /* change the chipselect state and the state of the spi engine clock */
Ben Dooks7fba5342006-05-20 15:00:18 -0700100
101 switch (value) {
102 case BITBANG_CS_INACTIVE:
Ben Dooks3d2c5b42007-04-16 22:53:22 -0700103 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
Ben Dooks570327d2009-09-22 16:46:14 -0700104 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
Ben Dooks7fba5342006-05-20 15:00:18 -0700105 break;
106
107 case BITBANG_CS_ACTIVE:
Ben Dooks570327d2009-09-22 16:46:14 -0700108 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
109 hw->regs + S3C2410_SPCON);
Ben Dooks3d2c5b42007-04-16 22:53:22 -0700110 hw->set_cs(hw->pdata, spi->chip_select, cspol);
Ben Dooks7fba5342006-05-20 15:00:18 -0700111 break;
Ben Dooks7fba5342006-05-20 15:00:18 -0700112 }
113}
114
Ben Dooks570327d2009-09-22 16:46:14 -0700115static int s3c24xx_spi_update_state(struct spi_device *spi,
116 struct spi_transfer *t)
Ben Dooks7fba5342006-05-20 15:00:18 -0700117{
118 struct s3c24xx_spi *hw = to_hw(spi);
Ben Dooks570327d2009-09-22 16:46:14 -0700119 struct s3c24xx_spi_devstate *cs = spi->controller_state;
Ben Dooks7fba5342006-05-20 15:00:18 -0700120 unsigned int hz;
121 unsigned int div;
Ben Dooksb8978782009-08-18 14:11:16 -0700122 unsigned long clk;
Ben Dooks7fba5342006-05-20 15:00:18 -0700123
Ben Dooks7fba5342006-05-20 15:00:18 -0700124 hz = t ? t->speed_hz : spi->max_speed_hz;
125
Ben Dooks19152972009-08-18 14:11:17 -0700126 if (!hz)
127 hz = spi->max_speed_hz;
128
Ben Dooks570327d2009-09-22 16:46:14 -0700129 if (spi->mode != cs->mode) {
Ben Dooksbec08062009-12-14 22:20:24 -0800130 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
Ben Dooks7fba5342006-05-20 15:00:18 -0700131
Ben Dooks570327d2009-09-22 16:46:14 -0700132 if (spi->mode & SPI_CPHA)
133 spcon |= S3C2410_SPCON_CPHA_FMTB;
Ben Dooks7fba5342006-05-20 15:00:18 -0700134
Ben Dooks570327d2009-09-22 16:46:14 -0700135 if (spi->mode & SPI_CPOL)
136 spcon |= S3C2410_SPCON_CPOL_HIGH;
Ben Dooksb8978782009-08-18 14:11:16 -0700137
Ben Dooks570327d2009-09-22 16:46:14 -0700138 cs->mode = spi->mode;
139 cs->spcon = spcon;
140 }
Ben Dooksb8978782009-08-18 14:11:16 -0700141
Ben Dooks570327d2009-09-22 16:46:14 -0700142 if (cs->hz != hz) {
143 clk = clk_get_rate(hw->clk);
144 div = DIV_ROUND_UP(clk, hz * 2) - 1;
145
146 if (div > 255)
147 div = 255;
148
149 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
150 div, hz, clk / (2 * (div + 1)));
151
152 cs->hz = hz;
153 cs->sppre = div;
154 }
155
156 return 0;
157}
158
159static int s3c24xx_spi_setupxfer(struct spi_device *spi,
160 struct spi_transfer *t)
161{
162 struct s3c24xx_spi_devstate *cs = spi->controller_state;
163 struct s3c24xx_spi *hw = to_hw(spi);
164 int ret;
165
166 ret = s3c24xx_spi_update_state(spi, t);
167 if (!ret)
168 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
169
170 return ret;
171}
172
173static int s3c24xx_spi_setup(struct spi_device *spi)
174{
175 struct s3c24xx_spi_devstate *cs = spi->controller_state;
176 struct s3c24xx_spi *hw = to_hw(spi);
177 int ret;
178
179 /* allocate settings on the first call */
180 if (!cs) {
Axel Linc586feb2014-03-31 11:37:29 +0800181 cs = devm_kzalloc(&spi->dev,
182 sizeof(struct s3c24xx_spi_devstate),
183 GFP_KERNEL);
Jingoo Han0375cff2014-04-29 17:20:02 +0900184 if (!cs)
Ben Dooks570327d2009-09-22 16:46:14 -0700185 return -ENOMEM;
Ben Dooks570327d2009-09-22 16:46:14 -0700186
187 cs->spcon = SPCON_DEFAULT;
188 cs->hz = -1;
189 spi->controller_state = cs;
190 }
191
192 /* initialise the state from the device */
193 ret = s3c24xx_spi_update_state(spi, NULL);
194 if (ret)
195 return ret;
Ben Dooks7fba5342006-05-20 15:00:18 -0700196
Nicolas Boichatc15f6ed2015-08-17 11:52:54 +0800197 mutex_lock(&hw->bitbang.lock);
Ben Dooks7fba5342006-05-20 15:00:18 -0700198 if (!hw->bitbang.busy) {
199 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
200 /* need to ndelay for 0.5 clocktick ? */
201 }
Nicolas Boichatc15f6ed2015-08-17 11:52:54 +0800202 mutex_unlock(&hw->bitbang.lock);
Ben Dooks7fba5342006-05-20 15:00:18 -0700203
204 return 0;
205}
206
Ben Dooks7fba5342006-05-20 15:00:18 -0700207static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
208{
David Brownell4b1badf2006-12-29 16:48:39 -0800209 return hw->tx ? hw->tx[count] : 0;
Ben Dooks7fba5342006-05-20 15:00:18 -0700210}
211
Ben Dooksbec08062009-12-14 22:20:24 -0800212#ifdef CONFIG_SPI_S3C24XX_FIQ
213/* Support for FIQ based pseudo-DMA to improve the transfer speed.
214 *
215 * This code uses the assembly helper in spi_s3c24xx_spi.S which is
216 * used by the FIQ core to move data between main memory and the peripheral
217 * block. Since this is code running on the processor, there is no problem
218 * with cache coherency of the buffers, so we can use any buffer we like.
219 */
220
221/**
222 * struct spi_fiq_code - FIQ code and header
223 * @length: The length of the code fragment, excluding this header.
224 * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
225 * @data: The code itself to install as a FIQ handler.
226 */
227struct spi_fiq_code {
228 u32 length;
229 u32 ack_offset;
230 u8 data[0];
231};
232
233extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
234extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
235extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
236
237/**
238 * ack_bit - turn IRQ into IRQ acknowledgement bit
239 * @irq: The interrupt number
240 *
241 * Returns the bit to write to the interrupt acknowledge register.
242 */
243static inline u32 ack_bit(unsigned int irq)
244{
245 return 1 << (irq - IRQ_EINT0);
246}
247
248/**
249 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
250 * @hw: The hardware state.
251 *
252 * Claim the FIQ handler (only one can be active at any one time) and
253 * then setup the correct transfer code for this transfer.
254 *
Daniel Mack3ad2f3fb2010-02-03 08:01:28 +0800255 * This call updates all the necessary state information if successful,
Ben Dooksbec08062009-12-14 22:20:24 -0800256 * so the caller does not need to do anything more than start the transfer
257 * as normal, since the IRQ will have been re-routed to the FIQ handler.
258*/
Sachin Kamatcfeb3312013-09-10 11:20:13 +0530259static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
Ben Dooksbec08062009-12-14 22:20:24 -0800260{
261 struct pt_regs regs;
262 enum spi_fiq_mode mode;
263 struct spi_fiq_code *code;
264 int ret;
265
266 if (!hw->fiq_claimed) {
267 /* try and claim fiq if we haven't got it, and if not
268 * then return and simply use another transfer method */
269
270 ret = claim_fiq(&hw->fiq_handler);
271 if (ret)
272 return;
273 }
274
275 if (hw->tx && !hw->rx)
276 mode = FIQ_MODE_TX;
277 else if (hw->rx && !hw->tx)
278 mode = FIQ_MODE_RX;
279 else
280 mode = FIQ_MODE_TXRX;
281
282 regs.uregs[fiq_rspi] = (long)hw->regs;
283 regs.uregs[fiq_rrx] = (long)hw->rx;
284 regs.uregs[fiq_rtx] = (long)hw->tx + 1;
285 regs.uregs[fiq_rcount] = hw->len - 1;
286 regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
287
288 set_fiq_regs(&regs);
289
290 if (hw->fiq_mode != mode) {
291 u32 *ack_ptr;
292
293 hw->fiq_mode = mode;
294
295 switch (mode) {
296 case FIQ_MODE_TX:
297 code = &s3c24xx_spi_fiq_tx;
298 break;
299 case FIQ_MODE_RX:
300 code = &s3c24xx_spi_fiq_rx;
301 break;
302 case FIQ_MODE_TXRX:
303 code = &s3c24xx_spi_fiq_txrx;
304 break;
305 default:
306 code = NULL;
307 }
308
309 BUG_ON(!code);
310
311 ack_ptr = (u32 *)&code->data[code->ack_offset];
312 *ack_ptr = ack_bit(hw->irq);
313
314 set_fiq_handler(&code->data, code->length);
315 }
316
317 s3c24xx_set_fiq(hw->irq, true);
318
319 hw->fiq_mode = mode;
320 hw->fiq_inuse = 1;
321}
322
323/**
324 * s3c24xx_spi_fiqop - FIQ core code callback
325 * @pw: Data registered with the handler
326 * @release: Whether this is a release or a return.
327 *
328 * Called by the FIQ code when another module wants to use the FIQ, so
329 * return whether we are currently using this or not and then update our
330 * internal state.
331 */
332static int s3c24xx_spi_fiqop(void *pw, int release)
333{
334 struct s3c24xx_spi *hw = pw;
335 int ret = 0;
336
337 if (release) {
338 if (hw->fiq_inuse)
339 ret = -EBUSY;
340
341 /* note, we do not need to unroute the FIQ, as the FIQ
342 * vector code de-routes it to signal the end of transfer */
343
344 hw->fiq_mode = FIQ_MODE_NONE;
345 hw->fiq_claimed = 0;
346 } else {
347 hw->fiq_claimed = 1;
348 }
349
350 return ret;
351}
352
353/**
354 * s3c24xx_spi_initfiq - setup the information for the FIQ core
355 * @hw: The hardware state.
356 *
357 * Setup the fiq_handler block to pass to the FIQ core.
358 */
359static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
360{
361 hw->fiq_handler.dev_id = hw;
362 hw->fiq_handler.name = dev_name(hw->dev);
363 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
364}
365
366/**
367 * s3c24xx_spi_usefiq - return if we should be using FIQ.
368 * @hw: The hardware state.
369 *
370 * Return true if the platform data specifies whether this channel is
371 * allowed to use the FIQ.
372 */
373static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
374{
375 return hw->pdata->use_fiq;
376}
377
378/**
379 * s3c24xx_spi_usingfiq - return if channel is using FIQ
380 * @spi: The hardware state.
381 *
382 * Return whether the channel is currently using the FIQ (separate from
383 * whether the FIQ is claimed).
384 */
385static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
386{
387 return spi->fiq_inuse;
388}
389#else
390
391static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
392static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
393static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
394static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
395
396#endif /* CONFIG_SPI_S3C24XX_FIQ */
397
Ben Dooks7fba5342006-05-20 15:00:18 -0700398static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
399{
400 struct s3c24xx_spi *hw = to_hw(spi);
401
Ben Dooks7fba5342006-05-20 15:00:18 -0700402 hw->tx = t->tx_buf;
403 hw->rx = t->rx_buf;
404 hw->len = t->len;
405 hw->count = 0;
406
Ben Dooks4bb5eba2008-04-15 14:34:44 -0700407 init_completion(&hw->done);
408
Ben Dooksbec08062009-12-14 22:20:24 -0800409 hw->fiq_inuse = 0;
410 if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
411 s3c24xx_spi_tryfiq(hw);
412
Ben Dooks7fba5342006-05-20 15:00:18 -0700413 /* send the first byte */
414 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
Ben Dooks4bb5eba2008-04-15 14:34:44 -0700415
Ben Dooks7fba5342006-05-20 15:00:18 -0700416 wait_for_completion(&hw->done);
Ben Dooks7fba5342006-05-20 15:00:18 -0700417 return hw->count;
418}
419
David Howells7d12e782006-10-05 14:55:46 +0100420static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
Ben Dooks7fba5342006-05-20 15:00:18 -0700421{
422 struct s3c24xx_spi *hw = dev;
423 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
424 unsigned int count = hw->count;
425
426 if (spsta & S3C2410_SPSTA_DCOL) {
427 dev_dbg(hw->dev, "data-collision\n");
428 complete(&hw->done);
429 goto irq_done;
430 }
431
432 if (!(spsta & S3C2410_SPSTA_READY)) {
433 dev_dbg(hw->dev, "spi not ready for tx?\n");
434 complete(&hw->done);
435 goto irq_done;
436 }
437
Ben Dooksbec08062009-12-14 22:20:24 -0800438 if (!s3c24xx_spi_usingfiq(hw)) {
439 hw->count++;
Ben Dooks7fba5342006-05-20 15:00:18 -0700440
Ben Dooksbec08062009-12-14 22:20:24 -0800441 if (hw->rx)
442 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
Ben Dooks7fba5342006-05-20 15:00:18 -0700443
Ben Dooksbec08062009-12-14 22:20:24 -0800444 count++;
Ben Dooks7fba5342006-05-20 15:00:18 -0700445
Ben Dooksbec08062009-12-14 22:20:24 -0800446 if (count < hw->len)
447 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
448 else
449 complete(&hw->done);
450 } else {
451 hw->count = hw->len;
452 hw->fiq_inuse = 0;
453
454 if (hw->rx)
455 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
456
Ben Dooks7fba5342006-05-20 15:00:18 -0700457 complete(&hw->done);
Ben Dooksbec08062009-12-14 22:20:24 -0800458 }
Ben Dooks7fba5342006-05-20 15:00:18 -0700459
460 irq_done:
461 return IRQ_HANDLED;
462}
463
Ben Dooks5aa6cf32008-08-04 13:41:10 -0700464static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
465{
466 /* for the moment, permanently enable the clock */
467
468 clk_enable(hw->clk);
469
470 /* program defaults into the registers */
471
472 writeb(0xff, hw->regs + S3C2410_SPPRE);
473 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
474 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
Ben Dookscf46b972008-10-15 22:02:41 -0700475
Ben Dooksee9c1fb2009-01-06 14:41:44 -0800476 if (hw->pdata) {
477 if (hw->set_cs == s3c24xx_spi_gpiocs)
478 gpio_direction_output(hw->pdata->pin_cs, 1);
479
480 if (hw->pdata->gpio_setup)
481 hw->pdata->gpio_setup(hw->pdata, 1);
482 }
Ben Dooks5aa6cf32008-08-04 13:41:10 -0700483}
484
Grant Likelyfd4a3192012-12-07 16:57:14 +0000485static int s3c24xx_spi_probe(struct platform_device *pdev)
Ben Dooks7fba5342006-05-20 15:00:18 -0700486{
Ben Dooks50f426b2008-04-15 14:34:45 -0700487 struct s3c2410_spi_info *pdata;
Ben Dooks7fba5342006-05-20 15:00:18 -0700488 struct s3c24xx_spi *hw;
489 struct spi_master *master;
Ben Dooks7fba5342006-05-20 15:00:18 -0700490 struct resource *res;
491 int err = 0;
Ben Dooks7fba5342006-05-20 15:00:18 -0700492
493 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
494 if (master == NULL) {
495 dev_err(&pdev->dev, "No memory for spi_master\n");
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900496 return -ENOMEM;
Ben Dooks7fba5342006-05-20 15:00:18 -0700497 }
498
499 hw = spi_master_get_devdata(master);
Ben Dooks7fba5342006-05-20 15:00:18 -0700500
Axel Lin94c69f72013-09-10 15:43:41 +0800501 hw->master = master;
Jingoo Han8074cf02013-07-30 16:58:59 +0900502 hw->pdata = pdata = dev_get_platdata(&pdev->dev);
Ben Dooks7fba5342006-05-20 15:00:18 -0700503 hw->dev = &pdev->dev;
504
Ben Dooks50f426b2008-04-15 14:34:45 -0700505 if (pdata == NULL) {
Ben Dooks7fba5342006-05-20 15:00:18 -0700506 dev_err(&pdev->dev, "No platform data supplied\n");
507 err = -ENOENT;
508 goto err_no_pdata;
509 }
510
511 platform_set_drvdata(pdev, hw);
512 init_completion(&hw->done);
513
Ben Dooksbec08062009-12-14 22:20:24 -0800514 /* initialise fiq handler */
515
516 s3c24xx_spi_initfiq(hw);
517
Ben Dooksd1e77802008-04-15 14:34:46 -0700518 /* setup the master state. */
519
David Brownelle7db06b2009-06-17 16:26:04 -0700520 /* the spi->mode bits understood by this driver: */
521 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
522
Ben Dooksd1e77802008-04-15 14:34:46 -0700523 master->num_chipselect = hw->pdata->num_cs;
Ben Dookscb1d0a72008-07-28 15:46:33 -0700524 master->bus_num = pdata->bus_num;
Axel Lin08850fa2014-02-14 20:38:16 +0800525 master->bits_per_word_mask = SPI_BPW_MASK(8);
Ben Dooksd1e77802008-04-15 14:34:46 -0700526
Ben Dooks7fba5342006-05-20 15:00:18 -0700527 /* setup the state for the bitbang driver */
528
529 hw->bitbang.master = hw->master;
530 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
531 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
532 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
Ben Dooks570327d2009-09-22 16:46:14 -0700533
534 hw->master->setup = s3c24xx_spi_setup;
Ben Dooks7fba5342006-05-20 15:00:18 -0700535
536 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
537
538 /* find and map our resources */
Ben Dooks7fba5342006-05-20 15:00:18 -0700539 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900540 hw->regs = devm_ioremap_resource(&pdev->dev, res);
541 if (IS_ERR(hw->regs)) {
542 err = PTR_ERR(hw->regs);
543 goto err_no_pdata;
Ben Dooks7fba5342006-05-20 15:00:18 -0700544 }
545
546 hw->irq = platform_get_irq(pdev, 0);
547 if (hw->irq < 0) {
548 dev_err(&pdev->dev, "No IRQ specified\n");
549 err = -ENOENT;
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900550 goto err_no_pdata;
Ben Dooks7fba5342006-05-20 15:00:18 -0700551 }
552
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900553 err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
554 pdev->name, hw);
Ben Dooks7fba5342006-05-20 15:00:18 -0700555 if (err) {
556 dev_err(&pdev->dev, "Cannot claim IRQ\n");
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900557 goto err_no_pdata;
Ben Dooks7fba5342006-05-20 15:00:18 -0700558 }
559
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900560 hw->clk = devm_clk_get(&pdev->dev, "spi");
Ben Dooks7fba5342006-05-20 15:00:18 -0700561 if (IS_ERR(hw->clk)) {
562 dev_err(&pdev->dev, "No clock for device\n");
563 err = PTR_ERR(hw->clk);
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900564 goto err_no_pdata;
Ben Dooks7fba5342006-05-20 15:00:18 -0700565 }
566
Ben Dooks7fba5342006-05-20 15:00:18 -0700567 /* setup any gpio we can */
568
Ben Dooks50f426b2008-04-15 14:34:45 -0700569 if (!pdata->set_cs) {
Ben Dooksee9c1fb2009-01-06 14:41:44 -0800570 if (pdata->pin_cs < 0) {
571 dev_err(&pdev->dev, "No chipselect pin\n");
Julia Lawallb2af0452012-08-22 13:42:47 +0200572 err = -EINVAL;
Ben Dooksee9c1fb2009-01-06 14:41:44 -0800573 goto err_register;
574 }
Ben Dooks8736b922007-01-26 00:56:43 -0800575
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900576 err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
577 dev_name(&pdev->dev));
Ben Dooksee9c1fb2009-01-06 14:41:44 -0800578 if (err) {
579 dev_err(&pdev->dev, "Failed to get gpio for cs\n");
580 goto err_register;
581 }
582
583 hw->set_cs = s3c24xx_spi_gpiocs;
584 gpio_direction_output(pdata->pin_cs, 1);
Ben Dooks8736b922007-01-26 00:56:43 -0800585 } else
Ben Dooks50f426b2008-04-15 14:34:45 -0700586 hw->set_cs = pdata->set_cs;
Ben Dooks7fba5342006-05-20 15:00:18 -0700587
Ben Dooksee9c1fb2009-01-06 14:41:44 -0800588 s3c24xx_spi_initialsetup(hw);
589
Ben Dooks7fba5342006-05-20 15:00:18 -0700590 /* register our spi controller */
591
592 err = spi_bitbang_start(&hw->bitbang);
593 if (err) {
594 dev_err(&pdev->dev, "Failed to register SPI master\n");
595 goto err_register;
596 }
597
Ben Dooks7fba5342006-05-20 15:00:18 -0700598 return 0;
599
600 err_register:
601 clk_disable(hw->clk);
Ben Dooks7fba5342006-05-20 15:00:18 -0700602
Ben Dooks7fba5342006-05-20 15:00:18 -0700603 err_no_pdata:
Joe Perchesa419aef2009-08-18 11:18:35 -0700604 spi_master_put(hw->master);
Ben Dooks7fba5342006-05-20 15:00:18 -0700605 return err;
606}
607
Grant Likelyfd4a3192012-12-07 16:57:14 +0000608static int s3c24xx_spi_remove(struct platform_device *dev)
Ben Dooks7fba5342006-05-20 15:00:18 -0700609{
610 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
611
Axel Linc6e7b8c2011-05-15 07:35:16 +0800612 spi_bitbang_stop(&hw->bitbang);
Ben Dooks7fba5342006-05-20 15:00:18 -0700613 clk_disable(hw->clk);
Ben Dooks7fba5342006-05-20 15:00:18 -0700614 spi_master_put(hw->master);
615 return 0;
616}
617
618
619#ifdef CONFIG_PM
620
Ben Dooks6d613202009-09-22 16:46:13 -0700621static int s3c24xx_spi_suspend(struct device *dev)
Ben Dooks7fba5342006-05-20 15:00:18 -0700622{
Axel Lina12163942013-08-09 15:35:16 +0800623 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
Axel Lin38060372014-03-05 15:17:23 +0800624 int ret;
625
626 ret = spi_master_suspend(hw->master);
627 if (ret)
628 return ret;
Ben Dooks7fba5342006-05-20 15:00:18 -0700629
Ben Dookscf46b972008-10-15 22:02:41 -0700630 if (hw->pdata && hw->pdata->gpio_setup)
631 hw->pdata->gpio_setup(hw->pdata, 0);
632
Ben Dooks7fba5342006-05-20 15:00:18 -0700633 clk_disable(hw->clk);
634 return 0;
635}
636
Ben Dooks6d613202009-09-22 16:46:13 -0700637static int s3c24xx_spi_resume(struct device *dev)
Ben Dooks7fba5342006-05-20 15:00:18 -0700638{
Axel Lina12163942013-08-09 15:35:16 +0800639 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
Ben Dooks7fba5342006-05-20 15:00:18 -0700640
Ben Dooks5aa6cf32008-08-04 13:41:10 -0700641 s3c24xx_spi_initialsetup(hw);
Axel Lin38060372014-03-05 15:17:23 +0800642 return spi_master_resume(hw->master);
Ben Dooks7fba5342006-05-20 15:00:18 -0700643}
644
Alexey Dobriyan47145212009-12-14 18:00:08 -0800645static const struct dev_pm_ops s3c24xx_spi_pmops = {
Ben Dooks6d613202009-09-22 16:46:13 -0700646 .suspend = s3c24xx_spi_suspend,
647 .resume = s3c24xx_spi_resume,
648};
649
650#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
Ben Dooks7fba5342006-05-20 15:00:18 -0700651#else
Ben Dooks6d613202009-09-22 16:46:13 -0700652#define S3C24XX_SPI_PMOPS NULL
653#endif /* CONFIG_PM */
Ben Dooks7fba5342006-05-20 15:00:18 -0700654
Kay Sievers7e38c3c2008-04-10 21:29:20 -0700655MODULE_ALIAS("platform:s3c2410-spi");
Ben Dooks42cde432008-09-13 02:33:24 -0700656static struct platform_driver s3c24xx_spi_driver = {
Grant Likely940ab882011-10-05 11:29:49 -0600657 .probe = s3c24xx_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000658 .remove = s3c24xx_spi_remove,
Ben Dooks7fba5342006-05-20 15:00:18 -0700659 .driver = {
660 .name = "s3c2410-spi",
Ben Dooks6d613202009-09-22 16:46:13 -0700661 .pm = S3C24XX_SPI_PMOPS,
Ben Dooks7fba5342006-05-20 15:00:18 -0700662 },
663};
Grant Likely940ab882011-10-05 11:29:49 -0600664module_platform_driver(s3c24xx_spi_driver);
Ben Dooks7fba5342006-05-20 15:00:18 -0700665
666MODULE_DESCRIPTION("S3C24XX SPI Driver");
667MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
668MODULE_LICENSE("GPL");