Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1 | /* |
| 2 | * In-Memory Collection (IMC) Performance Monitor counter support. |
| 3 | * |
| 4 | * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation. |
| 5 | * (C) 2017 Anju T Sudhakar, IBM Corporation. |
| 6 | * (C) 2017 Hemant K Shaw, IBM Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License |
| 10 | * as published by the Free Software Foundation; either version |
| 11 | * 2 of the License, or later version. |
| 12 | */ |
| 13 | #include <linux/perf_event.h> |
| 14 | #include <linux/slab.h> |
| 15 | #include <asm/opal.h> |
| 16 | #include <asm/imc-pmu.h> |
| 17 | #include <asm/cputhreads.h> |
| 18 | #include <asm/smp.h> |
| 19 | #include <linux/string.h> |
| 20 | |
| 21 | /* Nest IMC data structures and variables */ |
| 22 | |
| 23 | /* |
| 24 | * Used to avoid races in counting the nest-pmu units during hotplug |
| 25 | * register and unregister |
| 26 | */ |
| 27 | static DEFINE_MUTEX(nest_init_lock); |
| 28 | static DEFINE_PER_CPU(struct imc_pmu_ref *, local_nest_imc_refc); |
Madhavan Srinivasan | 73ce9aec | 2017-11-22 10:45:39 +0530 | [diff] [blame] | 29 | static struct imc_pmu **per_nest_pmu_arr; |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 30 | static cpumask_t nest_imc_cpumask; |
| 31 | struct imc_pmu_ref *nest_imc_refc; |
| 32 | static int nest_pmus; |
| 33 | |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 34 | /* Core IMC data structures and variables */ |
| 35 | |
| 36 | static cpumask_t core_imc_cpumask; |
| 37 | struct imc_pmu_ref *core_imc_refc; |
| 38 | static struct imc_pmu *core_imc_pmu; |
| 39 | |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 40 | /* Thread IMC data structures and variables */ |
| 41 | |
| 42 | static DEFINE_PER_CPU(u64 *, thread_imc_mem); |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 43 | static int thread_imc_mem_size; |
| 44 | |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 45 | struct imc_pmu *imc_event_to_pmu(struct perf_event *event) |
| 46 | { |
| 47 | return container_of(event->pmu, struct imc_pmu, pmu); |
| 48 | } |
| 49 | |
| 50 | PMU_FORMAT_ATTR(event, "config:0-40"); |
| 51 | PMU_FORMAT_ATTR(offset, "config:0-31"); |
| 52 | PMU_FORMAT_ATTR(rvalue, "config:32"); |
| 53 | PMU_FORMAT_ATTR(mode, "config:33-40"); |
| 54 | static struct attribute *imc_format_attrs[] = { |
| 55 | &format_attr_event.attr, |
| 56 | &format_attr_offset.attr, |
| 57 | &format_attr_rvalue.attr, |
| 58 | &format_attr_mode.attr, |
| 59 | NULL, |
| 60 | }; |
| 61 | |
| 62 | static struct attribute_group imc_format_group = { |
| 63 | .name = "format", |
| 64 | .attrs = imc_format_attrs, |
| 65 | }; |
| 66 | |
| 67 | /* Get the cpumask printed to a buffer "buf" */ |
| 68 | static ssize_t imc_pmu_cpumask_get_attr(struct device *dev, |
| 69 | struct device_attribute *attr, |
| 70 | char *buf) |
| 71 | { |
| 72 | struct pmu *pmu = dev_get_drvdata(dev); |
| 73 | struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu); |
| 74 | cpumask_t *active_mask; |
| 75 | |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 76 | switch(imc_pmu->domain){ |
| 77 | case IMC_DOMAIN_NEST: |
| 78 | active_mask = &nest_imc_cpumask; |
| 79 | break; |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 80 | case IMC_DOMAIN_CORE: |
| 81 | active_mask = &core_imc_cpumask; |
| 82 | break; |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 83 | default: |
| 84 | return 0; |
| 85 | } |
| 86 | |
| 87 | return cpumap_print_to_pagebuf(true, buf, active_mask); |
| 88 | } |
| 89 | |
| 90 | static DEVICE_ATTR(cpumask, S_IRUGO, imc_pmu_cpumask_get_attr, NULL); |
| 91 | |
| 92 | static struct attribute *imc_pmu_cpumask_attrs[] = { |
| 93 | &dev_attr_cpumask.attr, |
| 94 | NULL, |
| 95 | }; |
| 96 | |
| 97 | static struct attribute_group imc_pmu_cpumask_attr_group = { |
| 98 | .attrs = imc_pmu_cpumask_attrs, |
| 99 | }; |
| 100 | |
| 101 | /* device_str_attr_create : Populate event "name" and string "str" in attribute */ |
| 102 | static struct attribute *device_str_attr_create(const char *name, const char *str) |
| 103 | { |
| 104 | struct perf_pmu_events_attr *attr; |
| 105 | |
| 106 | attr = kzalloc(sizeof(*attr), GFP_KERNEL); |
| 107 | if (!attr) |
| 108 | return NULL; |
| 109 | sysfs_attr_init(&attr->attr.attr); |
| 110 | |
| 111 | attr->event_str = str; |
| 112 | attr->attr.attr.name = name; |
| 113 | attr->attr.attr.mode = 0444; |
| 114 | attr->attr.show = perf_event_sysfs_show; |
| 115 | |
| 116 | return &attr->attr.attr; |
| 117 | } |
| 118 | |
Anju T Sudhakar | 8b4e6de | 2017-12-11 11:28:37 +0530 | [diff] [blame] | 119 | static int imc_parse_event(struct device_node *np, const char *scale, |
| 120 | const char *unit, const char *prefix, |
| 121 | u32 base, struct imc_events *event) |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 122 | { |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 123 | const char *s; |
| 124 | u32 reg; |
| 125 | |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 126 | if (of_property_read_u32(np, "reg", ®)) |
| 127 | goto error; |
| 128 | /* Add the base_reg value to the "reg" */ |
| 129 | event->value = base + reg; |
| 130 | |
| 131 | if (of_property_read_string(np, "event-name", &s)) |
| 132 | goto error; |
| 133 | |
| 134 | event->name = kasprintf(GFP_KERNEL, "%s%s", prefix, s); |
| 135 | if (!event->name) |
| 136 | goto error; |
| 137 | |
| 138 | if (of_property_read_string(np, "scale", &s)) |
| 139 | s = scale; |
| 140 | |
| 141 | if (s) { |
| 142 | event->scale = kstrdup(s, GFP_KERNEL); |
| 143 | if (!event->scale) |
| 144 | goto error; |
| 145 | } |
| 146 | |
| 147 | if (of_property_read_string(np, "unit", &s)) |
| 148 | s = unit; |
| 149 | |
| 150 | if (s) { |
| 151 | event->unit = kstrdup(s, GFP_KERNEL); |
| 152 | if (!event->unit) |
| 153 | goto error; |
| 154 | } |
| 155 | |
Anju T Sudhakar | 8b4e6de | 2017-12-11 11:28:37 +0530 | [diff] [blame] | 156 | return 0; |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 157 | error: |
| 158 | kfree(event->unit); |
| 159 | kfree(event->scale); |
| 160 | kfree(event->name); |
Anju T Sudhakar | 8b4e6de | 2017-12-11 11:28:37 +0530 | [diff] [blame] | 161 | return -EINVAL; |
| 162 | } |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 163 | |
Anju T Sudhakar | 8b4e6de | 2017-12-11 11:28:37 +0530 | [diff] [blame] | 164 | /* |
| 165 | * imc_free_events: Function to cleanup the events list, having |
| 166 | * "nr_entries". |
| 167 | */ |
| 168 | static void imc_free_events(struct imc_events *events, int nr_entries) |
| 169 | { |
| 170 | int i; |
| 171 | |
| 172 | /* Nothing to clean, return */ |
| 173 | if (!events) |
| 174 | return; |
| 175 | for (i = 0; i < nr_entries; i++) { |
| 176 | kfree(events[i].unit); |
| 177 | kfree(events[i].scale); |
| 178 | kfree(events[i].name); |
| 179 | } |
| 180 | |
| 181 | kfree(events); |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 182 | } |
| 183 | |
| 184 | /* |
| 185 | * update_events_in_group: Update the "events" information in an attr_group |
| 186 | * and assign the attr_group to the pmu "pmu". |
| 187 | */ |
| 188 | static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu) |
| 189 | { |
| 190 | struct attribute_group *attr_group; |
| 191 | struct attribute **attrs, *dev_str; |
| 192 | struct device_node *np, *pmu_events; |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 193 | u32 handle, base_reg; |
Anju T Sudhakar | 8b4e6de | 2017-12-11 11:28:37 +0530 | [diff] [blame] | 194 | int i = 0, j = 0, ct, ret; |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 195 | const char *prefix, *g_scale, *g_unit; |
| 196 | const char *ev_val_str, *ev_scale_str, *ev_unit_str; |
| 197 | |
| 198 | if (!of_property_read_u32(node, "events", &handle)) |
| 199 | pmu_events = of_find_node_by_phandle(handle); |
| 200 | else |
| 201 | return 0; |
| 202 | |
| 203 | /* Did not find any node with a given phandle */ |
| 204 | if (!pmu_events) |
| 205 | return 0; |
| 206 | |
| 207 | /* Get a count of number of child nodes */ |
| 208 | ct = of_get_child_count(pmu_events); |
| 209 | |
| 210 | /* Get the event prefix */ |
| 211 | if (of_property_read_string(node, "events-prefix", &prefix)) |
| 212 | return 0; |
| 213 | |
| 214 | /* Get a global unit and scale data if available */ |
| 215 | if (of_property_read_string(node, "scale", &g_scale)) |
| 216 | g_scale = NULL; |
| 217 | |
| 218 | if (of_property_read_string(node, "unit", &g_unit)) |
| 219 | g_unit = NULL; |
| 220 | |
| 221 | /* "reg" property gives out the base offset of the counters data */ |
| 222 | of_property_read_u32(node, "reg", &base_reg); |
| 223 | |
| 224 | /* Allocate memory for the events */ |
| 225 | pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL); |
| 226 | if (!pmu->events) |
| 227 | return -ENOMEM; |
| 228 | |
| 229 | ct = 0; |
| 230 | /* Parse the events and update the struct */ |
| 231 | for_each_child_of_node(pmu_events, np) { |
Anju T Sudhakar | 8b4e6de | 2017-12-11 11:28:37 +0530 | [diff] [blame] | 232 | ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]); |
| 233 | if (!ret) |
| 234 | ct++; |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 235 | } |
| 236 | |
| 237 | /* Allocate memory for attribute group */ |
| 238 | attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL); |
Anju T Sudhakar | 8b4e6de | 2017-12-11 11:28:37 +0530 | [diff] [blame] | 239 | if (!attr_group) { |
| 240 | imc_free_events(pmu->events, ct); |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 241 | return -ENOMEM; |
Anju T Sudhakar | 8b4e6de | 2017-12-11 11:28:37 +0530 | [diff] [blame] | 242 | } |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 243 | |
| 244 | /* |
| 245 | * Allocate memory for attributes. |
| 246 | * Since we have count of events for this pmu, we also allocate |
| 247 | * memory for the scale and unit attribute for now. |
| 248 | * "ct" has the total event structs added from the events-parent node. |
| 249 | * So allocate three times the "ct" (this includes event, event_scale and |
| 250 | * event_unit). |
| 251 | */ |
| 252 | attrs = kcalloc(((ct * 3) + 1), sizeof(struct attribute *), GFP_KERNEL); |
| 253 | if (!attrs) { |
| 254 | kfree(attr_group); |
Anju T Sudhakar | 8b4e6de | 2017-12-11 11:28:37 +0530 | [diff] [blame] | 255 | imc_free_events(pmu->events, ct); |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 256 | return -ENOMEM; |
| 257 | } |
| 258 | |
| 259 | attr_group->name = "events"; |
| 260 | attr_group->attrs = attrs; |
| 261 | do { |
Anju T Sudhakar | 8b4e6de | 2017-12-11 11:28:37 +0530 | [diff] [blame] | 262 | ev_val_str = kasprintf(GFP_KERNEL, "event=0x%x", pmu->events[i].value); |
| 263 | dev_str = device_str_attr_create(pmu->events[i].name, ev_val_str); |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 264 | if (!dev_str) |
| 265 | continue; |
| 266 | |
| 267 | attrs[j++] = dev_str; |
Anju T Sudhakar | 8b4e6de | 2017-12-11 11:28:37 +0530 | [diff] [blame] | 268 | if (pmu->events[i].scale) { |
| 269 | ev_scale_str = kasprintf(GFP_KERNEL, "%s.scale", pmu->events[i].name); |
| 270 | dev_str = device_str_attr_create(ev_scale_str, pmu->events[i].scale); |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 271 | if (!dev_str) |
| 272 | continue; |
| 273 | |
| 274 | attrs[j++] = dev_str; |
| 275 | } |
| 276 | |
Anju T Sudhakar | 8b4e6de | 2017-12-11 11:28:37 +0530 | [diff] [blame] | 277 | if (pmu->events[i].unit) { |
| 278 | ev_unit_str = kasprintf(GFP_KERNEL, "%s.unit", pmu->events[i].name); |
| 279 | dev_str = device_str_attr_create(ev_unit_str, pmu->events[i].unit); |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 280 | if (!dev_str) |
| 281 | continue; |
| 282 | |
| 283 | attrs[j++] = dev_str; |
| 284 | } |
| 285 | } while (++i < ct); |
| 286 | |
| 287 | /* Save the event attribute */ |
| 288 | pmu->attr_groups[IMC_EVENT_ATTR] = attr_group; |
| 289 | |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 290 | return 0; |
| 291 | } |
| 292 | |
| 293 | /* get_nest_pmu_ref: Return the imc_pmu_ref struct for the given node */ |
| 294 | static struct imc_pmu_ref *get_nest_pmu_ref(int cpu) |
| 295 | { |
| 296 | return per_cpu(local_nest_imc_refc, cpu); |
| 297 | } |
| 298 | |
| 299 | static void nest_change_cpu_context(int old_cpu, int new_cpu) |
| 300 | { |
| 301 | struct imc_pmu **pn = per_nest_pmu_arr; |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 302 | |
| 303 | if (old_cpu < 0 || new_cpu < 0) |
| 304 | return; |
| 305 | |
Madhavan Srinivasan | 73ce9aec | 2017-11-22 10:45:39 +0530 | [diff] [blame] | 306 | while (*pn) { |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 307 | perf_pmu_migrate_context(&(*pn)->pmu, old_cpu, new_cpu); |
Madhavan Srinivasan | 73ce9aec | 2017-11-22 10:45:39 +0530 | [diff] [blame] | 308 | pn++; |
| 309 | } |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 310 | } |
| 311 | |
| 312 | static int ppc_nest_imc_cpu_offline(unsigned int cpu) |
| 313 | { |
| 314 | int nid, target = -1; |
| 315 | const struct cpumask *l_cpumask; |
| 316 | struct imc_pmu_ref *ref; |
| 317 | |
| 318 | /* |
| 319 | * Check in the designated list for this cpu. Dont bother |
| 320 | * if not one of them. |
| 321 | */ |
| 322 | if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask)) |
| 323 | return 0; |
| 324 | |
| 325 | /* |
Anju T Sudhakar | ad2b6e0 | 2017-12-05 11:00:38 +0530 | [diff] [blame] | 326 | * Check whether nest_imc is registered. We could end up here if the |
| 327 | * cpuhotplug callback registration fails. i.e, callback invokes the |
| 328 | * offline path for all successfully registered nodes. At this stage, |
| 329 | * nest_imc pmu will not be registered and we should return here. |
| 330 | * |
| 331 | * We return with a zero since this is not an offline failure. And |
| 332 | * cpuhp_setup_state() returns the actual failure reason to the caller, |
| 333 | * which in turn will call the cleanup routine. |
| 334 | */ |
| 335 | if (!nest_pmus) |
| 336 | return 0; |
| 337 | |
| 338 | /* |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 339 | * Now that this cpu is one of the designated, |
| 340 | * find a next cpu a) which is online and b) in same chip. |
| 341 | */ |
| 342 | nid = cpu_to_node(cpu); |
| 343 | l_cpumask = cpumask_of_node(nid); |
| 344 | target = cpumask_any_but(l_cpumask, cpu); |
| 345 | |
| 346 | /* |
| 347 | * Update the cpumask with the target cpu and |
| 348 | * migrate the context if needed |
| 349 | */ |
| 350 | if (target >= 0 && target < nr_cpu_ids) { |
| 351 | cpumask_set_cpu(target, &nest_imc_cpumask); |
| 352 | nest_change_cpu_context(cpu, target); |
| 353 | } else { |
| 354 | opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST, |
| 355 | get_hard_smp_processor_id(cpu)); |
| 356 | /* |
| 357 | * If this is the last cpu in this chip then, skip the reference |
| 358 | * count mutex lock and make the reference count on this chip zero. |
| 359 | */ |
| 360 | ref = get_nest_pmu_ref(cpu); |
| 361 | if (!ref) |
| 362 | return -EINVAL; |
| 363 | |
| 364 | ref->refc = 0; |
| 365 | } |
| 366 | return 0; |
| 367 | } |
| 368 | |
| 369 | static int ppc_nest_imc_cpu_online(unsigned int cpu) |
| 370 | { |
| 371 | const struct cpumask *l_cpumask; |
| 372 | static struct cpumask tmp_mask; |
| 373 | int res; |
| 374 | |
| 375 | /* Get the cpumask of this node */ |
| 376 | l_cpumask = cpumask_of_node(cpu_to_node(cpu)); |
| 377 | |
| 378 | /* |
| 379 | * If this is not the first online CPU on this node, then |
| 380 | * just return. |
| 381 | */ |
| 382 | if (cpumask_and(&tmp_mask, l_cpumask, &nest_imc_cpumask)) |
| 383 | return 0; |
| 384 | |
| 385 | /* |
| 386 | * If this is the first online cpu on this node |
| 387 | * disable the nest counters by making an OPAL call. |
| 388 | */ |
| 389 | res = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST, |
| 390 | get_hard_smp_processor_id(cpu)); |
| 391 | if (res) |
| 392 | return res; |
| 393 | |
| 394 | /* Make this CPU the designated target for counter collection */ |
| 395 | cpumask_set_cpu(cpu, &nest_imc_cpumask); |
| 396 | return 0; |
| 397 | } |
| 398 | |
| 399 | static int nest_pmu_cpumask_init(void) |
| 400 | { |
| 401 | return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE, |
| 402 | "perf/powerpc/imc:online", |
| 403 | ppc_nest_imc_cpu_online, |
| 404 | ppc_nest_imc_cpu_offline); |
| 405 | } |
| 406 | |
| 407 | static void nest_imc_counters_release(struct perf_event *event) |
| 408 | { |
| 409 | int rc, node_id; |
| 410 | struct imc_pmu_ref *ref; |
| 411 | |
| 412 | if (event->cpu < 0) |
| 413 | return; |
| 414 | |
| 415 | node_id = cpu_to_node(event->cpu); |
| 416 | |
| 417 | /* |
| 418 | * See if we need to disable the nest PMU. |
| 419 | * If no events are currently in use, then we have to take a |
| 420 | * mutex to ensure that we don't race with another task doing |
| 421 | * enable or disable the nest counters. |
| 422 | */ |
| 423 | ref = get_nest_pmu_ref(event->cpu); |
| 424 | if (!ref) |
| 425 | return; |
| 426 | |
| 427 | /* Take the mutex lock for this node and then decrement the reference count */ |
| 428 | mutex_lock(&ref->lock); |
Anju T Sudhakar | 0d92382 | 2017-10-04 12:20:52 +0530 | [diff] [blame] | 429 | if (ref->refc == 0) { |
| 430 | /* |
| 431 | * The scenario where this is true is, when perf session is |
| 432 | * started, followed by offlining of all cpus in a given node. |
| 433 | * |
| 434 | * In the cpuhotplug offline path, ppc_nest_imc_cpu_offline() |
| 435 | * function set the ref->count to zero, if the cpu which is |
| 436 | * about to offline is the last cpu in a given node and make |
| 437 | * an OPAL call to disable the engine in that node. |
| 438 | * |
| 439 | */ |
| 440 | mutex_unlock(&ref->lock); |
| 441 | return; |
| 442 | } |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 443 | ref->refc--; |
| 444 | if (ref->refc == 0) { |
| 445 | rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST, |
| 446 | get_hard_smp_processor_id(event->cpu)); |
| 447 | if (rc) { |
Madhavan Srinivasan | 711bd20 | 2017-08-16 21:51:34 +0530 | [diff] [blame] | 448 | mutex_unlock(&ref->lock); |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 449 | pr_err("nest-imc: Unable to stop the counters for core %d\n", node_id); |
| 450 | return; |
| 451 | } |
| 452 | } else if (ref->refc < 0) { |
| 453 | WARN(1, "nest-imc: Invalid event reference count\n"); |
| 454 | ref->refc = 0; |
| 455 | } |
| 456 | mutex_unlock(&ref->lock); |
| 457 | } |
| 458 | |
| 459 | static int nest_imc_event_init(struct perf_event *event) |
| 460 | { |
| 461 | int chip_id, rc, node_id; |
| 462 | u32 l_config, config = event->attr.config; |
| 463 | struct imc_mem_info *pcni; |
| 464 | struct imc_pmu *pmu; |
| 465 | struct imc_pmu_ref *ref; |
| 466 | bool flag = false; |
| 467 | |
| 468 | if (event->attr.type != event->pmu->type) |
| 469 | return -ENOENT; |
| 470 | |
| 471 | /* Sampling not supported */ |
| 472 | if (event->hw.sample_period) |
| 473 | return -EINVAL; |
| 474 | |
| 475 | /* unsupported modes and filters */ |
| 476 | if (event->attr.exclude_user || |
| 477 | event->attr.exclude_kernel || |
| 478 | event->attr.exclude_hv || |
| 479 | event->attr.exclude_idle || |
| 480 | event->attr.exclude_host || |
| 481 | event->attr.exclude_guest) |
| 482 | return -EINVAL; |
| 483 | |
| 484 | if (event->cpu < 0) |
| 485 | return -EINVAL; |
| 486 | |
| 487 | pmu = imc_event_to_pmu(event); |
| 488 | |
| 489 | /* Sanity check for config (event offset) */ |
| 490 | if ((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size) |
| 491 | return -EINVAL; |
| 492 | |
| 493 | /* |
| 494 | * Nest HW counter memory resides in a per-chip reserve-memory (HOMER). |
| 495 | * Get the base memory addresss for this cpu. |
| 496 | */ |
Michael Ellerman | f3f1dfd | 2017-10-16 00:13:41 +0530 | [diff] [blame] | 497 | chip_id = cpu_to_chip_id(event->cpu); |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 498 | pcni = pmu->mem_info; |
| 499 | do { |
| 500 | if (pcni->id == chip_id) { |
| 501 | flag = true; |
| 502 | break; |
| 503 | } |
| 504 | pcni++; |
| 505 | } while (pcni); |
| 506 | |
| 507 | if (!flag) |
| 508 | return -ENODEV; |
| 509 | |
| 510 | /* |
| 511 | * Add the event offset to the base address. |
| 512 | */ |
| 513 | l_config = config & IMC_EVENT_OFFSET_MASK; |
| 514 | event->hw.event_base = (u64)pcni->vbase + l_config; |
| 515 | node_id = cpu_to_node(event->cpu); |
| 516 | |
| 517 | /* |
| 518 | * Get the imc_pmu_ref struct for this node. |
| 519 | * Take the mutex lock and then increment the count of nest pmu events |
| 520 | * inited. |
| 521 | */ |
| 522 | ref = get_nest_pmu_ref(event->cpu); |
| 523 | if (!ref) |
| 524 | return -EINVAL; |
| 525 | |
| 526 | mutex_lock(&ref->lock); |
| 527 | if (ref->refc == 0) { |
| 528 | rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_NEST, |
| 529 | get_hard_smp_processor_id(event->cpu)); |
| 530 | if (rc) { |
Madhavan Srinivasan | 711bd20 | 2017-08-16 21:51:34 +0530 | [diff] [blame] | 531 | mutex_unlock(&ref->lock); |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 532 | pr_err("nest-imc: Unable to start the counters for node %d\n", |
| 533 | node_id); |
| 534 | return rc; |
| 535 | } |
| 536 | } |
| 537 | ++ref->refc; |
| 538 | mutex_unlock(&ref->lock); |
| 539 | |
| 540 | event->destroy = nest_imc_counters_release; |
| 541 | return 0; |
| 542 | } |
| 543 | |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 544 | /* |
| 545 | * core_imc_mem_init : Initializes memory for the current core. |
| 546 | * |
| 547 | * Uses alloc_pages_node() and uses the returned address as an argument to |
| 548 | * an opal call to configure the pdbar. The address sent as an argument is |
| 549 | * converted to physical address before the opal call is made. This is the |
| 550 | * base address at which the core imc counters are populated. |
| 551 | */ |
| 552 | static int core_imc_mem_init(int cpu, int size) |
| 553 | { |
Michael Ellerman | f3f1dfd | 2017-10-16 00:13:41 +0530 | [diff] [blame] | 554 | int nid, rc = 0, core_id = (cpu / threads_per_core); |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 555 | struct imc_mem_info *mem_info; |
| 556 | |
| 557 | /* |
| 558 | * alloc_pages_node() will allocate memory for core in the |
| 559 | * local node only. |
| 560 | */ |
Michael Ellerman | f3f1dfd | 2017-10-16 00:13:41 +0530 | [diff] [blame] | 561 | nid = cpu_to_node(cpu); |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 562 | mem_info = &core_imc_pmu->mem_info[core_id]; |
| 563 | mem_info->id = core_id; |
| 564 | |
| 565 | /* We need only vbase for core counters */ |
Michael Ellerman | f3f1dfd | 2017-10-16 00:13:41 +0530 | [diff] [blame] | 566 | mem_info->vbase = page_address(alloc_pages_node(nid, |
Anju T Sudhakar | cd4f2b3 | 2017-10-11 18:27:39 +0530 | [diff] [blame] | 567 | GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE | |
| 568 | __GFP_NOWARN, get_order(size))); |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 569 | if (!mem_info->vbase) |
| 570 | return -ENOMEM; |
| 571 | |
| 572 | /* Init the mutex */ |
| 573 | core_imc_refc[core_id].id = core_id; |
| 574 | mutex_init(&core_imc_refc[core_id].lock); |
| 575 | |
| 576 | rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_CORE, |
| 577 | __pa((void *)mem_info->vbase), |
| 578 | get_hard_smp_processor_id(cpu)); |
| 579 | if (rc) { |
| 580 | free_pages((u64)mem_info->vbase, get_order(size)); |
| 581 | mem_info->vbase = NULL; |
| 582 | } |
| 583 | |
| 584 | return rc; |
| 585 | } |
| 586 | |
| 587 | static bool is_core_imc_mem_inited(int cpu) |
| 588 | { |
| 589 | struct imc_mem_info *mem_info; |
| 590 | int core_id = (cpu / threads_per_core); |
| 591 | |
| 592 | mem_info = &core_imc_pmu->mem_info[core_id]; |
| 593 | if (!mem_info->vbase) |
| 594 | return false; |
| 595 | |
| 596 | return true; |
| 597 | } |
| 598 | |
| 599 | static int ppc_core_imc_cpu_online(unsigned int cpu) |
| 600 | { |
| 601 | const struct cpumask *l_cpumask; |
| 602 | static struct cpumask tmp_mask; |
| 603 | int ret = 0; |
| 604 | |
| 605 | /* Get the cpumask for this core */ |
| 606 | l_cpumask = cpu_sibling_mask(cpu); |
| 607 | |
| 608 | /* If a cpu for this core is already set, then, don't do anything */ |
| 609 | if (cpumask_and(&tmp_mask, l_cpumask, &core_imc_cpumask)) |
| 610 | return 0; |
| 611 | |
| 612 | if (!is_core_imc_mem_inited(cpu)) { |
| 613 | ret = core_imc_mem_init(cpu, core_imc_pmu->counter_mem_size); |
| 614 | if (ret) { |
| 615 | pr_info("core_imc memory allocation for cpu %d failed\n", cpu); |
| 616 | return ret; |
| 617 | } |
| 618 | } |
| 619 | |
| 620 | /* set the cpu in the mask */ |
| 621 | cpumask_set_cpu(cpu, &core_imc_cpumask); |
| 622 | return 0; |
| 623 | } |
| 624 | |
| 625 | static int ppc_core_imc_cpu_offline(unsigned int cpu) |
| 626 | { |
Anju T Sudhakar | 074db39 | 2017-10-31 15:22:00 +0530 | [diff] [blame] | 627 | unsigned int core_id; |
| 628 | int ncpu; |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 629 | struct imc_pmu_ref *ref; |
| 630 | |
| 631 | /* |
| 632 | * clear this cpu out of the mask, if not present in the mask, |
| 633 | * don't bother doing anything. |
| 634 | */ |
| 635 | if (!cpumask_test_and_clear_cpu(cpu, &core_imc_cpumask)) |
| 636 | return 0; |
| 637 | |
Madhavan Srinivasan | 7ecb37f | 2017-11-02 17:42:26 +0530 | [diff] [blame] | 638 | /* |
| 639 | * Check whether core_imc is registered. We could end up here |
| 640 | * if the cpuhotplug callback registration fails. i.e, callback |
| 641 | * invokes the offline path for all sucessfully registered cpus. |
| 642 | * At this stage, core_imc pmu will not be registered and we |
| 643 | * should return here. |
| 644 | * |
| 645 | * We return with a zero since this is not an offline failure. |
| 646 | * And cpuhp_setup_state() returns the actual failure reason |
| 647 | * to the caller, which inturn will call the cleanup routine. |
| 648 | */ |
| 649 | if (!core_imc_pmu->pmu.event_init) |
| 650 | return 0; |
| 651 | |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 652 | /* Find any online cpu in that core except the current "cpu" */ |
| 653 | ncpu = cpumask_any_but(cpu_sibling_mask(cpu), cpu); |
| 654 | |
| 655 | if (ncpu >= 0 && ncpu < nr_cpu_ids) { |
| 656 | cpumask_set_cpu(ncpu, &core_imc_cpumask); |
| 657 | perf_pmu_migrate_context(&core_imc_pmu->pmu, cpu, ncpu); |
| 658 | } else { |
| 659 | /* |
| 660 | * If this is the last cpu in this core then, skip taking refernce |
| 661 | * count mutex lock for this core and directly zero "refc" for |
| 662 | * this core. |
| 663 | */ |
| 664 | opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE, |
| 665 | get_hard_smp_processor_id(cpu)); |
| 666 | core_id = cpu / threads_per_core; |
| 667 | ref = &core_imc_refc[core_id]; |
| 668 | if (!ref) |
| 669 | return -EINVAL; |
| 670 | |
| 671 | ref->refc = 0; |
| 672 | } |
| 673 | return 0; |
| 674 | } |
| 675 | |
| 676 | static int core_imc_pmu_cpumask_init(void) |
| 677 | { |
| 678 | return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE, |
| 679 | "perf/powerpc/imc_core:online", |
| 680 | ppc_core_imc_cpu_online, |
| 681 | ppc_core_imc_cpu_offline); |
| 682 | } |
| 683 | |
| 684 | static void core_imc_counters_release(struct perf_event *event) |
| 685 | { |
| 686 | int rc, core_id; |
| 687 | struct imc_pmu_ref *ref; |
| 688 | |
| 689 | if (event->cpu < 0) |
| 690 | return; |
| 691 | /* |
| 692 | * See if we need to disable the IMC PMU. |
| 693 | * If no events are currently in use, then we have to take a |
| 694 | * mutex to ensure that we don't race with another task doing |
| 695 | * enable or disable the core counters. |
| 696 | */ |
| 697 | core_id = event->cpu / threads_per_core; |
| 698 | |
| 699 | /* Take the mutex lock and decrement the refernce count for this core */ |
| 700 | ref = &core_imc_refc[core_id]; |
| 701 | if (!ref) |
| 702 | return; |
| 703 | |
| 704 | mutex_lock(&ref->lock); |
Anju T Sudhakar | 0d92382 | 2017-10-04 12:20:52 +0530 | [diff] [blame] | 705 | if (ref->refc == 0) { |
| 706 | /* |
| 707 | * The scenario where this is true is, when perf session is |
| 708 | * started, followed by offlining of all cpus in a given core. |
| 709 | * |
| 710 | * In the cpuhotplug offline path, ppc_core_imc_cpu_offline() |
| 711 | * function set the ref->count to zero, if the cpu which is |
| 712 | * about to offline is the last cpu in a given core and make |
| 713 | * an OPAL call to disable the engine in that core. |
| 714 | * |
| 715 | */ |
| 716 | mutex_unlock(&ref->lock); |
| 717 | return; |
| 718 | } |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 719 | ref->refc--; |
| 720 | if (ref->refc == 0) { |
| 721 | rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE, |
| 722 | get_hard_smp_processor_id(event->cpu)); |
| 723 | if (rc) { |
| 724 | mutex_unlock(&ref->lock); |
| 725 | pr_err("IMC: Unable to stop the counters for core %d\n", core_id); |
| 726 | return; |
| 727 | } |
| 728 | } else if (ref->refc < 0) { |
| 729 | WARN(1, "core-imc: Invalid event reference count\n"); |
| 730 | ref->refc = 0; |
| 731 | } |
| 732 | mutex_unlock(&ref->lock); |
| 733 | } |
| 734 | |
| 735 | static int core_imc_event_init(struct perf_event *event) |
| 736 | { |
| 737 | int core_id, rc; |
| 738 | u64 config = event->attr.config; |
| 739 | struct imc_mem_info *pcmi; |
| 740 | struct imc_pmu *pmu; |
| 741 | struct imc_pmu_ref *ref; |
| 742 | |
| 743 | if (event->attr.type != event->pmu->type) |
| 744 | return -ENOENT; |
| 745 | |
| 746 | /* Sampling not supported */ |
| 747 | if (event->hw.sample_period) |
| 748 | return -EINVAL; |
| 749 | |
| 750 | /* unsupported modes and filters */ |
| 751 | if (event->attr.exclude_user || |
| 752 | event->attr.exclude_kernel || |
| 753 | event->attr.exclude_hv || |
| 754 | event->attr.exclude_idle || |
| 755 | event->attr.exclude_host || |
| 756 | event->attr.exclude_guest) |
| 757 | return -EINVAL; |
| 758 | |
| 759 | if (event->cpu < 0) |
| 760 | return -EINVAL; |
| 761 | |
| 762 | event->hw.idx = -1; |
| 763 | pmu = imc_event_to_pmu(event); |
| 764 | |
| 765 | /* Sanity check for config (event offset) */ |
| 766 | if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)) |
| 767 | return -EINVAL; |
| 768 | |
| 769 | if (!is_core_imc_mem_inited(event->cpu)) |
| 770 | return -ENODEV; |
| 771 | |
| 772 | core_id = event->cpu / threads_per_core; |
| 773 | pcmi = &core_imc_pmu->mem_info[core_id]; |
| 774 | if ((!pcmi->vbase)) |
| 775 | return -ENODEV; |
| 776 | |
| 777 | /* Get the core_imc mutex for this core */ |
| 778 | ref = &core_imc_refc[core_id]; |
| 779 | if (!ref) |
| 780 | return -EINVAL; |
| 781 | |
| 782 | /* |
| 783 | * Core pmu units are enabled only when it is used. |
| 784 | * See if this is triggered for the first time. |
| 785 | * If yes, take the mutex lock and enable the core counters. |
| 786 | * If not, just increment the count in core_imc_refc struct. |
| 787 | */ |
| 788 | mutex_lock(&ref->lock); |
| 789 | if (ref->refc == 0) { |
| 790 | rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE, |
| 791 | get_hard_smp_processor_id(event->cpu)); |
| 792 | if (rc) { |
| 793 | mutex_unlock(&ref->lock); |
| 794 | pr_err("core-imc: Unable to start the counters for core %d\n", |
| 795 | core_id); |
| 796 | return rc; |
| 797 | } |
| 798 | } |
| 799 | ++ref->refc; |
| 800 | mutex_unlock(&ref->lock); |
| 801 | |
| 802 | event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK); |
| 803 | event->destroy = core_imc_counters_release; |
| 804 | return 0; |
| 805 | } |
| 806 | |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 807 | /* |
| 808 | * Allocates a page of memory for each of the online cpus, and write the |
| 809 | * physical base address of that page to the LDBAR for that cpu. |
| 810 | * |
| 811 | * LDBAR Register Layout: |
| 812 | * |
| 813 | * 0 4 8 12 16 20 24 28 |
| 814 | * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | |
| 815 | * | | [ ] [ Counter Address [8:50] |
| 816 | * | * Mode | |
| 817 | * | * PB Scope |
| 818 | * * Enable/Disable |
| 819 | * |
| 820 | * 32 36 40 44 48 52 56 60 |
| 821 | * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | |
| 822 | * Counter Address [8:50] ] |
| 823 | * |
| 824 | */ |
| 825 | static int thread_imc_mem_alloc(int cpu_id, int size) |
| 826 | { |
| 827 | u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, cpu_id); |
Michael Ellerman | f3f1dfd | 2017-10-16 00:13:41 +0530 | [diff] [blame] | 828 | int nid = cpu_to_node(cpu_id); |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 829 | |
| 830 | if (!local_mem) { |
| 831 | /* |
| 832 | * This case could happen only once at start, since we dont |
| 833 | * free the memory in cpu offline path. |
| 834 | */ |
Michael Ellerman | f3f1dfd | 2017-10-16 00:13:41 +0530 | [diff] [blame] | 835 | local_mem = page_address(alloc_pages_node(nid, |
Anju T Sudhakar | cd4f2b3 | 2017-10-11 18:27:39 +0530 | [diff] [blame] | 836 | GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE | |
| 837 | __GFP_NOWARN, get_order(size))); |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 838 | if (!local_mem) |
| 839 | return -ENOMEM; |
| 840 | |
| 841 | per_cpu(thread_imc_mem, cpu_id) = local_mem; |
| 842 | } |
| 843 | |
| 844 | ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE; |
| 845 | |
| 846 | mtspr(SPRN_LDBAR, ldbar_value); |
| 847 | return 0; |
| 848 | } |
| 849 | |
| 850 | static int ppc_thread_imc_cpu_online(unsigned int cpu) |
| 851 | { |
| 852 | return thread_imc_mem_alloc(cpu, thread_imc_mem_size); |
| 853 | } |
| 854 | |
| 855 | static int ppc_thread_imc_cpu_offline(unsigned int cpu) |
| 856 | { |
| 857 | mtspr(SPRN_LDBAR, 0); |
| 858 | return 0; |
| 859 | } |
| 860 | |
| 861 | static int thread_imc_cpu_init(void) |
| 862 | { |
| 863 | return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE, |
| 864 | "perf/powerpc/imc_thread:online", |
| 865 | ppc_thread_imc_cpu_online, |
| 866 | ppc_thread_imc_cpu_offline); |
| 867 | } |
| 868 | |
| 869 | void thread_imc_pmu_sched_task(struct perf_event_context *ctx, |
| 870 | bool sched_in) |
| 871 | { |
| 872 | int core_id; |
| 873 | struct imc_pmu_ref *ref; |
| 874 | |
| 875 | if (!is_core_imc_mem_inited(smp_processor_id())) |
| 876 | return; |
| 877 | |
| 878 | core_id = smp_processor_id() / threads_per_core; |
| 879 | /* |
| 880 | * imc pmus are enabled only when it is used. |
| 881 | * See if this is triggered for the first time. |
| 882 | * If yes, take the mutex lock and enable the counters. |
| 883 | * If not, just increment the count in ref count struct. |
| 884 | */ |
| 885 | ref = &core_imc_refc[core_id]; |
| 886 | if (!ref) |
| 887 | return; |
| 888 | |
| 889 | if (sched_in) { |
| 890 | mutex_lock(&ref->lock); |
| 891 | if (ref->refc == 0) { |
| 892 | if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE, |
| 893 | get_hard_smp_processor_id(smp_processor_id()))) { |
| 894 | mutex_unlock(&ref->lock); |
| 895 | pr_err("thread-imc: Unable to start the counter\ |
| 896 | for core %d\n", core_id); |
| 897 | return; |
| 898 | } |
| 899 | } |
| 900 | ++ref->refc; |
| 901 | mutex_unlock(&ref->lock); |
| 902 | } else { |
| 903 | mutex_lock(&ref->lock); |
| 904 | ref->refc--; |
| 905 | if (ref->refc == 0) { |
| 906 | if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE, |
| 907 | get_hard_smp_processor_id(smp_processor_id()))) { |
| 908 | mutex_unlock(&ref->lock); |
| 909 | pr_err("thread-imc: Unable to stop the counters\ |
| 910 | for core %d\n", core_id); |
| 911 | return; |
| 912 | } |
| 913 | } else if (ref->refc < 0) { |
| 914 | ref->refc = 0; |
| 915 | } |
| 916 | mutex_unlock(&ref->lock); |
| 917 | } |
| 918 | |
| 919 | return; |
| 920 | } |
| 921 | |
| 922 | static int thread_imc_event_init(struct perf_event *event) |
| 923 | { |
| 924 | u32 config = event->attr.config; |
| 925 | struct task_struct *target; |
| 926 | struct imc_pmu *pmu; |
| 927 | |
| 928 | if (event->attr.type != event->pmu->type) |
| 929 | return -ENOENT; |
| 930 | |
| 931 | /* Sampling not supported */ |
| 932 | if (event->hw.sample_period) |
| 933 | return -EINVAL; |
| 934 | |
| 935 | event->hw.idx = -1; |
| 936 | pmu = imc_event_to_pmu(event); |
| 937 | |
| 938 | /* Sanity check for config offset */ |
| 939 | if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)) |
| 940 | return -EINVAL; |
| 941 | |
| 942 | target = event->hw.target; |
| 943 | if (!target) |
| 944 | return -EINVAL; |
| 945 | |
| 946 | event->pmu->task_ctx_nr = perf_sw_context; |
| 947 | return 0; |
| 948 | } |
| 949 | |
| 950 | static bool is_thread_imc_pmu(struct perf_event *event) |
| 951 | { |
| 952 | if (!strncmp(event->pmu->name, "thread_imc", strlen("thread_imc"))) |
| 953 | return true; |
| 954 | |
| 955 | return false; |
| 956 | } |
| 957 | |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 958 | static u64 * get_event_base_addr(struct perf_event *event) |
| 959 | { |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 960 | u64 addr; |
| 961 | |
| 962 | if (is_thread_imc_pmu(event)) { |
| 963 | addr = (u64)per_cpu(thread_imc_mem, smp_processor_id()); |
| 964 | return (u64 *)(addr + (event->attr.config & IMC_EVENT_OFFSET_MASK)); |
| 965 | } |
| 966 | |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 967 | return (u64 *)event->hw.event_base; |
| 968 | } |
| 969 | |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 970 | static void thread_imc_pmu_start_txn(struct pmu *pmu, |
| 971 | unsigned int txn_flags) |
| 972 | { |
| 973 | if (txn_flags & ~PERF_PMU_TXN_ADD) |
| 974 | return; |
| 975 | perf_pmu_disable(pmu); |
| 976 | } |
| 977 | |
| 978 | static void thread_imc_pmu_cancel_txn(struct pmu *pmu) |
| 979 | { |
| 980 | perf_pmu_enable(pmu); |
| 981 | } |
| 982 | |
| 983 | static int thread_imc_pmu_commit_txn(struct pmu *pmu) |
| 984 | { |
| 985 | perf_pmu_enable(pmu); |
| 986 | return 0; |
| 987 | } |
| 988 | |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 989 | static u64 imc_read_counter(struct perf_event *event) |
| 990 | { |
| 991 | u64 *addr, data; |
| 992 | |
| 993 | /* |
| 994 | * In-Memory Collection (IMC) counters are free flowing counters. |
| 995 | * So we take a snapshot of the counter value on enable and save it |
| 996 | * to calculate the delta at later stage to present the event counter |
| 997 | * value. |
| 998 | */ |
| 999 | addr = get_event_base_addr(event); |
| 1000 | data = be64_to_cpu(READ_ONCE(*addr)); |
| 1001 | local64_set(&event->hw.prev_count, data); |
| 1002 | |
| 1003 | return data; |
| 1004 | } |
| 1005 | |
| 1006 | static void imc_event_update(struct perf_event *event) |
| 1007 | { |
| 1008 | u64 counter_prev, counter_new, final_count; |
| 1009 | |
| 1010 | counter_prev = local64_read(&event->hw.prev_count); |
| 1011 | counter_new = imc_read_counter(event); |
| 1012 | final_count = counter_new - counter_prev; |
| 1013 | |
| 1014 | /* Update the delta to the event count */ |
| 1015 | local64_add(final_count, &event->count); |
| 1016 | } |
| 1017 | |
| 1018 | static void imc_event_start(struct perf_event *event, int flags) |
| 1019 | { |
| 1020 | /* |
| 1021 | * In Memory Counters are free flowing counters. HW or the microcode |
| 1022 | * keeps adding to the counter offset in memory. To get event |
| 1023 | * counter value, we snapshot the value here and we calculate |
| 1024 | * delta at later point. |
| 1025 | */ |
| 1026 | imc_read_counter(event); |
| 1027 | } |
| 1028 | |
| 1029 | static void imc_event_stop(struct perf_event *event, int flags) |
| 1030 | { |
| 1031 | /* |
| 1032 | * Take a snapshot and calculate the delta and update |
| 1033 | * the event counter values. |
| 1034 | */ |
| 1035 | imc_event_update(event); |
| 1036 | } |
| 1037 | |
| 1038 | static int imc_event_add(struct perf_event *event, int flags) |
| 1039 | { |
| 1040 | if (flags & PERF_EF_START) |
| 1041 | imc_event_start(event, flags); |
| 1042 | |
| 1043 | return 0; |
| 1044 | } |
| 1045 | |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 1046 | static int thread_imc_event_add(struct perf_event *event, int flags) |
| 1047 | { |
| 1048 | if (flags & PERF_EF_START) |
| 1049 | imc_event_start(event, flags); |
| 1050 | |
| 1051 | /* Enable the sched_task to start the engine */ |
| 1052 | perf_sched_cb_inc(event->ctx->pmu); |
| 1053 | return 0; |
| 1054 | } |
| 1055 | |
| 1056 | static void thread_imc_event_del(struct perf_event *event, int flags) |
| 1057 | { |
| 1058 | /* |
| 1059 | * Take a snapshot and calculate the delta and update |
| 1060 | * the event counter values. |
| 1061 | */ |
| 1062 | imc_event_update(event); |
| 1063 | perf_sched_cb_dec(event->ctx->pmu); |
| 1064 | } |
| 1065 | |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1066 | /* update_pmu_ops : Populate the appropriate operations for "pmu" */ |
| 1067 | static int update_pmu_ops(struct imc_pmu *pmu) |
| 1068 | { |
| 1069 | pmu->pmu.task_ctx_nr = perf_invalid_context; |
| 1070 | pmu->pmu.add = imc_event_add; |
| 1071 | pmu->pmu.del = imc_event_stop; |
| 1072 | pmu->pmu.start = imc_event_start; |
| 1073 | pmu->pmu.stop = imc_event_stop; |
| 1074 | pmu->pmu.read = imc_event_update; |
| 1075 | pmu->pmu.attr_groups = pmu->attr_groups; |
| 1076 | pmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group; |
| 1077 | |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1078 | switch (pmu->domain) { |
| 1079 | case IMC_DOMAIN_NEST: |
| 1080 | pmu->pmu.event_init = nest_imc_event_init; |
| 1081 | pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group; |
| 1082 | break; |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 1083 | case IMC_DOMAIN_CORE: |
| 1084 | pmu->pmu.event_init = core_imc_event_init; |
| 1085 | pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group; |
| 1086 | break; |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 1087 | case IMC_DOMAIN_THREAD: |
| 1088 | pmu->pmu.event_init = thread_imc_event_init; |
| 1089 | pmu->pmu.sched_task = thread_imc_pmu_sched_task; |
| 1090 | pmu->pmu.add = thread_imc_event_add; |
| 1091 | pmu->pmu.del = thread_imc_event_del; |
| 1092 | pmu->pmu.start_txn = thread_imc_pmu_start_txn; |
| 1093 | pmu->pmu.cancel_txn = thread_imc_pmu_cancel_txn; |
| 1094 | pmu->pmu.commit_txn = thread_imc_pmu_commit_txn; |
| 1095 | break; |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1096 | default: |
| 1097 | break; |
| 1098 | } |
| 1099 | |
| 1100 | return 0; |
| 1101 | } |
| 1102 | |
| 1103 | /* init_nest_pmu_ref: Initialize the imc_pmu_ref struct for all the nodes */ |
| 1104 | static int init_nest_pmu_ref(void) |
| 1105 | { |
| 1106 | int nid, i, cpu; |
| 1107 | |
| 1108 | nest_imc_refc = kcalloc(num_possible_nodes(), sizeof(*nest_imc_refc), |
| 1109 | GFP_KERNEL); |
| 1110 | |
| 1111 | if (!nest_imc_refc) |
| 1112 | return -ENOMEM; |
| 1113 | |
| 1114 | i = 0; |
| 1115 | for_each_node(nid) { |
| 1116 | /* |
| 1117 | * Mutex lock to avoid races while tracking the number of |
| 1118 | * sessions using the chip's nest pmu units. |
| 1119 | */ |
| 1120 | mutex_init(&nest_imc_refc[i].lock); |
| 1121 | |
| 1122 | /* |
| 1123 | * Loop to init the "id" with the node_id. Variable "i" initialized to |
| 1124 | * 0 and will be used as index to the array. "i" will not go off the |
| 1125 | * end of the array since the "for_each_node" loops for "N_POSSIBLE" |
| 1126 | * nodes only. |
| 1127 | */ |
| 1128 | nest_imc_refc[i++].id = nid; |
| 1129 | } |
| 1130 | |
| 1131 | /* |
| 1132 | * Loop to init the per_cpu "local_nest_imc_refc" with the proper |
| 1133 | * "nest_imc_refc" index. This makes get_nest_pmu_ref() alot simple. |
| 1134 | */ |
| 1135 | for_each_possible_cpu(cpu) { |
| 1136 | nid = cpu_to_node(cpu); |
Anju T | 7efbae9 | 2017-08-14 17:12:23 +0530 | [diff] [blame] | 1137 | for (i = 0; i < num_possible_nodes(); i++) { |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1138 | if (nest_imc_refc[i].id == nid) { |
| 1139 | per_cpu(local_nest_imc_refc, cpu) = &nest_imc_refc[i]; |
| 1140 | break; |
| 1141 | } |
| 1142 | } |
| 1143 | } |
| 1144 | return 0; |
| 1145 | } |
| 1146 | |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 1147 | static void cleanup_all_core_imc_memory(void) |
| 1148 | { |
Guilherme G. Piccoli | 0b167f1 | 2017-10-19 17:41:33 -0200 | [diff] [blame] | 1149 | int i, nr_cores = DIV_ROUND_UP(num_present_cpus(), threads_per_core); |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 1150 | struct imc_mem_info *ptr = core_imc_pmu->mem_info; |
| 1151 | int size = core_imc_pmu->counter_mem_size; |
| 1152 | |
| 1153 | /* mem_info will never be NULL */ |
| 1154 | for (i = 0; i < nr_cores; i++) { |
| 1155 | if (ptr[i].vbase) |
| 1156 | free_pages((u64)ptr->vbase, get_order(size)); |
| 1157 | } |
| 1158 | |
| 1159 | kfree(ptr); |
| 1160 | kfree(core_imc_refc); |
| 1161 | } |
| 1162 | |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 1163 | static void thread_imc_ldbar_disable(void *dummy) |
| 1164 | { |
| 1165 | /* |
| 1166 | * By Zeroing LDBAR, we disable thread-imc |
| 1167 | * updates. |
| 1168 | */ |
| 1169 | mtspr(SPRN_LDBAR, 0); |
| 1170 | } |
| 1171 | |
| 1172 | void thread_imc_disable(void) |
| 1173 | { |
| 1174 | on_each_cpu(thread_imc_ldbar_disable, NULL, 1); |
| 1175 | } |
| 1176 | |
| 1177 | static void cleanup_all_thread_imc_memory(void) |
| 1178 | { |
| 1179 | int i, order = get_order(thread_imc_mem_size); |
| 1180 | |
| 1181 | for_each_online_cpu(i) { |
| 1182 | if (per_cpu(thread_imc_mem, i)) |
| 1183 | free_pages((u64)per_cpu(thread_imc_mem, i), order); |
| 1184 | |
| 1185 | } |
| 1186 | } |
| 1187 | |
Anju T Sudhakar | ed8e443 | 2017-12-11 11:28:36 +0530 | [diff] [blame] | 1188 | /* Function to free the attr_groups which are dynamically allocated */ |
| 1189 | static void imc_common_mem_free(struct imc_pmu *pmu_ptr) |
| 1190 | { |
| 1191 | if (pmu_ptr->attr_groups[IMC_EVENT_ATTR]) |
| 1192 | kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs); |
| 1193 | kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]); |
| 1194 | kfree(pmu_ptr); |
Anju T Sudhakar | ed8e443 | 2017-12-11 11:28:36 +0530 | [diff] [blame] | 1195 | } |
| 1196 | |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1197 | /* |
| 1198 | * Common function to unregister cpu hotplug callback and |
| 1199 | * free the memory. |
| 1200 | * TODO: Need to handle pmu unregistering, which will be |
| 1201 | * done in followup series. |
| 1202 | */ |
| 1203 | static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr) |
| 1204 | { |
| 1205 | if (pmu_ptr->domain == IMC_DOMAIN_NEST) { |
Dan Carpenter | b3376dc | 2017-08-11 23:05:41 +0300 | [diff] [blame] | 1206 | mutex_lock(&nest_init_lock); |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1207 | if (nest_pmus == 1) { |
| 1208 | cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE); |
| 1209 | kfree(nest_imc_refc); |
Anju T Sudhakar | 110df8b | 2017-12-07 22:53:27 +0530 | [diff] [blame] | 1210 | kfree(per_nest_pmu_arr); |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1211 | } |
| 1212 | |
| 1213 | if (nest_pmus > 0) |
| 1214 | nest_pmus--; |
| 1215 | mutex_unlock(&nest_init_lock); |
| 1216 | } |
| 1217 | |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 1218 | /* Free core_imc memory */ |
| 1219 | if (pmu_ptr->domain == IMC_DOMAIN_CORE) { |
| 1220 | cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE); |
| 1221 | cleanup_all_core_imc_memory(); |
| 1222 | } |
| 1223 | |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 1224 | /* Free thread_imc memory */ |
| 1225 | if (pmu_ptr->domain == IMC_DOMAIN_THREAD) { |
| 1226 | cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE); |
| 1227 | cleanup_all_thread_imc_memory(); |
| 1228 | } |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1229 | } |
| 1230 | |
| 1231 | |
| 1232 | /* |
| 1233 | * imc_mem_init : Function to support memory allocation for core imc. |
| 1234 | */ |
| 1235 | static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent, |
| 1236 | int pmu_index) |
| 1237 | { |
| 1238 | const char *s; |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 1239 | int nr_cores, cpu, res; |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1240 | |
| 1241 | if (of_property_read_string(parent, "name", &s)) |
| 1242 | return -ENODEV; |
| 1243 | |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1244 | switch (pmu_ptr->domain) { |
| 1245 | case IMC_DOMAIN_NEST: |
| 1246 | /* Update the pmu name */ |
| 1247 | pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s_imc", "nest_", s); |
| 1248 | if (!pmu_ptr->pmu.name) |
| 1249 | return -ENOMEM; |
| 1250 | |
| 1251 | /* Needed for hotplug/migration */ |
Madhavan Srinivasan | 73ce9aec | 2017-11-22 10:45:39 +0530 | [diff] [blame] | 1252 | if (!per_nest_pmu_arr) { |
| 1253 | per_nest_pmu_arr = kcalloc(get_max_nest_dev() + 1, |
| 1254 | sizeof(struct imc_pmu *), |
| 1255 | GFP_KERNEL); |
| 1256 | if (!per_nest_pmu_arr) |
| 1257 | return -ENOMEM; |
| 1258 | } |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1259 | per_nest_pmu_arr[pmu_index] = pmu_ptr; |
| 1260 | break; |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 1261 | case IMC_DOMAIN_CORE: |
| 1262 | /* Update the pmu name */ |
| 1263 | pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc"); |
| 1264 | if (!pmu_ptr->pmu.name) |
| 1265 | return -ENOMEM; |
| 1266 | |
Guilherme G. Piccoli | 0b167f1 | 2017-10-19 17:41:33 -0200 | [diff] [blame] | 1267 | nr_cores = DIV_ROUND_UP(num_present_cpus(), threads_per_core); |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 1268 | pmu_ptr->mem_info = kcalloc(nr_cores, sizeof(struct imc_mem_info), |
| 1269 | GFP_KERNEL); |
| 1270 | |
| 1271 | if (!pmu_ptr->mem_info) |
| 1272 | return -ENOMEM; |
| 1273 | |
| 1274 | core_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref), |
| 1275 | GFP_KERNEL); |
| 1276 | |
Anju T Sudhakar | ed8e443 | 2017-12-11 11:28:36 +0530 | [diff] [blame] | 1277 | if (!core_imc_refc) { |
| 1278 | kfree(pmu_ptr->mem_info); |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 1279 | return -ENOMEM; |
Anju T Sudhakar | ed8e443 | 2017-12-11 11:28:36 +0530 | [diff] [blame] | 1280 | } |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 1281 | |
| 1282 | core_imc_pmu = pmu_ptr; |
| 1283 | break; |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 1284 | case IMC_DOMAIN_THREAD: |
| 1285 | /* Update the pmu name */ |
| 1286 | pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc"); |
| 1287 | if (!pmu_ptr->pmu.name) |
| 1288 | return -ENOMEM; |
| 1289 | |
| 1290 | thread_imc_mem_size = pmu_ptr->counter_mem_size; |
| 1291 | for_each_online_cpu(cpu) { |
| 1292 | res = thread_imc_mem_alloc(cpu, pmu_ptr->counter_mem_size); |
Anju T Sudhakar | ed8e443 | 2017-12-11 11:28:36 +0530 | [diff] [blame] | 1293 | if (res) { |
| 1294 | cleanup_all_thread_imc_memory(); |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 1295 | return res; |
Anju T Sudhakar | ed8e443 | 2017-12-11 11:28:36 +0530 | [diff] [blame] | 1296 | } |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 1297 | } |
| 1298 | |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 1299 | break; |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1300 | default: |
| 1301 | return -EINVAL; |
| 1302 | } |
| 1303 | |
| 1304 | return 0; |
| 1305 | } |
| 1306 | |
| 1307 | /* |
| 1308 | * init_imc_pmu : Setup and register the IMC pmu device. |
| 1309 | * |
| 1310 | * @parent: Device tree unit node |
| 1311 | * @pmu_ptr: memory allocated for this pmu |
| 1312 | * @pmu_idx: Count of nest pmc registered |
| 1313 | * |
| 1314 | * init_imc_pmu() setup pmu cpumask and registers for a cpu hotplug callback. |
| 1315 | * Handles failure cases and accordingly frees memory. |
| 1316 | */ |
| 1317 | int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_idx) |
| 1318 | { |
| 1319 | int ret; |
| 1320 | |
| 1321 | ret = imc_mem_init(pmu_ptr, parent, pmu_idx); |
Anju T Sudhakar | ed8e443 | 2017-12-11 11:28:36 +0530 | [diff] [blame] | 1322 | if (ret) { |
| 1323 | imc_common_mem_free(pmu_ptr); |
| 1324 | return ret; |
| 1325 | } |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1326 | |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1327 | switch (pmu_ptr->domain) { |
| 1328 | case IMC_DOMAIN_NEST: |
| 1329 | /* |
| 1330 | * Nest imc pmu need only one cpu per chip, we initialize the |
| 1331 | * cpumask for the first nest imc pmu and use the same for the |
| 1332 | * rest. To handle the cpuhotplug callback unregister, we track |
| 1333 | * the number of nest pmus in "nest_pmus". |
| 1334 | */ |
| 1335 | mutex_lock(&nest_init_lock); |
| 1336 | if (nest_pmus == 0) { |
| 1337 | ret = init_nest_pmu_ref(); |
| 1338 | if (ret) { |
| 1339 | mutex_unlock(&nest_init_lock); |
| 1340 | goto err_free; |
| 1341 | } |
| 1342 | /* Register for cpu hotplug notification. */ |
| 1343 | ret = nest_pmu_cpumask_init(); |
| 1344 | if (ret) { |
| 1345 | mutex_unlock(&nest_init_lock); |
Anju T Sudhakar | 110df8b | 2017-12-07 22:53:27 +0530 | [diff] [blame] | 1346 | kfree(nest_imc_refc); |
| 1347 | kfree(per_nest_pmu_arr); |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1348 | goto err_free; |
| 1349 | } |
| 1350 | } |
| 1351 | nest_pmus++; |
| 1352 | mutex_unlock(&nest_init_lock); |
| 1353 | break; |
Anju T Sudhakar | 39a846d | 2017-07-19 03:06:35 +0530 | [diff] [blame] | 1354 | case IMC_DOMAIN_CORE: |
| 1355 | ret = core_imc_pmu_cpumask_init(); |
| 1356 | if (ret) { |
| 1357 | cleanup_all_core_imc_memory(); |
| 1358 | return ret; |
| 1359 | } |
| 1360 | |
| 1361 | break; |
Anju T Sudhakar | f74c89b | 2017-07-19 03:06:36 +0530 | [diff] [blame] | 1362 | case IMC_DOMAIN_THREAD: |
| 1363 | ret = thread_imc_cpu_init(); |
| 1364 | if (ret) { |
| 1365 | cleanup_all_thread_imc_memory(); |
| 1366 | return ret; |
| 1367 | } |
| 1368 | |
| 1369 | break; |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1370 | default: |
| 1371 | return -1; /* Unknown domain */ |
| 1372 | } |
| 1373 | |
| 1374 | ret = update_events_in_group(parent, pmu_ptr); |
| 1375 | if (ret) |
| 1376 | goto err_free; |
| 1377 | |
| 1378 | ret = update_pmu_ops(pmu_ptr); |
| 1379 | if (ret) |
| 1380 | goto err_free; |
| 1381 | |
| 1382 | ret = perf_pmu_register(&pmu_ptr->pmu, pmu_ptr->pmu.name, -1); |
| 1383 | if (ret) |
| 1384 | goto err_free; |
| 1385 | |
| 1386 | pr_info("%s performance monitor hardware support registered\n", |
| 1387 | pmu_ptr->pmu.name); |
| 1388 | |
| 1389 | return 0; |
| 1390 | |
| 1391 | err_free: |
Anju T Sudhakar | ed8e443 | 2017-12-11 11:28:36 +0530 | [diff] [blame] | 1392 | imc_common_mem_free(pmu_ptr); |
Anju T Sudhakar | 885dcd7 | 2017-07-19 03:06:34 +0530 | [diff] [blame] | 1393 | imc_common_cpuhp_mem_free(pmu_ptr); |
| 1394 | return ret; |
| 1395 | } |