Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 2 | /* |
| 3 | * arch/arm/mach-ep93xx/include/mach/hardware.h |
| 4 | */ |
Hubert Feurstein | 43234b1 | 2009-11-17 18:10:48 +0100 | [diff] [blame] | 5 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 6 | #ifndef __ASM_ARCH_HARDWARE_H |
| 7 | #define __ASM_ARCH_HARDWARE_H |
| 8 | |
Arnd Bergmann | 5b7cc90 | 2019-04-15 22:17:12 +0200 | [diff] [blame] | 9 | #include "platform.h" |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 10 | |
Hartley Sweeten | 701fac8 | 2009-06-30 23:06:43 +0100 | [diff] [blame] | 11 | /* |
| 12 | * The EP93xx has two external crystal oscillators. To generate the |
| 13 | * required high-frequency clocks, the processor uses two phase-locked- |
| 14 | * loops (PLLs) to multiply the incoming external clock signal to much |
| 15 | * higher frequencies that are then divided down by programmable dividers |
| 16 | * to produce the needed clocks. The PLLs operate independently of one |
| 17 | * another. |
| 18 | */ |
| 19 | #define EP93XX_EXT_CLK_RATE 14745600 |
| 20 | #define EP93XX_EXT_RTC_RATE 32768 |
| 21 | |
| 22 | #define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4) |
| 23 | #define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16) |
| 24 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 25 | #endif |