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Jerome Brunet7713a702018-07-17 17:42:56 +02001* Amlogic Audio TDM formatters
2
3Required properties:
4- compatible: 'amlogic,axg-tdmin' or
Jerome Brunet679f4e62019-04-04 13:17:28 +02005 'amlogic,axg-tdmout' or
6 'amlogic,g12a-tdmin' or
Jerome Brunetf4663092019-09-05 14:01:13 +02007 'amlogic,g12a-tdmout' or
8 'amlogic,sm1-tdmin' or
9 'amlogic,sm1-tdmout
Jerome Brunet7713a702018-07-17 17:42:56 +020010- reg: physical base address of the controller and length of memory
11 mapped region.
12- clocks: list of clock phandle, one for each entry clock-names.
13- clock-names: should contain the following:
14 * "pclk" : peripheral clock.
15 * "sclk" : bit clock.
16 * "sclk_sel" : bit clock input multiplexer.
17 * "lrclk" : sample clock
18 * "lrclk_sel": sample clock input multiplexer
19
Jerome Brunet094380e2019-07-03 14:07:48 +020020Optional property:
21- resets: phandle to the dedicated reset line of the tdm formatter.
22
23Example of TDMOUT_A on the S905X2 SoC:
Jerome Brunet7713a702018-07-17 17:42:56 +020024
25tdmout_a: audio-controller@500 {
26 compatible = "amlogic,axg-tdmout";
27 reg = <0x0 0x500 0x0 0x40>;
Jerome Brunet094380e2019-07-03 14:07:48 +020028 resets = <&clkc_audio AUD_RESET_TDMOUT_A>;
Jerome Brunet7713a702018-07-17 17:42:56 +020029 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
30 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
31 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
32 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
33 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
34 clock-names = "pclk", "sclk", "sclk_sel",
35 "lrclk", "lrclk_sel";
36};