Thomas Gleixner | 1802d0b | 2019-05-27 08:55:21 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2015 MediaTek Inc. |
| 4 | * Author: Leilk Liu <leilk.liu@mediatek.com> |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <linux/clk.h> |
| 8 | #include <linux/device.h> |
| 9 | #include <linux/err.h> |
| 10 | #include <linux/interrupt.h> |
Leilk Liu | dd69a0a | 2015-08-24 11:45:15 +0800 | [diff] [blame] | 11 | #include <linux/io.h> |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 12 | #include <linux/ioport.h> |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/of.h> |
Linus Walleij | 1a5a87d | 2022-01-22 01:33:02 +0100 | [diff] [blame] | 15 | #include <linux/gpio/consumer.h> |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/platform_data/spi-mt65xx.h> |
| 18 | #include <linux/pm_runtime.h> |
| 19 | #include <linux/spi/spi.h> |
Leilk Liu | 9f763fd | 2022-03-21 09:39:20 +0800 | [diff] [blame] | 20 | #include <linux/spi/spi-mem.h> |
luhua.xu | fdeae8f | 2019-09-11 05:55:31 -0400 | [diff] [blame] | 21 | #include <linux/dma-mapping.h> |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 22 | |
AngeloGioacchino Del Regno | 8e8a9e3 | 2022-04-07 13:44:28 +0200 | [diff] [blame] | 23 | #define SPI_CFG0_REG 0x0000 |
| 24 | #define SPI_CFG1_REG 0x0004 |
| 25 | #define SPI_TX_SRC_REG 0x0008 |
| 26 | #define SPI_RX_DST_REG 0x000c |
| 27 | #define SPI_TX_DATA_REG 0x0010 |
| 28 | #define SPI_RX_DATA_REG 0x0014 |
| 29 | #define SPI_CMD_REG 0x0018 |
| 30 | #define SPI_STATUS0_REG 0x001c |
| 31 | #define SPI_PAD_SEL_REG 0x0024 |
| 32 | #define SPI_CFG2_REG 0x0028 |
| 33 | #define SPI_TX_SRC_REG_64 0x002c |
| 34 | #define SPI_RX_DST_REG_64 0x0030 |
| 35 | #define SPI_CFG3_IPM_REG 0x0040 |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 36 | |
AngeloGioacchino Del Regno | 8e8a9e3 | 2022-04-07 13:44:28 +0200 | [diff] [blame] | 37 | #define SPI_CFG0_SCK_HIGH_OFFSET 0 |
| 38 | #define SPI_CFG0_SCK_LOW_OFFSET 8 |
| 39 | #define SPI_CFG0_CS_HOLD_OFFSET 16 |
| 40 | #define SPI_CFG0_CS_SETUP_OFFSET 24 |
| 41 | #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 |
| 42 | #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 43 | |
AngeloGioacchino Del Regno | 8e8a9e3 | 2022-04-07 13:44:28 +0200 | [diff] [blame] | 44 | #define SPI_CFG1_CS_IDLE_OFFSET 0 |
| 45 | #define SPI_CFG1_PACKET_LOOP_OFFSET 8 |
| 46 | #define SPI_CFG1_PACKET_LENGTH_OFFSET 16 |
| 47 | #define SPI_CFG1_GET_TICK_DLY_OFFSET 29 |
| 48 | #define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30 |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 49 | |
AngeloGioacchino Del Regno | 8e8a9e3 | 2022-04-07 13:44:28 +0200 | [diff] [blame] | 50 | #define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000 |
| 51 | #define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000 |
Leilk Liu | 03b1be3 | 2022-03-15 11:24:06 +0800 | [diff] [blame] | 52 | |
AngeloGioacchino Del Regno | 8e8a9e3 | 2022-04-07 13:44:28 +0200 | [diff] [blame] | 53 | #define SPI_CFG1_CS_IDLE_MASK 0xff |
| 54 | #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 |
| 55 | #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 |
| 56 | #define SPI_CFG1_IPM_PACKET_LENGTH_MASK GENMASK(31, 16) |
| 57 | #define SPI_CFG2_SCK_HIGH_OFFSET 0 |
| 58 | #define SPI_CFG2_SCK_LOW_OFFSET 16 |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 59 | |
AngeloGioacchino Del Regno | 8e8a9e3 | 2022-04-07 13:44:28 +0200 | [diff] [blame] | 60 | #define SPI_CMD_ACT BIT(0) |
| 61 | #define SPI_CMD_RESUME BIT(1) |
| 62 | #define SPI_CMD_RST BIT(2) |
| 63 | #define SPI_CMD_PAUSE_EN BIT(4) |
| 64 | #define SPI_CMD_DEASSERT BIT(5) |
| 65 | #define SPI_CMD_SAMPLE_SEL BIT(6) |
| 66 | #define SPI_CMD_CS_POL BIT(7) |
| 67 | #define SPI_CMD_CPHA BIT(8) |
| 68 | #define SPI_CMD_CPOL BIT(9) |
| 69 | #define SPI_CMD_RX_DMA BIT(10) |
| 70 | #define SPI_CMD_TX_DMA BIT(11) |
| 71 | #define SPI_CMD_TXMSBF BIT(12) |
| 72 | #define SPI_CMD_RXMSBF BIT(13) |
| 73 | #define SPI_CMD_RX_ENDIAN BIT(14) |
| 74 | #define SPI_CMD_TX_ENDIAN BIT(15) |
| 75 | #define SPI_CMD_FINISH_IE BIT(16) |
| 76 | #define SPI_CMD_PAUSE_IE BIT(17) |
| 77 | #define SPI_CMD_IPM_NONIDLE_MODE BIT(19) |
| 78 | #define SPI_CMD_IPM_SPIM_LOOP BIT(21) |
| 79 | #define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 80 | |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 81 | #define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) |
Leilk Liu | 9f763fd | 2022-03-21 09:39:20 +0800 | [diff] [blame] | 82 | |
| 83 | #define PIN_MODE_CFG(x) ((x) / 2) |
| 84 | |
AngeloGioacchino Del Regno | 8e8a9e3 | 2022-04-07 13:44:28 +0200 | [diff] [blame] | 85 | #define SPI_CFG3_IPM_HALF_DUPLEX_DIR BIT(2) |
| 86 | #define SPI_CFG3_IPM_HALF_DUPLEX_EN BIT(3) |
| 87 | #define SPI_CFG3_IPM_XMODE_EN BIT(4) |
| 88 | #define SPI_CFG3_IPM_NODATA_FLAG BIT(5) |
| 89 | #define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET 8 |
| 90 | #define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12 |
Leilk Liu | 9f763fd | 2022-03-21 09:39:20 +0800 | [diff] [blame] | 91 | |
AngeloGioacchino Del Regno | 8e8a9e3 | 2022-04-07 13:44:28 +0200 | [diff] [blame] | 92 | #define SPI_CFG3_IPM_CMD_PIN_MODE_MASK GENMASK(1, 0) |
| 93 | #define SPI_CFG3_IPM_CMD_BYTELEN_MASK GENMASK(11, 8) |
| 94 | #define SPI_CFG3_IPM_ADDR_BYTELEN_MASK GENMASK(15, 12) |
Leilk Liu | 9f763fd | 2022-03-21 09:39:20 +0800 | [diff] [blame] | 95 | |
AngeloGioacchino Del Regno | 8e8a9e3 | 2022-04-07 13:44:28 +0200 | [diff] [blame] | 96 | #define MT8173_SPI_MAX_PAD_SEL 3 |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 97 | |
AngeloGioacchino Del Regno | 8e8a9e3 | 2022-04-07 13:44:28 +0200 | [diff] [blame] | 98 | #define MTK_SPI_PAUSE_INT_STATUS 0x2 |
Leilk Liu | 50f8fec | 2015-08-24 11:45:16 +0800 | [diff] [blame] | 99 | |
AngeloGioacchino Del Regno | 8e8a9e3 | 2022-04-07 13:44:28 +0200 | [diff] [blame] | 100 | #define MTK_SPI_MAX_FIFO_SIZE 32U |
| 101 | #define MTK_SPI_PACKET_SIZE 1024 |
| 102 | #define MTK_SPI_IPM_PACKET_SIZE SZ_64K |
| 103 | #define MTK_SPI_IPM_PACKET_LOOP SZ_256 |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 104 | |
AngeloGioacchino Del Regno | 8e8a9e3 | 2022-04-07 13:44:28 +0200 | [diff] [blame] | 105 | #define MTK_SPI_IDLE 0 |
| 106 | #define MTK_SPI_PAUSED 1 |
Leilk Liu | 9f763fd | 2022-03-21 09:39:20 +0800 | [diff] [blame] | 107 | |
AngeloGioacchino Del Regno | 8e8a9e3 | 2022-04-07 13:44:28 +0200 | [diff] [blame] | 108 | #define MTK_SPI_32BITS_MASK (0xffffffff) |
luhua.xu | fdeae8f | 2019-09-11 05:55:31 -0400 | [diff] [blame] | 109 | |
AngeloGioacchino Del Regno | 8e8a9e3 | 2022-04-07 13:44:28 +0200 | [diff] [blame] | 110 | #define DMA_ADDR_EXT_BITS (36) |
| 111 | #define DMA_ADDR_DEF_BITS (32) |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 112 | |
AngeloGioacchino Del Regno | 3c5cd2e | 2022-04-07 13:44:27 +0200 | [diff] [blame] | 113 | /** |
| 114 | * struct mtk_spi_compatible - device data structure |
| 115 | * @need_pad_sel: Enable pad (pins) selection in SPI controller |
| 116 | * @must_tx: Must explicitly send dummy TX bytes to do RX only transfer |
| 117 | * @enhance_timing: Enable adjusting cfg register to enhance time accuracy |
| 118 | * @dma_ext: DMA address extension supported |
| 119 | * @no_need_unprepare: Don't unprepare the SPI clk during runtime |
| 120 | * @ipm_design: Adjust/extend registers to support IPM design IP features |
| 121 | */ |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 122 | struct mtk_spi_compatible { |
Leilk Liu | af57937 | 2015-08-20 17:19:07 +0800 | [diff] [blame] | 123 | bool need_pad_sel; |
Leilk Liu | af57937 | 2015-08-20 17:19:07 +0800 | [diff] [blame] | 124 | bool must_tx; |
Leilk Liu | 058fe49 | 2017-06-12 09:24:39 +0800 | [diff] [blame] | 125 | bool enhance_timing; |
luhua.xu | fdeae8f | 2019-09-11 05:55:31 -0400 | [diff] [blame] | 126 | bool dma_ext; |
Mason Zhang | 162a31e | 2021-06-29 18:08:15 +0800 | [diff] [blame] | 127 | bool no_need_unprepare; |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 128 | bool ipm_design; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 129 | }; |
| 130 | |
AngeloGioacchino Del Regno | 3c5cd2e | 2022-04-07 13:44:27 +0200 | [diff] [blame] | 131 | /** |
| 132 | * struct mtk_spi - SPI driver instance |
| 133 | * @base: Start address of the SPI controller registers |
| 134 | * @state: SPI controller state |
| 135 | * @pad_num: Number of pad_sel entries |
| 136 | * @pad_sel: Groups of pins to select |
| 137 | * @parent_clk: Parent of sel_clk |
| 138 | * @sel_clk: SPI master mux clock |
| 139 | * @spi_clk: Peripheral clock |
| 140 | * @spi_hclk: AHB bus clock |
| 141 | * @cur_transfer: Currently processed SPI transfer |
| 142 | * @xfer_len: Number of bytes to transfer |
| 143 | * @num_xfered: Number of transferred bytes |
| 144 | * @tx_sgl: TX transfer scatterlist |
| 145 | * @rx_sgl: RX transfer scatterlist |
| 146 | * @tx_sgl_len: Size of TX DMA transfer |
| 147 | * @rx_sgl_len: Size of RX DMA transfer |
| 148 | * @dev_comp: Device data structure |
| 149 | * @spi_clk_hz: Current SPI clock in Hz |
| 150 | * @spimem_done: SPI-MEM operation completion |
| 151 | * @use_spimem: Enables SPI-MEM |
| 152 | * @dev: Device pointer |
| 153 | * @tx_dma: DMA start for SPI-MEM TX |
| 154 | * @rx_dma: DMA start for SPI-MEM RX |
| 155 | */ |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 156 | struct mtk_spi { |
| 157 | void __iomem *base; |
| 158 | u32 state; |
Leilk Liu | 3745760 | 2015-10-26 16:09:44 +0800 | [diff] [blame] | 159 | int pad_num; |
| 160 | u32 *pad_sel; |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 161 | struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 162 | struct spi_transfer *cur_transfer; |
| 163 | u32 xfer_len; |
Peter Shih | 00bca73 | 2018-09-10 11:54:21 +0800 | [diff] [blame] | 164 | u32 num_xfered; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 165 | struct scatterlist *tx_sgl, *rx_sgl; |
| 166 | u32 tx_sgl_len, rx_sgl_len; |
| 167 | const struct mtk_spi_compatible *dev_comp; |
Mason Zhang | 162a31e | 2021-06-29 18:08:15 +0800 | [diff] [blame] | 168 | u32 spi_clk_hz; |
Leilk Liu | 9f763fd | 2022-03-21 09:39:20 +0800 | [diff] [blame] | 169 | struct completion spimem_done; |
| 170 | bool use_spimem; |
| 171 | struct device *dev; |
| 172 | dma_addr_t tx_dma; |
| 173 | dma_addr_t rx_dma; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 174 | }; |
| 175 | |
Leilk Liu | 4eaf6f7 | 2015-12-31 10:59:00 +0800 | [diff] [blame] | 176 | static const struct mtk_spi_compatible mtk_common_compat; |
Leilk Liu | fc4f226 | 2017-06-12 09:24:40 +0800 | [diff] [blame] | 177 | |
leilk.liu@mediatek.com | b6b1f2d | 2017-06-20 16:21:07 +0800 | [diff] [blame] | 178 | static const struct mtk_spi_compatible mt2712_compat = { |
| 179 | .must_tx = true, |
| 180 | }; |
| 181 | |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 182 | static const struct mtk_spi_compatible mtk_ipm_compat = { |
| 183 | .enhance_timing = true, |
| 184 | .dma_ext = true, |
| 185 | .ipm_design = true, |
| 186 | }; |
| 187 | |
luhua.xu | 2c231e0 | 2019-09-11 05:55:30 -0400 | [diff] [blame] | 188 | static const struct mtk_spi_compatible mt6765_compat = { |
| 189 | .need_pad_sel = true, |
| 190 | .must_tx = true, |
| 191 | .enhance_timing = true, |
luhua.xu | fdeae8f | 2019-09-11 05:55:31 -0400 | [diff] [blame] | 192 | .dma_ext = true, |
luhua.xu | 2c231e0 | 2019-09-11 05:55:30 -0400 | [diff] [blame] | 193 | }; |
| 194 | |
Leilk Liu | fc4f226 | 2017-06-12 09:24:40 +0800 | [diff] [blame] | 195 | static const struct mtk_spi_compatible mt7622_compat = { |
| 196 | .must_tx = true, |
| 197 | .enhance_timing = true, |
| 198 | }; |
| 199 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 200 | static const struct mtk_spi_compatible mt8173_compat = { |
Leilk Liu | af57937 | 2015-08-20 17:19:07 +0800 | [diff] [blame] | 201 | .need_pad_sel = true, |
| 202 | .must_tx = true, |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 203 | }; |
| 204 | |
Leilk Liu | b654aa6 | 2018-11-01 14:02:19 +0800 | [diff] [blame] | 205 | static const struct mtk_spi_compatible mt8183_compat = { |
| 206 | .need_pad_sel = true, |
| 207 | .must_tx = true, |
| 208 | .enhance_timing = true, |
| 209 | }; |
| 210 | |
Mason Zhang | 162a31e | 2021-06-29 18:08:15 +0800 | [diff] [blame] | 211 | static const struct mtk_spi_compatible mt6893_compat = { |
| 212 | .need_pad_sel = true, |
| 213 | .must_tx = true, |
| 214 | .enhance_timing = true, |
| 215 | .dma_ext = true, |
| 216 | .no_need_unprepare = true, |
| 217 | }; |
| 218 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 219 | /* |
| 220 | * A piece of default chip info unless the platform |
| 221 | * supplies it. |
| 222 | */ |
| 223 | static const struct mtk_chip_config mtk_default_chip_info = { |
Leilk Liu | 058fe49 | 2017-06-12 09:24:39 +0800 | [diff] [blame] | 224 | .sample_sel = 0, |
Mason Zhang | f84d866 | 2021-07-13 19:40:49 +0800 | [diff] [blame] | 225 | .tick_delay = 0, |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 226 | }; |
| 227 | |
| 228 | static const struct of_device_id mtk_spi_of_match[] = { |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 229 | { .compatible = "mediatek,spi-ipm", |
| 230 | .data = (void *)&mtk_ipm_compat, |
| 231 | }, |
Leilk Liu | 15bcdefd | 2015-12-31 10:59:01 +0800 | [diff] [blame] | 232 | { .compatible = "mediatek,mt2701-spi", |
| 233 | .data = (void *)&mtk_common_compat, |
| 234 | }, |
leilk.liu@mediatek.com | b6b1f2d | 2017-06-20 16:21:07 +0800 | [diff] [blame] | 235 | { .compatible = "mediatek,mt2712-spi", |
| 236 | .data = (void *)&mt2712_compat, |
| 237 | }, |
Leilk Liu | 4eaf6f7 | 2015-12-31 10:59:00 +0800 | [diff] [blame] | 238 | { .compatible = "mediatek,mt6589-spi", |
| 239 | .data = (void *)&mtk_common_compat, |
| 240 | }, |
luhua.xu | 2c231e0 | 2019-09-11 05:55:30 -0400 | [diff] [blame] | 241 | { .compatible = "mediatek,mt6765-spi", |
| 242 | .data = (void *)&mt6765_compat, |
| 243 | }, |
Leilk Liu | fc4f226 | 2017-06-12 09:24:40 +0800 | [diff] [blame] | 244 | { .compatible = "mediatek,mt7622-spi", |
| 245 | .data = (void *)&mt7622_compat, |
| 246 | }, |
Leilk Liu | 942779c | 2018-11-20 16:41:08 +0800 | [diff] [blame] | 247 | { .compatible = "mediatek,mt7629-spi", |
| 248 | .data = (void *)&mt7622_compat, |
| 249 | }, |
Leilk Liu | 4eaf6f7 | 2015-12-31 10:59:00 +0800 | [diff] [blame] | 250 | { .compatible = "mediatek,mt8135-spi", |
| 251 | .data = (void *)&mtk_common_compat, |
| 252 | }, |
| 253 | { .compatible = "mediatek,mt8173-spi", |
| 254 | .data = (void *)&mt8173_compat, |
| 255 | }, |
Leilk Liu | b654aa6 | 2018-11-01 14:02:19 +0800 | [diff] [blame] | 256 | { .compatible = "mediatek,mt8183-spi", |
| 257 | .data = (void *)&mt8183_compat, |
| 258 | }, |
leilk.liu | 8cf125c | 2020-07-21 20:24:36 +0800 | [diff] [blame] | 259 | { .compatible = "mediatek,mt8192-spi", |
| 260 | .data = (void *)&mt6765_compat, |
| 261 | }, |
Mason Zhang | 162a31e | 2021-06-29 18:08:15 +0800 | [diff] [blame] | 262 | { .compatible = "mediatek,mt6893-spi", |
| 263 | .data = (void *)&mt6893_compat, |
| 264 | }, |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 265 | {} |
| 266 | }; |
| 267 | MODULE_DEVICE_TABLE(of, mtk_spi_of_match); |
| 268 | |
| 269 | static void mtk_spi_reset(struct mtk_spi *mdata) |
| 270 | { |
| 271 | u32 reg_val; |
| 272 | |
| 273 | /* set the software reset bit in SPI_CMD_REG. */ |
| 274 | reg_val = readl(mdata->base + SPI_CMD_REG); |
| 275 | reg_val |= SPI_CMD_RST; |
| 276 | writel(reg_val, mdata->base + SPI_CMD_REG); |
| 277 | |
| 278 | reg_val = readl(mdata->base + SPI_CMD_REG); |
| 279 | reg_val &= ~SPI_CMD_RST; |
| 280 | writel(reg_val, mdata->base + SPI_CMD_REG); |
| 281 | } |
| 282 | |
Mason Zhang | 04e6bb0 | 2021-08-04 21:37:47 +0800 | [diff] [blame] | 283 | static int mtk_spi_set_hw_cs_timing(struct spi_device *spi) |
| 284 | { |
| 285 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); |
| 286 | struct spi_delay *cs_setup = &spi->cs_setup; |
| 287 | struct spi_delay *cs_hold = &spi->cs_hold; |
| 288 | struct spi_delay *cs_inactive = &spi->cs_inactive; |
Mason Zhang | 5c842e5 | 2021-08-09 13:59:12 +0800 | [diff] [blame] | 289 | u32 setup, hold, inactive; |
Mason Zhang | 04e6bb0 | 2021-08-04 21:37:47 +0800 | [diff] [blame] | 290 | u32 reg_val; |
| 291 | int delay; |
| 292 | |
| 293 | delay = spi_delay_to_ns(cs_setup, NULL); |
| 294 | if (delay < 0) |
| 295 | return delay; |
| 296 | setup = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; |
| 297 | |
| 298 | delay = spi_delay_to_ns(cs_hold, NULL); |
| 299 | if (delay < 0) |
| 300 | return delay; |
| 301 | hold = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; |
| 302 | |
| 303 | delay = spi_delay_to_ns(cs_inactive, NULL); |
| 304 | if (delay < 0) |
| 305 | return delay; |
| 306 | inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; |
| 307 | |
Dafna Hirschfeld | 3672bb82 | 2021-10-01 17:21:53 +0200 | [diff] [blame] | 308 | if (hold || setup) { |
| 309 | reg_val = readl(mdata->base + SPI_CFG0_REG); |
| 310 | if (mdata->dev_comp->enhance_timing) { |
| 311 | if (hold) { |
| 312 | hold = min_t(u32, hold, 0x10000); |
| 313 | reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); |
| 314 | reg_val |= (((hold - 1) & 0xffff) |
| 315 | << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); |
| 316 | } |
| 317 | if (setup) { |
| 318 | setup = min_t(u32, setup, 0x10000); |
| 319 | reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); |
| 320 | reg_val |= (((setup - 1) & 0xffff) |
| 321 | << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); |
| 322 | } |
| 323 | } else { |
| 324 | if (hold) { |
| 325 | hold = min_t(u32, hold, 0x100); |
| 326 | reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET); |
| 327 | reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); |
| 328 | } |
| 329 | if (setup) { |
| 330 | setup = min_t(u32, setup, 0x100); |
| 331 | reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET); |
| 332 | reg_val |= (((setup - 1) & 0xff) |
| 333 | << SPI_CFG0_CS_SETUP_OFFSET); |
| 334 | } |
| 335 | } |
| 336 | writel(reg_val, mdata->base + SPI_CFG0_REG); |
Mason Zhang | 04e6bb0 | 2021-08-04 21:37:47 +0800 | [diff] [blame] | 337 | } |
Mason Zhang | 04e6bb0 | 2021-08-04 21:37:47 +0800 | [diff] [blame] | 338 | |
Dafna Hirschfeld | 3672bb82 | 2021-10-01 17:21:53 +0200 | [diff] [blame] | 339 | if (inactive) { |
| 340 | inactive = min_t(u32, inactive, 0x100); |
| 341 | reg_val = readl(mdata->base + SPI_CFG1_REG); |
| 342 | reg_val &= ~SPI_CFG1_CS_IDLE_MASK; |
| 343 | reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); |
| 344 | writel(reg_val, mdata->base + SPI_CFG1_REG); |
| 345 | } |
Mason Zhang | 04e6bb0 | 2021-08-04 21:37:47 +0800 | [diff] [blame] | 346 | |
| 347 | return 0; |
| 348 | } |
| 349 | |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 350 | static int mtk_spi_hw_init(struct spi_master *master, |
| 351 | struct spi_device *spi) |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 352 | { |
Leilk Liu | 79b5d3f | 2015-10-26 16:09:41 +0800 | [diff] [blame] | 353 | u16 cpha, cpol; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 354 | u32 reg_val; |
Leilk Liu | 58a984c7 | 2015-10-26 16:09:43 +0800 | [diff] [blame] | 355 | struct mtk_chip_config *chip_config = spi->controller_data; |
Leilk Liu | 79b5d3f | 2015-10-26 16:09:41 +0800 | [diff] [blame] | 356 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
| 357 | |
| 358 | cpha = spi->mode & SPI_CPHA ? 1 : 0; |
| 359 | cpol = spi->mode & SPI_CPOL ? 1 : 0; |
| 360 | |
Leilk Liu | 79b5d3f | 2015-10-26 16:09:41 +0800 | [diff] [blame] | 361 | reg_val = readl(mdata->base + SPI_CMD_REG); |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 362 | if (mdata->dev_comp->ipm_design) { |
| 363 | /* SPI transfer without idle time until packet length done */ |
| 364 | reg_val |= SPI_CMD_IPM_NONIDLE_MODE; |
| 365 | if (spi->mode & SPI_LOOP) |
| 366 | reg_val |= SPI_CMD_IPM_SPIM_LOOP; |
| 367 | else |
| 368 | reg_val &= ~SPI_CMD_IPM_SPIM_LOOP; |
| 369 | } |
| 370 | |
Leilk Liu | 79b5d3f | 2015-10-26 16:09:41 +0800 | [diff] [blame] | 371 | if (cpha) |
| 372 | reg_val |= SPI_CMD_CPHA; |
| 373 | else |
| 374 | reg_val &= ~SPI_CMD_CPHA; |
| 375 | if (cpol) |
| 376 | reg_val |= SPI_CMD_CPOL; |
| 377 | else |
| 378 | reg_val &= ~SPI_CMD_CPOL; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 379 | |
| 380 | /* set the mlsbx and mlsbtx */ |
Leilk Liu | 3e582c6 | 2019-06-05 11:07:04 +0800 | [diff] [blame] | 381 | if (spi->mode & SPI_LSB_FIRST) { |
Leilk Liu | a71d6ea | 2015-08-20 17:19:08 +0800 | [diff] [blame] | 382 | reg_val &= ~SPI_CMD_TXMSBF; |
Leilk Liu | a71d6ea | 2015-08-20 17:19:08 +0800 | [diff] [blame] | 383 | reg_val &= ~SPI_CMD_RXMSBF; |
Leilk Liu | 3e582c6 | 2019-06-05 11:07:04 +0800 | [diff] [blame] | 384 | } else { |
| 385 | reg_val |= SPI_CMD_TXMSBF; |
| 386 | reg_val |= SPI_CMD_RXMSBF; |
| 387 | } |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 388 | |
| 389 | /* set the tx/rx endian */ |
Leilk Liu | 44f636d | 2015-08-20 17:19:06 +0800 | [diff] [blame] | 390 | #ifdef __LITTLE_ENDIAN |
| 391 | reg_val &= ~SPI_CMD_TX_ENDIAN; |
| 392 | reg_val &= ~SPI_CMD_RX_ENDIAN; |
| 393 | #else |
| 394 | reg_val |= SPI_CMD_TX_ENDIAN; |
| 395 | reg_val |= SPI_CMD_RX_ENDIAN; |
| 396 | #endif |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 397 | |
Leilk Liu | 058fe49 | 2017-06-12 09:24:39 +0800 | [diff] [blame] | 398 | if (mdata->dev_comp->enhance_timing) { |
Luhua Xu | ae7c2d3 | 2019-11-18 12:57:16 +0800 | [diff] [blame] | 399 | /* set CS polarity */ |
| 400 | if (spi->mode & SPI_CS_HIGH) |
Leilk Liu | 058fe49 | 2017-06-12 09:24:39 +0800 | [diff] [blame] | 401 | reg_val |= SPI_CMD_CS_POL; |
| 402 | else |
| 403 | reg_val &= ~SPI_CMD_CS_POL; |
Luhua Xu | ae7c2d3 | 2019-11-18 12:57:16 +0800 | [diff] [blame] | 404 | |
Leilk Liu | 058fe49 | 2017-06-12 09:24:39 +0800 | [diff] [blame] | 405 | if (chip_config->sample_sel) |
| 406 | reg_val |= SPI_CMD_SAMPLE_SEL; |
| 407 | else |
| 408 | reg_val &= ~SPI_CMD_SAMPLE_SEL; |
| 409 | } |
| 410 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 411 | /* set finish and pause interrupt always enable */ |
Leilk Liu | 1529332 | 2015-08-27 21:09:04 +0800 | [diff] [blame] | 412 | reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 413 | |
| 414 | /* disable dma mode */ |
| 415 | reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); |
| 416 | |
| 417 | /* disable deassert mode */ |
| 418 | reg_val &= ~SPI_CMD_DEASSERT; |
| 419 | |
| 420 | writel(reg_val, mdata->base + SPI_CMD_REG); |
| 421 | |
| 422 | /* pad select */ |
| 423 | if (mdata->dev_comp->need_pad_sel) |
Leilk Liu | 3745760 | 2015-10-26 16:09:44 +0800 | [diff] [blame] | 424 | writel(mdata->pad_sel[spi->chip_select], |
| 425 | mdata->base + SPI_PAD_SEL_REG); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 426 | |
Mason Zhang | f84d866 | 2021-07-13 19:40:49 +0800 | [diff] [blame] | 427 | /* tick delay */ |
Leilk Liu | 03b1be3 | 2022-03-15 11:24:06 +0800 | [diff] [blame] | 428 | if (mdata->dev_comp->enhance_timing) { |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 429 | if (mdata->dev_comp->ipm_design) { |
| 430 | reg_val = readl(mdata->base + SPI_CMD_REG); |
| 431 | reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; |
| 432 | reg_val |= ((chip_config->tick_delay & 0x7) |
| 433 | << SPI_CMD_IPM_GET_TICKDLY_OFFSET); |
| 434 | writel(reg_val, mdata->base + SPI_CMD_REG); |
| 435 | } else { |
| 436 | reg_val = readl(mdata->base + SPI_CFG1_REG); |
| 437 | reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; |
| 438 | reg_val |= ((chip_config->tick_delay & 0x7) |
| 439 | << SPI_CFG1_GET_TICK_DLY_OFFSET); |
| 440 | writel(reg_val, mdata->base + SPI_CFG1_REG); |
| 441 | } |
Leilk Liu | 03b1be3 | 2022-03-15 11:24:06 +0800 | [diff] [blame] | 442 | } else { |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 443 | reg_val = readl(mdata->base + SPI_CFG1_REG); |
Leilk Liu | 03b1be3 | 2022-03-15 11:24:06 +0800 | [diff] [blame] | 444 | reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; |
| 445 | reg_val |= ((chip_config->tick_delay & 0x3) |
| 446 | << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 447 | writel(reg_val, mdata->base + SPI_CFG1_REG); |
Leilk Liu | 03b1be3 | 2022-03-15 11:24:06 +0800 | [diff] [blame] | 448 | } |
Mason Zhang | f84d866 | 2021-07-13 19:40:49 +0800 | [diff] [blame] | 449 | |
Mason Zhang | 04e6bb0 | 2021-08-04 21:37:47 +0800 | [diff] [blame] | 450 | /* set hw cs timing */ |
| 451 | mtk_spi_set_hw_cs_timing(spi); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 452 | return 0; |
| 453 | } |
| 454 | |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 455 | static int mtk_spi_prepare_message(struct spi_master *master, |
| 456 | struct spi_message *msg) |
| 457 | { |
| 458 | return mtk_spi_hw_init(master, msg->spi); |
| 459 | } |
| 460 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 461 | static void mtk_spi_set_cs(struct spi_device *spi, bool enable) |
| 462 | { |
| 463 | u32 reg_val; |
| 464 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); |
| 465 | |
Luhua Xu | ae7c2d3 | 2019-11-18 12:57:16 +0800 | [diff] [blame] | 466 | if (spi->mode & SPI_CS_HIGH) |
| 467 | enable = !enable; |
| 468 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 469 | reg_val = readl(mdata->base + SPI_CMD_REG); |
Leilk Liu | 6583d20 | 2015-09-07 19:37:57 +0800 | [diff] [blame] | 470 | if (!enable) { |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 471 | reg_val |= SPI_CMD_PAUSE_EN; |
Leilk Liu | 6583d20 | 2015-09-07 19:37:57 +0800 | [diff] [blame] | 472 | writel(reg_val, mdata->base + SPI_CMD_REG); |
| 473 | } else { |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 474 | reg_val &= ~SPI_CMD_PAUSE_EN; |
Leilk Liu | 6583d20 | 2015-09-07 19:37:57 +0800 | [diff] [blame] | 475 | writel(reg_val, mdata->base + SPI_CMD_REG); |
| 476 | mdata->state = MTK_SPI_IDLE; |
| 477 | mtk_spi_reset(mdata); |
| 478 | } |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 479 | } |
| 480 | |
| 481 | static void mtk_spi_prepare_transfer(struct spi_master *master, |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 482 | u32 speed_hz) |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 483 | { |
Mason Zhang | 162a31e | 2021-06-29 18:08:15 +0800 | [diff] [blame] | 484 | u32 div, sck_time, reg_val; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 485 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
| 486 | |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 487 | if (speed_hz < mdata->spi_clk_hz / 2) |
| 488 | div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 489 | else |
| 490 | div = 1; |
| 491 | |
Leilk Liu | 2ce0acf | 2015-08-24 11:45:18 +0800 | [diff] [blame] | 492 | sck_time = (div + 1) / 2; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 493 | |
Leilk Liu | 058fe49 | 2017-06-12 09:24:39 +0800 | [diff] [blame] | 494 | if (mdata->dev_comp->enhance_timing) { |
leilk.liu | 9f6e7e8 | 2021-02-07 11:09:53 +0800 | [diff] [blame] | 495 | reg_val = readl(mdata->base + SPI_CFG2_REG); |
| 496 | reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET); |
| 497 | reg_val |= (((sck_time - 1) & 0xffff) |
leilk.liu | 44b37eb | 2020-07-01 17:00:20 +0800 | [diff] [blame] | 498 | << SPI_CFG2_SCK_HIGH_OFFSET); |
leilk.liu | 9f6e7e8 | 2021-02-07 11:09:53 +0800 | [diff] [blame] | 499 | reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET); |
Leilk Liu | 058fe49 | 2017-06-12 09:24:39 +0800 | [diff] [blame] | 500 | reg_val |= (((sck_time - 1) & 0xffff) |
leilk.liu | 44b37eb | 2020-07-01 17:00:20 +0800 | [diff] [blame] | 501 | << SPI_CFG2_SCK_LOW_OFFSET); |
Leilk Liu | 058fe49 | 2017-06-12 09:24:39 +0800 | [diff] [blame] | 502 | writel(reg_val, mdata->base + SPI_CFG2_REG); |
Leilk Liu | 058fe49 | 2017-06-12 09:24:39 +0800 | [diff] [blame] | 503 | } else { |
leilk.liu | 9f6e7e8 | 2021-02-07 11:09:53 +0800 | [diff] [blame] | 504 | reg_val = readl(mdata->base + SPI_CFG0_REG); |
| 505 | reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET); |
| 506 | reg_val |= (((sck_time - 1) & 0xff) |
Leilk Liu | 058fe49 | 2017-06-12 09:24:39 +0800 | [diff] [blame] | 507 | << SPI_CFG0_SCK_HIGH_OFFSET); |
leilk.liu | 9f6e7e8 | 2021-02-07 11:09:53 +0800 | [diff] [blame] | 508 | reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET); |
Leilk Liu | 058fe49 | 2017-06-12 09:24:39 +0800 | [diff] [blame] | 509 | reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); |
Leilk Liu | 058fe49 | 2017-06-12 09:24:39 +0800 | [diff] [blame] | 510 | writel(reg_val, mdata->base + SPI_CFG0_REG); |
| 511 | } |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 512 | } |
| 513 | |
| 514 | static void mtk_spi_setup_packet(struct spi_master *master) |
| 515 | { |
| 516 | u32 packet_size, packet_loop, reg_val; |
| 517 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
| 518 | |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 519 | if (mdata->dev_comp->ipm_design) |
| 520 | packet_size = min_t(u32, |
| 521 | mdata->xfer_len, |
| 522 | MTK_SPI_IPM_PACKET_SIZE); |
| 523 | else |
| 524 | packet_size = min_t(u32, |
| 525 | mdata->xfer_len, |
| 526 | MTK_SPI_PACKET_SIZE); |
| 527 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 528 | packet_loop = mdata->xfer_len / packet_size; |
| 529 | |
| 530 | reg_val = readl(mdata->base + SPI_CFG1_REG); |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 531 | if (mdata->dev_comp->ipm_design) |
| 532 | reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK; |
| 533 | else |
| 534 | reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 535 | reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 536 | reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 537 | reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; |
| 538 | writel(reg_val, mdata->base + SPI_CFG1_REG); |
| 539 | } |
| 540 | |
| 541 | static void mtk_spi_enable_transfer(struct spi_master *master) |
| 542 | { |
Leilk Liu | 50f8fec | 2015-08-24 11:45:16 +0800 | [diff] [blame] | 543 | u32 cmd; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 544 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
| 545 | |
| 546 | cmd = readl(mdata->base + SPI_CMD_REG); |
| 547 | if (mdata->state == MTK_SPI_IDLE) |
Leilk Liu | a71d6ea | 2015-08-20 17:19:08 +0800 | [diff] [blame] | 548 | cmd |= SPI_CMD_ACT; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 549 | else |
Leilk Liu | a71d6ea | 2015-08-20 17:19:08 +0800 | [diff] [blame] | 550 | cmd |= SPI_CMD_RESUME; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 551 | writel(cmd, mdata->base + SPI_CMD_REG); |
| 552 | } |
| 553 | |
zhichao.liu | cf82d0e | 2022-10-21 17:16:53 +0800 | [diff] [blame] | 554 | static int mtk_spi_get_mult_delta(struct mtk_spi *mdata, u32 xfer_len) |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 555 | { |
zhichao.liu | cf82d0e | 2022-10-21 17:16:53 +0800 | [diff] [blame] | 556 | u32 mult_delta = 0; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 557 | |
zhichao.liu | cf82d0e | 2022-10-21 17:16:53 +0800 | [diff] [blame] | 558 | if (mdata->dev_comp->ipm_design) { |
| 559 | if (xfer_len > MTK_SPI_IPM_PACKET_SIZE) |
| 560 | mult_delta = xfer_len % MTK_SPI_IPM_PACKET_SIZE; |
| 561 | } else { |
| 562 | if (xfer_len > MTK_SPI_PACKET_SIZE) |
| 563 | mult_delta = xfer_len % MTK_SPI_PACKET_SIZE; |
| 564 | } |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 565 | |
| 566 | return mult_delta; |
| 567 | } |
| 568 | |
| 569 | static void mtk_spi_update_mdata_len(struct spi_master *master) |
| 570 | { |
| 571 | int mult_delta; |
| 572 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
| 573 | |
| 574 | if (mdata->tx_sgl_len && mdata->rx_sgl_len) { |
| 575 | if (mdata->tx_sgl_len > mdata->rx_sgl_len) { |
zhichao.liu | cf82d0e | 2022-10-21 17:16:53 +0800 | [diff] [blame] | 576 | mult_delta = mtk_spi_get_mult_delta(mdata, mdata->rx_sgl_len); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 577 | mdata->xfer_len = mdata->rx_sgl_len - mult_delta; |
| 578 | mdata->rx_sgl_len = mult_delta; |
| 579 | mdata->tx_sgl_len -= mdata->xfer_len; |
| 580 | } else { |
zhichao.liu | cf82d0e | 2022-10-21 17:16:53 +0800 | [diff] [blame] | 581 | mult_delta = mtk_spi_get_mult_delta(mdata, mdata->tx_sgl_len); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 582 | mdata->xfer_len = mdata->tx_sgl_len - mult_delta; |
| 583 | mdata->tx_sgl_len = mult_delta; |
| 584 | mdata->rx_sgl_len -= mdata->xfer_len; |
| 585 | } |
| 586 | } else if (mdata->tx_sgl_len) { |
zhichao.liu | cf82d0e | 2022-10-21 17:16:53 +0800 | [diff] [blame] | 587 | mult_delta = mtk_spi_get_mult_delta(mdata, mdata->tx_sgl_len); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 588 | mdata->xfer_len = mdata->tx_sgl_len - mult_delta; |
| 589 | mdata->tx_sgl_len = mult_delta; |
| 590 | } else if (mdata->rx_sgl_len) { |
zhichao.liu | cf82d0e | 2022-10-21 17:16:53 +0800 | [diff] [blame] | 591 | mult_delta = mtk_spi_get_mult_delta(mdata, mdata->rx_sgl_len); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 592 | mdata->xfer_len = mdata->rx_sgl_len - mult_delta; |
| 593 | mdata->rx_sgl_len = mult_delta; |
| 594 | } |
| 595 | } |
| 596 | |
| 597 | static void mtk_spi_setup_dma_addr(struct spi_master *master, |
| 598 | struct spi_transfer *xfer) |
| 599 | { |
| 600 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
| 601 | |
luhua.xu | fdeae8f | 2019-09-11 05:55:31 -0400 | [diff] [blame] | 602 | if (mdata->tx_sgl) { |
| 603 | writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK), |
| 604 | mdata->base + SPI_TX_SRC_REG); |
| 605 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
| 606 | if (mdata->dev_comp->dma_ext) |
| 607 | writel((u32)(xfer->tx_dma >> 32), |
| 608 | mdata->base + SPI_TX_SRC_REG_64); |
| 609 | #endif |
| 610 | } |
| 611 | |
| 612 | if (mdata->rx_sgl) { |
| 613 | writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK), |
| 614 | mdata->base + SPI_RX_DST_REG); |
| 615 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
| 616 | if (mdata->dev_comp->dma_ext) |
| 617 | writel((u32)(xfer->rx_dma >> 32), |
| 618 | mdata->base + SPI_RX_DST_REG_64); |
| 619 | #endif |
| 620 | } |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 621 | } |
| 622 | |
| 623 | static int mtk_spi_fifo_transfer(struct spi_master *master, |
| 624 | struct spi_device *spi, |
| 625 | struct spi_transfer *xfer) |
| 626 | { |
Nicolas Boichat | de327e4 | 2015-12-27 18:17:06 +0800 | [diff] [blame] | 627 | int cnt, remainder; |
| 628 | u32 reg_val; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 629 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
| 630 | |
| 631 | mdata->cur_transfer = xfer; |
Daniel Kurtz | 1ce2486 | 2017-01-27 00:21:54 +0800 | [diff] [blame] | 632 | mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); |
Peter Shih | 00bca73 | 2018-09-10 11:54:21 +0800 | [diff] [blame] | 633 | mdata->num_xfered = 0; |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 634 | mtk_spi_prepare_transfer(master, xfer->speed_hz); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 635 | mtk_spi_setup_packet(master); |
| 636 | |
Guenter Roeck | 0d5c395 | 2021-08-01 20:00:23 -0700 | [diff] [blame] | 637 | if (xfer->tx_buf) { |
| 638 | cnt = xfer->len / 4; |
Peter Hess | 3a70dd2 | 2021-07-06 14:16:09 +0200 | [diff] [blame] | 639 | iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); |
Guenter Roeck | 0d5c395 | 2021-08-01 20:00:23 -0700 | [diff] [blame] | 640 | remainder = xfer->len % 4; |
| 641 | if (remainder > 0) { |
| 642 | reg_val = 0; |
Peter Hess | 3a70dd2 | 2021-07-06 14:16:09 +0200 | [diff] [blame] | 643 | memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); |
| 644 | writel(reg_val, mdata->base + SPI_TX_DATA_REG); |
| 645 | } |
Nicolas Boichat | de327e4 | 2015-12-27 18:17:06 +0800 | [diff] [blame] | 646 | } |
| 647 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 648 | mtk_spi_enable_transfer(master); |
| 649 | |
| 650 | return 1; |
| 651 | } |
| 652 | |
| 653 | static int mtk_spi_dma_transfer(struct spi_master *master, |
| 654 | struct spi_device *spi, |
| 655 | struct spi_transfer *xfer) |
| 656 | { |
| 657 | int cmd; |
| 658 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
| 659 | |
| 660 | mdata->tx_sgl = NULL; |
| 661 | mdata->rx_sgl = NULL; |
| 662 | mdata->tx_sgl_len = 0; |
| 663 | mdata->rx_sgl_len = 0; |
| 664 | mdata->cur_transfer = xfer; |
Peter Shih | 00bca73 | 2018-09-10 11:54:21 +0800 | [diff] [blame] | 665 | mdata->num_xfered = 0; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 666 | |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 667 | mtk_spi_prepare_transfer(master, xfer->speed_hz); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 668 | |
| 669 | cmd = readl(mdata->base + SPI_CMD_REG); |
| 670 | if (xfer->tx_buf) |
| 671 | cmd |= SPI_CMD_TX_DMA; |
| 672 | if (xfer->rx_buf) |
| 673 | cmd |= SPI_CMD_RX_DMA; |
| 674 | writel(cmd, mdata->base + SPI_CMD_REG); |
| 675 | |
| 676 | if (xfer->tx_buf) |
| 677 | mdata->tx_sgl = xfer->tx_sg.sgl; |
| 678 | if (xfer->rx_buf) |
| 679 | mdata->rx_sgl = xfer->rx_sg.sgl; |
| 680 | |
| 681 | if (mdata->tx_sgl) { |
| 682 | xfer->tx_dma = sg_dma_address(mdata->tx_sgl); |
| 683 | mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); |
| 684 | } |
| 685 | if (mdata->rx_sgl) { |
| 686 | xfer->rx_dma = sg_dma_address(mdata->rx_sgl); |
| 687 | mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); |
| 688 | } |
| 689 | |
| 690 | mtk_spi_update_mdata_len(master); |
| 691 | mtk_spi_setup_packet(master); |
| 692 | mtk_spi_setup_dma_addr(master, xfer); |
| 693 | mtk_spi_enable_transfer(master); |
| 694 | |
| 695 | return 1; |
| 696 | } |
| 697 | |
| 698 | static int mtk_spi_transfer_one(struct spi_master *master, |
| 699 | struct spi_device *spi, |
| 700 | struct spi_transfer *xfer) |
| 701 | { |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 702 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); |
| 703 | u32 reg_val = 0; |
| 704 | |
| 705 | /* prepare xfer direction and duplex mode */ |
| 706 | if (mdata->dev_comp->ipm_design) { |
| 707 | if (!xfer->tx_buf || !xfer->rx_buf) { |
| 708 | reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; |
| 709 | if (xfer->rx_buf) |
| 710 | reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; |
| 711 | } |
| 712 | writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); |
| 713 | } |
| 714 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 715 | if (master->can_dma(master, spi, xfer)) |
| 716 | return mtk_spi_dma_transfer(master, spi, xfer); |
| 717 | else |
| 718 | return mtk_spi_fifo_transfer(master, spi, xfer); |
| 719 | } |
| 720 | |
| 721 | static bool mtk_spi_can_dma(struct spi_master *master, |
| 722 | struct spi_device *spi, |
| 723 | struct spi_transfer *xfer) |
| 724 | { |
Daniel Kurtz | 1ce2486 | 2017-01-27 00:21:54 +0800 | [diff] [blame] | 725 | /* Buffers for DMA transactions must be 4-byte aligned */ |
| 726 | return (xfer->len > MTK_SPI_MAX_FIFO_SIZE && |
| 727 | (unsigned long)xfer->tx_buf % 4 == 0 && |
| 728 | (unsigned long)xfer->rx_buf % 4 == 0); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 729 | } |
| 730 | |
Leilk Liu | 58a984c7 | 2015-10-26 16:09:43 +0800 | [diff] [blame] | 731 | static int mtk_spi_setup(struct spi_device *spi) |
| 732 | { |
| 733 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); |
| 734 | |
| 735 | if (!spi->controller_data) |
| 736 | spi->controller_data = (void *)&mtk_default_chip_info; |
| 737 | |
Linus Walleij | 1a5a87d | 2022-01-22 01:33:02 +0100 | [diff] [blame] | 738 | if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) |
| 739 | /* CS de-asserted, gpiolib will handle inversion */ |
| 740 | gpiod_direction_output(spi->cs_gpiod, 0); |
Leilk Liu | 3745760 | 2015-10-26 16:09:44 +0800 | [diff] [blame] | 741 | |
Leilk Liu | 58a984c7 | 2015-10-26 16:09:43 +0800 | [diff] [blame] | 742 | return 0; |
| 743 | } |
| 744 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 745 | static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) |
| 746 | { |
Peter Shih | 00bca73 | 2018-09-10 11:54:21 +0800 | [diff] [blame] | 747 | u32 cmd, reg_val, cnt, remainder, len; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 748 | struct spi_master *master = dev_id; |
| 749 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
| 750 | struct spi_transfer *trans = mdata->cur_transfer; |
| 751 | |
| 752 | reg_val = readl(mdata->base + SPI_STATUS0_REG); |
Leilk Liu | 50f8fec | 2015-08-24 11:45:16 +0800 | [diff] [blame] | 753 | if (reg_val & MTK_SPI_PAUSE_INT_STATUS) |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 754 | mdata->state = MTK_SPI_PAUSED; |
| 755 | else |
| 756 | mdata->state = MTK_SPI_IDLE; |
| 757 | |
Leilk Liu | 9f763fd | 2022-03-21 09:39:20 +0800 | [diff] [blame] | 758 | /* SPI-MEM ops */ |
| 759 | if (mdata->use_spimem) { |
| 760 | complete(&mdata->spimem_done); |
| 761 | return IRQ_HANDLED; |
| 762 | } |
| 763 | |
Benjamin Gaignard | f83a96e | 2022-01-31 15:17:08 +0100 | [diff] [blame] | 764 | if (!master->can_dma(master, NULL, trans)) { |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 765 | if (trans->rx_buf) { |
Nicolas Boichat | de327e4 | 2015-12-27 18:17:06 +0800 | [diff] [blame] | 766 | cnt = mdata->xfer_len / 4; |
Leilk Liu | 44f636d | 2015-08-20 17:19:06 +0800 | [diff] [blame] | 767 | ioread32_rep(mdata->base + SPI_RX_DATA_REG, |
Peter Shih | 00bca73 | 2018-09-10 11:54:21 +0800 | [diff] [blame] | 768 | trans->rx_buf + mdata->num_xfered, cnt); |
Nicolas Boichat | de327e4 | 2015-12-27 18:17:06 +0800 | [diff] [blame] | 769 | remainder = mdata->xfer_len % 4; |
| 770 | if (remainder > 0) { |
| 771 | reg_val = readl(mdata->base + SPI_RX_DATA_REG); |
Peter Shih | 00bca73 | 2018-09-10 11:54:21 +0800 | [diff] [blame] | 772 | memcpy(trans->rx_buf + |
| 773 | mdata->num_xfered + |
| 774 | (cnt * 4), |
| 775 | ®_val, |
| 776 | remainder); |
Nicolas Boichat | de327e4 | 2015-12-27 18:17:06 +0800 | [diff] [blame] | 777 | } |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 778 | } |
Daniel Kurtz | 1ce2486 | 2017-01-27 00:21:54 +0800 | [diff] [blame] | 779 | |
Peter Shih | 00bca73 | 2018-09-10 11:54:21 +0800 | [diff] [blame] | 780 | mdata->num_xfered += mdata->xfer_len; |
| 781 | if (mdata->num_xfered == trans->len) { |
Daniel Kurtz | 1ce2486 | 2017-01-27 00:21:54 +0800 | [diff] [blame] | 782 | spi_finalize_current_transfer(master); |
| 783 | return IRQ_HANDLED; |
| 784 | } |
| 785 | |
Peter Shih | 00bca73 | 2018-09-10 11:54:21 +0800 | [diff] [blame] | 786 | len = trans->len - mdata->num_xfered; |
| 787 | mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len); |
Daniel Kurtz | 1ce2486 | 2017-01-27 00:21:54 +0800 | [diff] [blame] | 788 | mtk_spi_setup_packet(master); |
| 789 | |
Leilk Liu | a4d8f64 | 2018-10-31 16:49:16 +0800 | [diff] [blame] | 790 | cnt = mdata->xfer_len / 4; |
Peter Shih | 00bca73 | 2018-09-10 11:54:21 +0800 | [diff] [blame] | 791 | iowrite32_rep(mdata->base + SPI_TX_DATA_REG, |
| 792 | trans->tx_buf + mdata->num_xfered, cnt); |
Daniel Kurtz | 1ce2486 | 2017-01-27 00:21:54 +0800 | [diff] [blame] | 793 | |
Leilk Liu | a4d8f64 | 2018-10-31 16:49:16 +0800 | [diff] [blame] | 794 | remainder = mdata->xfer_len % 4; |
Daniel Kurtz | 1ce2486 | 2017-01-27 00:21:54 +0800 | [diff] [blame] | 795 | if (remainder > 0) { |
| 796 | reg_val = 0; |
Peter Shih | 00bca73 | 2018-09-10 11:54:21 +0800 | [diff] [blame] | 797 | memcpy(®_val, |
| 798 | trans->tx_buf + (cnt * 4) + mdata->num_xfered, |
| 799 | remainder); |
Daniel Kurtz | 1ce2486 | 2017-01-27 00:21:54 +0800 | [diff] [blame] | 800 | writel(reg_val, mdata->base + SPI_TX_DATA_REG); |
| 801 | } |
| 802 | |
| 803 | mtk_spi_enable_transfer(master); |
| 804 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 805 | return IRQ_HANDLED; |
| 806 | } |
| 807 | |
| 808 | if (mdata->tx_sgl) |
| 809 | trans->tx_dma += mdata->xfer_len; |
| 810 | if (mdata->rx_sgl) |
| 811 | trans->rx_dma += mdata->xfer_len; |
| 812 | |
| 813 | if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) { |
| 814 | mdata->tx_sgl = sg_next(mdata->tx_sgl); |
| 815 | if (mdata->tx_sgl) { |
| 816 | trans->tx_dma = sg_dma_address(mdata->tx_sgl); |
| 817 | mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); |
| 818 | } |
| 819 | } |
| 820 | if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) { |
| 821 | mdata->rx_sgl = sg_next(mdata->rx_sgl); |
| 822 | if (mdata->rx_sgl) { |
| 823 | trans->rx_dma = sg_dma_address(mdata->rx_sgl); |
| 824 | mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); |
| 825 | } |
| 826 | } |
| 827 | |
| 828 | if (!mdata->tx_sgl && !mdata->rx_sgl) { |
| 829 | /* spi disable dma */ |
| 830 | cmd = readl(mdata->base + SPI_CMD_REG); |
| 831 | cmd &= ~SPI_CMD_TX_DMA; |
| 832 | cmd &= ~SPI_CMD_RX_DMA; |
| 833 | writel(cmd, mdata->base + SPI_CMD_REG); |
| 834 | |
| 835 | spi_finalize_current_transfer(master); |
| 836 | return IRQ_HANDLED; |
| 837 | } |
| 838 | |
| 839 | mtk_spi_update_mdata_len(master); |
| 840 | mtk_spi_setup_packet(master); |
| 841 | mtk_spi_setup_dma_addr(master, trans); |
| 842 | mtk_spi_enable_transfer(master); |
| 843 | |
| 844 | return IRQ_HANDLED; |
| 845 | } |
| 846 | |
Leilk Liu | 9f763fd | 2022-03-21 09:39:20 +0800 | [diff] [blame] | 847 | static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, |
| 848 | struct spi_mem_op *op) |
| 849 | { |
| 850 | int opcode_len; |
| 851 | |
| 852 | if (op->data.dir != SPI_MEM_NO_DATA) { |
| 853 | opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes; |
| 854 | if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { |
| 855 | op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len; |
| 856 | /* force data buffer dma-aligned. */ |
| 857 | op->data.nbytes -= op->data.nbytes % 4; |
| 858 | } |
| 859 | } |
| 860 | |
| 861 | return 0; |
| 862 | } |
| 863 | |
| 864 | static bool mtk_spi_mem_supports_op(struct spi_mem *mem, |
| 865 | const struct spi_mem_op *op) |
| 866 | { |
| 867 | if (!spi_mem_default_supports_op(mem, op)) |
| 868 | return false; |
| 869 | |
| 870 | if (op->addr.nbytes && op->dummy.nbytes && |
| 871 | op->addr.buswidth != op->dummy.buswidth) |
| 872 | return false; |
| 873 | |
| 874 | if (op->addr.nbytes + op->dummy.nbytes > 16) |
| 875 | return false; |
| 876 | |
| 877 | if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { |
| 878 | if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE > |
| 879 | MTK_SPI_IPM_PACKET_LOOP || |
| 880 | op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0) |
| 881 | return false; |
| 882 | } |
| 883 | |
| 884 | return true; |
| 885 | } |
| 886 | |
| 887 | static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master, |
| 888 | const struct spi_mem_op *op) |
| 889 | { |
| 890 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
| 891 | |
| 892 | writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK), |
| 893 | mdata->base + SPI_TX_SRC_REG); |
| 894 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
| 895 | if (mdata->dev_comp->dma_ext) |
| 896 | writel((u32)(mdata->tx_dma >> 32), |
| 897 | mdata->base + SPI_TX_SRC_REG_64); |
| 898 | #endif |
| 899 | |
| 900 | if (op->data.dir == SPI_MEM_DATA_IN) { |
| 901 | writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK), |
| 902 | mdata->base + SPI_RX_DST_REG); |
| 903 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
| 904 | if (mdata->dev_comp->dma_ext) |
| 905 | writel((u32)(mdata->rx_dma >> 32), |
| 906 | mdata->base + SPI_RX_DST_REG_64); |
| 907 | #endif |
| 908 | } |
| 909 | } |
| 910 | |
| 911 | static int mtk_spi_transfer_wait(struct spi_mem *mem, |
| 912 | const struct spi_mem_op *op) |
| 913 | { |
| 914 | struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); |
| 915 | /* |
| 916 | * For each byte we wait for 8 cycles of the SPI clock. |
| 917 | * Since speed is defined in Hz and we want milliseconds, |
| 918 | * so it should be 8 * 1000. |
| 919 | */ |
| 920 | u64 ms = 8000LL; |
| 921 | |
| 922 | if (op->data.dir == SPI_MEM_NO_DATA) |
| 923 | ms *= 32; /* prevent we may get 0 for short transfers. */ |
| 924 | else |
| 925 | ms *= op->data.nbytes; |
| 926 | ms = div_u64(ms, mem->spi->max_speed_hz); |
| 927 | ms += ms + 1000; /* 1s tolerance */ |
| 928 | |
| 929 | if (ms > UINT_MAX) |
| 930 | ms = UINT_MAX; |
| 931 | |
| 932 | if (!wait_for_completion_timeout(&mdata->spimem_done, |
| 933 | msecs_to_jiffies(ms))) { |
| 934 | dev_err(mdata->dev, "spi-mem transfer timeout\n"); |
| 935 | return -ETIMEDOUT; |
| 936 | } |
| 937 | |
| 938 | return 0; |
| 939 | } |
| 940 | |
| 941 | static int mtk_spi_mem_exec_op(struct spi_mem *mem, |
| 942 | const struct spi_mem_op *op) |
| 943 | { |
| 944 | struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); |
| 945 | u32 reg_val, nio, tx_size; |
| 946 | char *tx_tmp_buf, *rx_tmp_buf; |
| 947 | int ret = 0; |
| 948 | |
| 949 | mdata->use_spimem = true; |
| 950 | reinit_completion(&mdata->spimem_done); |
| 951 | |
| 952 | mtk_spi_reset(mdata); |
| 953 | mtk_spi_hw_init(mem->spi->master, mem->spi); |
| 954 | mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz); |
| 955 | |
| 956 | reg_val = readl(mdata->base + SPI_CFG3_IPM_REG); |
| 957 | /* opcode byte len */ |
| 958 | reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK; |
| 959 | reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET; |
| 960 | |
| 961 | /* addr & dummy byte len */ |
| 962 | reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK; |
| 963 | if (op->addr.nbytes || op->dummy.nbytes) |
| 964 | reg_val |= (op->addr.nbytes + op->dummy.nbytes) << |
| 965 | SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET; |
| 966 | |
| 967 | /* data byte len */ |
| 968 | if (op->data.dir == SPI_MEM_NO_DATA) { |
| 969 | reg_val |= SPI_CFG3_IPM_NODATA_FLAG; |
| 970 | writel(0, mdata->base + SPI_CFG1_REG); |
| 971 | } else { |
| 972 | reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG; |
| 973 | mdata->xfer_len = op->data.nbytes; |
| 974 | mtk_spi_setup_packet(mem->spi->master); |
| 975 | } |
| 976 | |
| 977 | if (op->addr.nbytes || op->dummy.nbytes) { |
| 978 | if (op->addr.buswidth == 1 || op->dummy.buswidth == 1) |
| 979 | reg_val |= SPI_CFG3_IPM_XMODE_EN; |
| 980 | else |
| 981 | reg_val &= ~SPI_CFG3_IPM_XMODE_EN; |
| 982 | } |
| 983 | |
| 984 | if (op->addr.buswidth == 2 || |
| 985 | op->dummy.buswidth == 2 || |
| 986 | op->data.buswidth == 2) |
| 987 | nio = 2; |
| 988 | else if (op->addr.buswidth == 4 || |
| 989 | op->dummy.buswidth == 4 || |
| 990 | op->data.buswidth == 4) |
| 991 | nio = 4; |
| 992 | else |
| 993 | nio = 1; |
| 994 | |
| 995 | reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK; |
| 996 | reg_val |= PIN_MODE_CFG(nio); |
| 997 | |
| 998 | reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN; |
| 999 | if (op->data.dir == SPI_MEM_DATA_IN) |
| 1000 | reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR; |
| 1001 | else |
| 1002 | reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR; |
| 1003 | writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); |
| 1004 | |
| 1005 | tx_size = 1 + op->addr.nbytes + op->dummy.nbytes; |
| 1006 | if (op->data.dir == SPI_MEM_DATA_OUT) |
| 1007 | tx_size += op->data.nbytes; |
| 1008 | |
| 1009 | tx_size = max_t(u32, tx_size, 32); |
| 1010 | |
| 1011 | tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL | GFP_DMA); |
| 1012 | if (!tx_tmp_buf) { |
| 1013 | mdata->use_spimem = false; |
| 1014 | return -ENOMEM; |
| 1015 | } |
| 1016 | |
| 1017 | tx_tmp_buf[0] = op->cmd.opcode; |
| 1018 | |
| 1019 | if (op->addr.nbytes) { |
| 1020 | int i; |
| 1021 | |
| 1022 | for (i = 0; i < op->addr.nbytes; i++) |
| 1023 | tx_tmp_buf[i + 1] = op->addr.val >> |
| 1024 | (8 * (op->addr.nbytes - i - 1)); |
| 1025 | } |
| 1026 | |
| 1027 | if (op->dummy.nbytes) |
| 1028 | memset(tx_tmp_buf + op->addr.nbytes + 1, |
| 1029 | 0xff, |
| 1030 | op->dummy.nbytes); |
| 1031 | |
| 1032 | if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) |
| 1033 | memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1, |
| 1034 | op->data.buf.out, |
| 1035 | op->data.nbytes); |
| 1036 | |
| 1037 | mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf, |
| 1038 | tx_size, DMA_TO_DEVICE); |
| 1039 | if (dma_mapping_error(mdata->dev, mdata->tx_dma)) { |
| 1040 | ret = -ENOMEM; |
| 1041 | goto err_exit; |
| 1042 | } |
| 1043 | |
| 1044 | if (op->data.dir == SPI_MEM_DATA_IN) { |
| 1045 | if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) { |
| 1046 | rx_tmp_buf = kzalloc(op->data.nbytes, |
| 1047 | GFP_KERNEL | GFP_DMA); |
| 1048 | if (!rx_tmp_buf) { |
| 1049 | ret = -ENOMEM; |
| 1050 | goto unmap_tx_dma; |
| 1051 | } |
| 1052 | } else { |
| 1053 | rx_tmp_buf = op->data.buf.in; |
| 1054 | } |
| 1055 | |
| 1056 | mdata->rx_dma = dma_map_single(mdata->dev, |
| 1057 | rx_tmp_buf, |
| 1058 | op->data.nbytes, |
| 1059 | DMA_FROM_DEVICE); |
| 1060 | if (dma_mapping_error(mdata->dev, mdata->rx_dma)) { |
| 1061 | ret = -ENOMEM; |
| 1062 | goto kfree_rx_tmp_buf; |
| 1063 | } |
| 1064 | } |
| 1065 | |
| 1066 | reg_val = readl(mdata->base + SPI_CMD_REG); |
| 1067 | reg_val |= SPI_CMD_TX_DMA; |
| 1068 | if (op->data.dir == SPI_MEM_DATA_IN) |
| 1069 | reg_val |= SPI_CMD_RX_DMA; |
| 1070 | writel(reg_val, mdata->base + SPI_CMD_REG); |
| 1071 | |
| 1072 | mtk_spi_mem_setup_dma_xfer(mem->spi->master, op); |
| 1073 | |
| 1074 | mtk_spi_enable_transfer(mem->spi->master); |
| 1075 | |
| 1076 | /* Wait for the interrupt. */ |
| 1077 | ret = mtk_spi_transfer_wait(mem, op); |
| 1078 | if (ret) |
| 1079 | goto unmap_rx_dma; |
| 1080 | |
| 1081 | /* spi disable dma */ |
| 1082 | reg_val = readl(mdata->base + SPI_CMD_REG); |
| 1083 | reg_val &= ~SPI_CMD_TX_DMA; |
| 1084 | if (op->data.dir == SPI_MEM_DATA_IN) |
| 1085 | reg_val &= ~SPI_CMD_RX_DMA; |
| 1086 | writel(reg_val, mdata->base + SPI_CMD_REG); |
| 1087 | |
| 1088 | unmap_rx_dma: |
| 1089 | if (op->data.dir == SPI_MEM_DATA_IN) { |
| 1090 | dma_unmap_single(mdata->dev, mdata->rx_dma, |
| 1091 | op->data.nbytes, DMA_FROM_DEVICE); |
| 1092 | if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) |
| 1093 | memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes); |
| 1094 | } |
| 1095 | kfree_rx_tmp_buf: |
| 1096 | if (op->data.dir == SPI_MEM_DATA_IN && |
| 1097 | !IS_ALIGNED((size_t)op->data.buf.in, 4)) |
| 1098 | kfree(rx_tmp_buf); |
| 1099 | unmap_tx_dma: |
| 1100 | dma_unmap_single(mdata->dev, mdata->tx_dma, |
| 1101 | tx_size, DMA_TO_DEVICE); |
| 1102 | err_exit: |
| 1103 | kfree(tx_tmp_buf); |
| 1104 | mdata->use_spimem = false; |
| 1105 | |
| 1106 | return ret; |
| 1107 | } |
| 1108 | |
| 1109 | static const struct spi_controller_mem_ops mtk_spi_mem_ops = { |
| 1110 | .adjust_op_size = mtk_spi_mem_adjust_op_size, |
| 1111 | .supports_op = mtk_spi_mem_supports_op, |
| 1112 | .exec_op = mtk_spi_mem_exec_op, |
| 1113 | }; |
| 1114 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1115 | static int mtk_spi_probe(struct platform_device *pdev) |
| 1116 | { |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1117 | struct device *dev = &pdev->dev; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1118 | struct spi_master *master; |
| 1119 | struct mtk_spi *mdata; |
luhua.xu | fdeae8f | 2019-09-11 05:55:31 -0400 | [diff] [blame] | 1120 | int i, irq, ret, addr_bits; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1121 | |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1122 | master = devm_spi_alloc_master(dev, sizeof(*mdata)); |
AngeloGioacchino Del Regno | 20cdbb8 | 2022-04-07 13:44:26 +0200 | [diff] [blame] | 1123 | if (!master) |
| 1124 | return dev_err_probe(dev, -ENOMEM, "failed to alloc spi master\n"); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1125 | |
| 1126 | master->auto_runtime_pm = true; |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1127 | master->dev.of_node = dev->of_node; |
Leilk Liu | 3e582c6 | 2019-06-05 11:07:04 +0800 | [diff] [blame] | 1128 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1129 | |
| 1130 | master->set_cs = mtk_spi_set_cs; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1131 | master->prepare_message = mtk_spi_prepare_message; |
| 1132 | master->transfer_one = mtk_spi_transfer_one; |
| 1133 | master->can_dma = mtk_spi_can_dma; |
Leilk Liu | 58a984c7 | 2015-10-26 16:09:43 +0800 | [diff] [blame] | 1134 | master->setup = mtk_spi_setup; |
leilk.liu | 9f6e7e8 | 2021-02-07 11:09:53 +0800 | [diff] [blame] | 1135 | master->set_cs_timing = mtk_spi_set_hw_cs_timing; |
Linus Walleij | 1a5a87d | 2022-01-22 01:33:02 +0100 | [diff] [blame] | 1136 | master->use_gpio_descriptors = true; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1137 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1138 | mdata = spi_master_get_devdata(master); |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1139 | mdata->dev_comp = device_get_match_data(dev); |
Luhua Xu | ae7c2d3 | 2019-11-18 12:57:16 +0800 | [diff] [blame] | 1140 | |
| 1141 | if (mdata->dev_comp->enhance_timing) |
| 1142 | master->mode_bits |= SPI_CS_HIGH; |
| 1143 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1144 | if (mdata->dev_comp->must_tx) |
| 1145 | master->flags = SPI_MASTER_MUST_TX; |
Leilk Liu | 7e963fb | 2022-03-15 11:24:08 +0800 | [diff] [blame] | 1146 | if (mdata->dev_comp->ipm_design) |
| 1147 | master->mode_bits |= SPI_LOOP; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1148 | |
Leilk Liu | 9f763fd | 2022-03-21 09:39:20 +0800 | [diff] [blame] | 1149 | if (mdata->dev_comp->ipm_design) { |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1150 | mdata->dev = dev; |
Leilk Liu | 9f763fd | 2022-03-21 09:39:20 +0800 | [diff] [blame] | 1151 | master->mem_ops = &mtk_spi_mem_ops; |
| 1152 | init_completion(&mdata->spimem_done); |
| 1153 | } |
| 1154 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1155 | if (mdata->dev_comp->need_pad_sel) { |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1156 | mdata->pad_num = of_property_count_u32_elems(dev->of_node, |
Leilk Liu | 3745760 | 2015-10-26 16:09:44 +0800 | [diff] [blame] | 1157 | "mediatek,pad-select"); |
AngeloGioacchino Del Regno | 20cdbb8 | 2022-04-07 13:44:26 +0200 | [diff] [blame] | 1158 | if (mdata->pad_num < 0) |
| 1159 | return dev_err_probe(dev, -EINVAL, |
Leilk Liu | 3745760 | 2015-10-26 16:09:44 +0800 | [diff] [blame] | 1160 | "No 'mediatek,pad-select' property\n"); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1161 | |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1162 | mdata->pad_sel = devm_kmalloc_array(dev, mdata->pad_num, |
Leilk Liu | 3745760 | 2015-10-26 16:09:44 +0800 | [diff] [blame] | 1163 | sizeof(u32), GFP_KERNEL); |
AngeloGioacchino Del Regno | ace1458 | 2022-04-07 13:44:21 +0200 | [diff] [blame] | 1164 | if (!mdata->pad_sel) |
| 1165 | return -ENOMEM; |
Leilk Liu | 3745760 | 2015-10-26 16:09:44 +0800 | [diff] [blame] | 1166 | |
| 1167 | for (i = 0; i < mdata->pad_num; i++) { |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1168 | of_property_read_u32_index(dev->of_node, |
Leilk Liu | 3745760 | 2015-10-26 16:09:44 +0800 | [diff] [blame] | 1169 | "mediatek,pad-select", |
| 1170 | i, &mdata->pad_sel[i]); |
AngeloGioacchino Del Regno | 20cdbb8 | 2022-04-07 13:44:26 +0200 | [diff] [blame] | 1171 | if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) |
| 1172 | return dev_err_probe(dev, -EINVAL, |
| 1173 | "wrong pad-sel[%d]: %u\n", |
| 1174 | i, mdata->pad_sel[i]); |
Leilk Liu | 3745760 | 2015-10-26 16:09:44 +0800 | [diff] [blame] | 1175 | } |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1176 | } |
| 1177 | |
| 1178 | platform_set_drvdata(pdev, master); |
Markus Elfring | 5dd381e7 | 2019-09-21 14:45:40 +0200 | [diff] [blame] | 1179 | mdata->base = devm_platform_ioremap_resource(pdev, 0); |
AngeloGioacchino Del Regno | ace1458 | 2022-04-07 13:44:21 +0200 | [diff] [blame] | 1180 | if (IS_ERR(mdata->base)) |
| 1181 | return PTR_ERR(mdata->base); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1182 | |
| 1183 | irq = platform_get_irq(pdev, 0); |
AngeloGioacchino Del Regno | ace1458 | 2022-04-07 13:44:21 +0200 | [diff] [blame] | 1184 | if (irq < 0) |
| 1185 | return irq; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1186 | |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1187 | if (!dev->dma_mask) |
| 1188 | dev->dma_mask = &dev->coherent_dma_mask; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1189 | |
zhichao.liu | 309e98548 | 2022-09-27 16:32:48 +0800 | [diff] [blame] | 1190 | if (mdata->dev_comp->ipm_design) |
| 1191 | dma_set_max_seg_size(dev, SZ_16M); |
| 1192 | else |
| 1193 | dma_set_max_seg_size(dev, SZ_256K); |
| 1194 | |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1195 | mdata->parent_clk = devm_clk_get(dev, "parent-clk"); |
AngeloGioacchino Del Regno | 20cdbb8 | 2022-04-07 13:44:26 +0200 | [diff] [blame] | 1196 | if (IS_ERR(mdata->parent_clk)) |
| 1197 | return dev_err_probe(dev, PTR_ERR(mdata->parent_clk), |
| 1198 | "failed to get parent-clk\n"); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1199 | |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1200 | mdata->sel_clk = devm_clk_get(dev, "sel-clk"); |
AngeloGioacchino Del Regno | 20cdbb8 | 2022-04-07 13:44:26 +0200 | [diff] [blame] | 1201 | if (IS_ERR(mdata->sel_clk)) |
| 1202 | return dev_err_probe(dev, PTR_ERR(mdata->sel_clk), "failed to get sel-clk\n"); |
Leilk Liu | adcbcfe | 2015-08-31 21:18:57 +0800 | [diff] [blame] | 1203 | |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1204 | mdata->spi_clk = devm_clk_get(dev, "spi-clk"); |
AngeloGioacchino Del Regno | 20cdbb8 | 2022-04-07 13:44:26 +0200 | [diff] [blame] | 1205 | if (IS_ERR(mdata->spi_clk)) |
| 1206 | return dev_err_probe(dev, PTR_ERR(mdata->spi_clk), "failed to get spi-clk\n"); |
Leilk Liu | adcbcfe | 2015-08-31 21:18:57 +0800 | [diff] [blame] | 1207 | |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1208 | mdata->spi_hclk = devm_clk_get_optional(dev, "hclk"); |
AngeloGioacchino Del Regno | 20cdbb8 | 2022-04-07 13:44:26 +0200 | [diff] [blame] | 1209 | if (IS_ERR(mdata->spi_hclk)) |
| 1210 | return dev_err_probe(dev, PTR_ERR(mdata->spi_hclk), "failed to get hclk\n"); |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1211 | |
AngeloGioacchino Del Regno | 5dee8bb | 2022-04-07 13:44:24 +0200 | [diff] [blame] | 1212 | ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); |
AngeloGioacchino Del Regno | 20cdbb8 | 2022-04-07 13:44:26 +0200 | [diff] [blame] | 1213 | if (ret < 0) |
| 1214 | return dev_err_probe(dev, ret, "failed to clk_set_parent\n"); |
AngeloGioacchino Del Regno | 5dee8bb | 2022-04-07 13:44:24 +0200 | [diff] [blame] | 1215 | |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1216 | ret = clk_prepare_enable(mdata->spi_hclk); |
AngeloGioacchino Del Regno | 20cdbb8 | 2022-04-07 13:44:26 +0200 | [diff] [blame] | 1217 | if (ret < 0) |
| 1218 | return dev_err_probe(dev, ret, "failed to enable hclk\n"); |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1219 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1220 | ret = clk_prepare_enable(mdata->spi_clk); |
| 1221 | if (ret < 0) { |
AngeloGioacchino Del Regno | 5dee8bb | 2022-04-07 13:44:24 +0200 | [diff] [blame] | 1222 | clk_disable_unprepare(mdata->spi_hclk); |
AngeloGioacchino Del Regno | 20cdbb8 | 2022-04-07 13:44:26 +0200 | [diff] [blame] | 1223 | return dev_err_probe(dev, ret, "failed to enable spi_clk\n"); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1224 | } |
| 1225 | |
Mason Zhang | 162a31e | 2021-06-29 18:08:15 +0800 | [diff] [blame] | 1226 | mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk); |
| 1227 | |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1228 | if (mdata->dev_comp->no_need_unprepare) { |
Mason Zhang | 162a31e | 2021-06-29 18:08:15 +0800 | [diff] [blame] | 1229 | clk_disable(mdata->spi_clk); |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1230 | clk_disable(mdata->spi_hclk); |
| 1231 | } else { |
Mason Zhang | 162a31e | 2021-06-29 18:08:15 +0800 | [diff] [blame] | 1232 | clk_disable_unprepare(mdata->spi_clk); |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1233 | clk_disable_unprepare(mdata->spi_hclk); |
| 1234 | } |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1235 | |
Leilk Liu | 3745760 | 2015-10-26 16:09:44 +0800 | [diff] [blame] | 1236 | if (mdata->dev_comp->need_pad_sel) { |
AngeloGioacchino Del Regno | 20cdbb8 | 2022-04-07 13:44:26 +0200 | [diff] [blame] | 1237 | if (mdata->pad_num != master->num_chipselect) |
| 1238 | return dev_err_probe(dev, -EINVAL, |
Leilk Liu | 3745760 | 2015-10-26 16:09:44 +0800 | [diff] [blame] | 1239 | "pad_num does not match num_chipselect(%d != %d)\n", |
| 1240 | mdata->pad_num, master->num_chipselect); |
Leilk Liu | 3745760 | 2015-10-26 16:09:44 +0800 | [diff] [blame] | 1241 | |
AngeloGioacchino Del Regno | 20cdbb8 | 2022-04-07 13:44:26 +0200 | [diff] [blame] | 1242 | if (!master->cs_gpiods && master->num_chipselect > 1) |
| 1243 | return dev_err_probe(dev, -EINVAL, |
Nicolas Boichat | 98c8dcc | 2015-11-09 12:14:51 +0800 | [diff] [blame] | 1244 | "cs_gpios not specified and num_chipselect > 1\n"); |
Leilk Liu | 3745760 | 2015-10-26 16:09:44 +0800 | [diff] [blame] | 1245 | } |
| 1246 | |
luhua.xu | fdeae8f | 2019-09-11 05:55:31 -0400 | [diff] [blame] | 1247 | if (mdata->dev_comp->dma_ext) |
| 1248 | addr_bits = DMA_ADDR_EXT_BITS; |
| 1249 | else |
| 1250 | addr_bits = DMA_ADDR_DEF_BITS; |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1251 | ret = dma_set_mask(dev, DMA_BIT_MASK(addr_bits)); |
luhua.xu | fdeae8f | 2019-09-11 05:55:31 -0400 | [diff] [blame] | 1252 | if (ret) |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1253 | dev_notice(dev, "SPI dma_set_mask(%d) failed, ret:%d\n", |
luhua.xu | fdeae8f | 2019-09-11 05:55:31 -0400 | [diff] [blame] | 1254 | addr_bits, ret); |
| 1255 | |
AngeloGioacchino Del Regno | 5088b31 | 2022-04-07 13:44:25 +0200 | [diff] [blame] | 1256 | pm_runtime_enable(dev); |
| 1257 | |
AngeloGioacchino Del Regno | 6b44405 | 2022-04-07 13:44:23 +0200 | [diff] [blame] | 1258 | ret = devm_spi_register_master(dev, master); |
Mason Zhang | c934fec | 2021-07-13 19:42:48 +0800 | [diff] [blame] | 1259 | if (ret) { |
AngeloGioacchino Del Regno | 5088b31 | 2022-04-07 13:44:25 +0200 | [diff] [blame] | 1260 | pm_runtime_disable(dev); |
AngeloGioacchino Del Regno | 20cdbb8 | 2022-04-07 13:44:26 +0200 | [diff] [blame] | 1261 | return dev_err_probe(dev, ret, "failed to register master\n"); |
Mason Zhang | c934fec | 2021-07-13 19:42:48 +0800 | [diff] [blame] | 1262 | } |
| 1263 | |
Ricardo Ribalda | c6f7874 | 2022-11-28 12:00:01 +0100 | [diff] [blame] | 1264 | ret = devm_request_irq(dev, irq, mtk_spi_interrupt, |
| 1265 | IRQF_TRIGGER_NONE, dev_name(dev), master); |
| 1266 | if (ret) { |
| 1267 | pm_runtime_disable(dev); |
| 1268 | return dev_err_probe(dev, ret, "failed to register irq\n"); |
| 1269 | } |
| 1270 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1271 | return 0; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1272 | } |
| 1273 | |
| 1274 | static int mtk_spi_remove(struct platform_device *pdev) |
| 1275 | { |
| 1276 | struct spi_master *master = platform_get_drvdata(pdev); |
| 1277 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
Zhichao Liu | 0d10e90 | 2022-11-10 15:28:39 +0800 | [diff] [blame] | 1278 | int ret; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1279 | |
Zhichao Liu | 0d10e90 | 2022-11-10 15:28:39 +0800 | [diff] [blame] | 1280 | ret = pm_runtime_resume_and_get(&pdev->dev); |
| 1281 | if (ret < 0) |
| 1282 | return ret; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1283 | |
| 1284 | mtk_spi_reset(mdata); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1285 | |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1286 | if (mdata->dev_comp->no_need_unprepare) { |
Mason Zhang | 162a31e | 2021-06-29 18:08:15 +0800 | [diff] [blame] | 1287 | clk_unprepare(mdata->spi_clk); |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1288 | clk_unprepare(mdata->spi_hclk); |
| 1289 | } |
Mason Zhang | 162a31e | 2021-06-29 18:08:15 +0800 | [diff] [blame] | 1290 | |
Zhichao Liu | 0d10e90 | 2022-11-10 15:28:39 +0800 | [diff] [blame] | 1291 | pm_runtime_put_noidle(&pdev->dev); |
| 1292 | pm_runtime_disable(&pdev->dev); |
| 1293 | |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1294 | return 0; |
| 1295 | } |
| 1296 | |
| 1297 | #ifdef CONFIG_PM_SLEEP |
| 1298 | static int mtk_spi_suspend(struct device *dev) |
| 1299 | { |
| 1300 | int ret; |
| 1301 | struct spi_master *master = dev_get_drvdata(dev); |
| 1302 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
| 1303 | |
| 1304 | ret = spi_master_suspend(master); |
| 1305 | if (ret) |
| 1306 | return ret; |
| 1307 | |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1308 | if (!pm_runtime_suspended(dev)) { |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1309 | clk_disable_unprepare(mdata->spi_clk); |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1310 | clk_disable_unprepare(mdata->spi_hclk); |
| 1311 | } |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1312 | |
| 1313 | return ret; |
| 1314 | } |
| 1315 | |
| 1316 | static int mtk_spi_resume(struct device *dev) |
| 1317 | { |
| 1318 | int ret; |
| 1319 | struct spi_master *master = dev_get_drvdata(dev); |
| 1320 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
| 1321 | |
| 1322 | if (!pm_runtime_suspended(dev)) { |
| 1323 | ret = clk_prepare_enable(mdata->spi_clk); |
Leilk Liu | 13da5a0 | 2015-08-24 11:45:17 +0800 | [diff] [blame] | 1324 | if (ret < 0) { |
| 1325 | dev_err(dev, "failed to enable spi_clk (%d)\n", ret); |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1326 | return ret; |
Leilk Liu | 13da5a0 | 2015-08-24 11:45:17 +0800 | [diff] [blame] | 1327 | } |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1328 | |
| 1329 | ret = clk_prepare_enable(mdata->spi_hclk); |
| 1330 | if (ret < 0) { |
| 1331 | dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); |
| 1332 | clk_disable_unprepare(mdata->spi_clk); |
| 1333 | return ret; |
| 1334 | } |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1335 | } |
| 1336 | |
| 1337 | ret = spi_master_resume(master); |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1338 | if (ret < 0) { |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1339 | clk_disable_unprepare(mdata->spi_clk); |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1340 | clk_disable_unprepare(mdata->spi_hclk); |
| 1341 | } |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1342 | |
| 1343 | return ret; |
| 1344 | } |
| 1345 | #endif /* CONFIG_PM_SLEEP */ |
| 1346 | |
| 1347 | #ifdef CONFIG_PM |
| 1348 | static int mtk_spi_runtime_suspend(struct device *dev) |
| 1349 | { |
| 1350 | struct spi_master *master = dev_get_drvdata(dev); |
| 1351 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
| 1352 | |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1353 | if (mdata->dev_comp->no_need_unprepare) { |
Mason Zhang | 162a31e | 2021-06-29 18:08:15 +0800 | [diff] [blame] | 1354 | clk_disable(mdata->spi_clk); |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1355 | clk_disable(mdata->spi_hclk); |
| 1356 | } else { |
Mason Zhang | 162a31e | 2021-06-29 18:08:15 +0800 | [diff] [blame] | 1357 | clk_disable_unprepare(mdata->spi_clk); |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1358 | clk_disable_unprepare(mdata->spi_hclk); |
| 1359 | } |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1360 | |
| 1361 | return 0; |
| 1362 | } |
| 1363 | |
| 1364 | static int mtk_spi_runtime_resume(struct device *dev) |
| 1365 | { |
| 1366 | struct spi_master *master = dev_get_drvdata(dev); |
| 1367 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
Leilk Liu | 13da5a0 | 2015-08-24 11:45:17 +0800 | [diff] [blame] | 1368 | int ret; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1369 | |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1370 | if (mdata->dev_comp->no_need_unprepare) { |
Mason Zhang | 162a31e | 2021-06-29 18:08:15 +0800 | [diff] [blame] | 1371 | ret = clk_enable(mdata->spi_clk); |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1372 | if (ret < 0) { |
| 1373 | dev_err(dev, "failed to enable spi_clk (%d)\n", ret); |
| 1374 | return ret; |
| 1375 | } |
| 1376 | ret = clk_enable(mdata->spi_hclk); |
| 1377 | if (ret < 0) { |
| 1378 | dev_err(dev, "failed to enable spi_hclk (%d)\n", ret); |
| 1379 | clk_disable(mdata->spi_clk); |
| 1380 | return ret; |
| 1381 | } |
| 1382 | } else { |
Mason Zhang | 162a31e | 2021-06-29 18:08:15 +0800 | [diff] [blame] | 1383 | ret = clk_prepare_enable(mdata->spi_clk); |
Leilk Liu | a740f4e | 2022-03-21 09:39:22 +0800 | [diff] [blame] | 1384 | if (ret < 0) { |
| 1385 | dev_err(dev, "failed to prepare_enable spi_clk (%d)\n", ret); |
| 1386 | return ret; |
| 1387 | } |
| 1388 | |
| 1389 | ret = clk_prepare_enable(mdata->spi_hclk); |
| 1390 | if (ret < 0) { |
| 1391 | dev_err(dev, "failed to prepare_enable spi_hclk (%d)\n", ret); |
| 1392 | clk_disable_unprepare(mdata->spi_clk); |
| 1393 | return ret; |
| 1394 | } |
Leilk Liu | 13da5a0 | 2015-08-24 11:45:17 +0800 | [diff] [blame] | 1395 | } |
| 1396 | |
| 1397 | return 0; |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1398 | } |
| 1399 | #endif /* CONFIG_PM */ |
| 1400 | |
| 1401 | static const struct dev_pm_ops mtk_spi_pm = { |
| 1402 | SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume) |
| 1403 | SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend, |
| 1404 | mtk_spi_runtime_resume, NULL) |
| 1405 | }; |
| 1406 | |
kbuild test robot | 4299aaa | 2015-08-07 22:33:11 +0800 | [diff] [blame] | 1407 | static struct platform_driver mtk_spi_driver = { |
Leilk Liu | a568231 | 2015-08-07 15:19:50 +0800 | [diff] [blame] | 1408 | .driver = { |
| 1409 | .name = "mtk-spi", |
| 1410 | .pm = &mtk_spi_pm, |
| 1411 | .of_match_table = mtk_spi_of_match, |
| 1412 | }, |
| 1413 | .probe = mtk_spi_probe, |
| 1414 | .remove = mtk_spi_remove, |
| 1415 | }; |
| 1416 | |
| 1417 | module_platform_driver(mtk_spi_driver); |
| 1418 | |
| 1419 | MODULE_DESCRIPTION("MTK SPI Controller driver"); |
| 1420 | MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>"); |
| 1421 | MODULE_LICENSE("GPL v2"); |
Axel Lin | e4001885c | 2015-08-11 09:15:30 +0800 | [diff] [blame] | 1422 | MODULE_ALIAS("platform:mtk-spi"); |