Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2007 MIPS Technologies, Inc. |
| 7 | * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org> |
| 8 | */ |
| 9 | #include <linux/clockchips.h> |
| 10 | #include <linux/interrupt.h> |
| 11 | #include <linux/percpu.h> |
Ralf Baechle | 631330f | 2009-06-19 14:05:26 +0100 | [diff] [blame] | 12 | #include <linux/smp.h> |
David Howells | ca4d3e67 | 2010-10-07 14:08:54 +0100 | [diff] [blame] | 13 | #include <linux/irq.h> |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 14 | |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 15 | #include <asm/time.h> |
Kevin D. Kissell | 8531a35 | 2008-09-09 21:48:52 +0200 | [diff] [blame] | 16 | #include <asm/cevt-r4k.h> |
| 17 | |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 18 | static int mips_next_event(unsigned long delta, |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 19 | struct clock_event_device *evt) |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 20 | { |
| 21 | unsigned int cnt; |
| 22 | int res; |
| 23 | |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 24 | cnt = read_c0_count(); |
| 25 | cnt += delta; |
| 26 | write_c0_compare(cnt); |
Kevin Cernekee | 5878fc9 | 2010-11-23 10:26:44 -0800 | [diff] [blame] | 27 | res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 28 | return res; |
| 29 | } |
| 30 | |
Kevin D. Kissell | 8531a35 | 2008-09-09 21:48:52 +0200 | [diff] [blame] | 31 | DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); |
| 32 | int cp0_timer_irq_installed; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 33 | |
James Hogan | 19971c0 | 2015-01-27 21:45:47 +0000 | [diff] [blame] | 34 | /* |
| 35 | * Possibly handle a performance counter interrupt. |
| 36 | * Return true if the timer interrupt should not be checked |
| 37 | */ |
| 38 | static inline int handle_perf_irq(int r2) |
| 39 | { |
| 40 | /* |
| 41 | * The performance counter overflow interrupt may be shared with the |
| 42 | * timer interrupt (cp0_perfcount_irq < 0). If it is and a |
| 43 | * performance counter has overflowed (perf_irq() == IRQ_HANDLED) |
| 44 | * and we can't reliably determine if a counter interrupt has also |
| 45 | * happened (!r2) then don't check for a timer interrupt. |
| 46 | */ |
| 47 | return (cp0_perfcount_irq < 0) && |
| 48 | perf_irq() == IRQ_HANDLED && |
| 49 | !r2; |
| 50 | } |
| 51 | |
Kevin D. Kissell | 8531a35 | 2008-09-09 21:48:52 +0200 | [diff] [blame] | 52 | irqreturn_t c0_compare_interrupt(int irq, void *dev_id) |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 53 | { |
Leonid Yegoshin | 54dac95 | 2014-11-13 13:39:39 +0000 | [diff] [blame] | 54 | const int r2 = cpu_has_mips_r2_r6; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 55 | struct clock_event_device *cd; |
| 56 | int cpu = smp_processor_id(); |
| 57 | |
| 58 | /* |
| 59 | * Suckage alert: |
| 60 | * Before R2 of the architecture there was no way to see if a |
| 61 | * performance counter interrupt was pending, so we have to run |
| 62 | * the performance counter interrupt handler anyway. |
| 63 | */ |
| 64 | if (handle_perf_irq(r2)) |
Ralf Baechle | f0c5b89 | 2015-03-20 19:45:09 +0100 | [diff] [blame] | 65 | return IRQ_HANDLED; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 66 | |
| 67 | /* |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 68 | * The same applies to performance counter interrupts. But with the |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 69 | * above we now know that the reason we got here must be a timer |
| 70 | * interrupt. Being the paranoiacs we are we check anyway. |
| 71 | */ |
James Hogan | 3ba5040 | 2015-01-27 21:45:48 +0000 | [diff] [blame] | 72 | if (!r2 || (read_c0_cause() & CAUSEF_TI)) { |
Kevin D. Kissell | 8531a35 | 2008-09-09 21:48:52 +0200 | [diff] [blame] | 73 | /* Clear Count/Compare Interrupt */ |
| 74 | write_c0_compare(read_c0_compare()); |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 75 | cd = &per_cpu(mips_clockevent_device, cpu); |
| 76 | cd->event_handler(cd); |
Ralf Baechle | f0c5b89 | 2015-03-20 19:45:09 +0100 | [diff] [blame] | 77 | |
| 78 | return IRQ_HANDLED; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 79 | } |
| 80 | |
Ralf Baechle | f0c5b89 | 2015-03-20 19:45:09 +0100 | [diff] [blame] | 81 | return IRQ_NONE; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 82 | } |
| 83 | |
Kevin D. Kissell | 8531a35 | 2008-09-09 21:48:52 +0200 | [diff] [blame] | 84 | struct irqaction c0_compare_irqaction = { |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 85 | .handler = c0_compare_interrupt, |
James Hogan | 7dfe819 | 2015-01-27 21:45:52 +0000 | [diff] [blame] | 86 | /* |
| 87 | * IRQF_SHARED: The timer interrupt may be shared with other interrupts |
| 88 | * such as perf counter and FDC interrupts. |
| 89 | */ |
| 90 | .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED, |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 91 | .name = "timer", |
| 92 | }; |
| 93 | |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 94 | |
Kevin D. Kissell | 8531a35 | 2008-09-09 21:48:52 +0200 | [diff] [blame] | 95 | void mips_event_handler(struct clock_event_device *dev) |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 96 | { |
| 97 | } |
| 98 | |
| 99 | /* |
| 100 | * FIXME: This doesn't hold for the relocated E9000 compare interrupt. |
| 101 | */ |
| 102 | static int c0_compare_int_pending(void) |
| 103 | { |
James Hogan | ae58d88 | 2015-01-19 12:00:55 +0000 | [diff] [blame] | 104 | /* When cpu_has_mips_r2, this checks Cause.TI instead of Cause.IP7 */ |
David VomLehn | 010c108 | 2009-12-21 17:49:22 -0800 | [diff] [blame] | 105 | return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP); |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 106 | } |
| 107 | |
Kevin D. Kissell | 8531a35 | 2008-09-09 21:48:52 +0200 | [diff] [blame] | 108 | /* |
| 109 | * Compare interrupt can be routed and latched outside the core, |
Al Cooper | 4f1a1eb | 2011-11-08 09:59:01 -0500 | [diff] [blame] | 110 | * so wait up to worst case number of cycle counter ticks for timer interrupt |
| 111 | * changes to propagate to the cause register. |
Kevin D. Kissell | 8531a35 | 2008-09-09 21:48:52 +0200 | [diff] [blame] | 112 | */ |
Al Cooper | 4f1a1eb | 2011-11-08 09:59:01 -0500 | [diff] [blame] | 113 | #define COMPARE_INT_SEEN_TICKS 50 |
Kevin D. Kissell | 8531a35 | 2008-09-09 21:48:52 +0200 | [diff] [blame] | 114 | |
| 115 | int c0_compare_int_usable(void) |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 116 | { |
Atsushi Nemoto | 3a6c43a | 2007-10-23 21:55:42 +0900 | [diff] [blame] | 117 | unsigned int delta; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 118 | unsigned int cnt; |
| 119 | |
Sanjay Lal | 9843b03 | 2012-11-21 18:34:03 -0800 | [diff] [blame] | 120 | #ifdef CONFIG_KVM_GUEST |
| 121 | return 1; |
| 122 | #endif |
| 123 | |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 124 | /* |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 125 | * IP7 already pending? Try to clear it by acking the timer. |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 126 | */ |
| 127 | if (c0_compare_int_pending()) { |
Al Cooper | 4f1a1eb | 2011-11-08 09:59:01 -0500 | [diff] [blame] | 128 | cnt = read_c0_count(); |
| 129 | write_c0_compare(cnt); |
| 130 | back_to_back_c0_hazard(); |
| 131 | while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) |
| 132 | if (!c0_compare_int_pending()) |
| 133 | break; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 134 | if (c0_compare_int_pending()) |
| 135 | return 0; |
| 136 | } |
| 137 | |
Atsushi Nemoto | 3a6c43a | 2007-10-23 21:55:42 +0900 | [diff] [blame] | 138 | for (delta = 0x10; delta <= 0x400000; delta <<= 1) { |
| 139 | cnt = read_c0_count(); |
| 140 | cnt += delta; |
| 141 | write_c0_compare(cnt); |
Al Cooper | 4f1a1eb | 2011-11-08 09:59:01 -0500 | [diff] [blame] | 142 | back_to_back_c0_hazard(); |
Atsushi Nemoto | 3a6c43a | 2007-10-23 21:55:42 +0900 | [diff] [blame] | 143 | if ((int)(read_c0_count() - cnt) < 0) |
| 144 | break; |
| 145 | /* increase delta if the timer was already expired */ |
| 146 | } |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 147 | |
Atsushi Nemoto | c637fec | 2007-10-23 21:51:19 +0900 | [diff] [blame] | 148 | while ((int)(read_c0_count() - cnt) <= 0) |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 149 | ; /* Wait for expiry */ |
| 150 | |
Al Cooper | 4f1a1eb | 2011-11-08 09:59:01 -0500 | [diff] [blame] | 151 | while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) |
| 152 | if (c0_compare_int_pending()) |
| 153 | break; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 154 | if (!c0_compare_int_pending()) |
| 155 | return 0; |
Al Cooper | 4f1a1eb | 2011-11-08 09:59:01 -0500 | [diff] [blame] | 156 | cnt = read_c0_count(); |
| 157 | write_c0_compare(cnt); |
| 158 | back_to_back_c0_hazard(); |
| 159 | while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) |
| 160 | if (!c0_compare_int_pending()) |
| 161 | break; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 162 | if (c0_compare_int_pending()) |
| 163 | return 0; |
| 164 | |
| 165 | /* |
| 166 | * Feels like a real count / compare timer. |
| 167 | */ |
| 168 | return 1; |
| 169 | } |
| 170 | |
Bjorn Helgaas | ec0b9d3 | 2015-07-12 18:11:38 -0500 | [diff] [blame] | 171 | unsigned int __weak get_c0_compare_int(void) |
| 172 | { |
| 173 | return MIPS_CPU_IRQ_BASE + cp0_compare_irq; |
| 174 | } |
| 175 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 176 | int r4k_clockevent_init(void) |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 177 | { |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 178 | unsigned int cpu = smp_processor_id(); |
| 179 | struct clock_event_device *cd; |
Ralf Baechle | 38760d4 | 2007-10-29 14:23:43 +0000 | [diff] [blame] | 180 | unsigned int irq; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 181 | |
Yoichi Yuasa | 22df3f5 | 2007-10-26 22:27:05 +0900 | [diff] [blame] | 182 | if (!cpu_has_counter || !mips_hpt_frequency) |
Ralf Baechle | 5aa85c9 | 2007-11-21 16:39:44 +0000 | [diff] [blame] | 183 | return -ENXIO; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 184 | |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 185 | if (!c0_compare_int_usable()) |
Ralf Baechle | 5aa85c9 | 2007-11-21 16:39:44 +0000 | [diff] [blame] | 186 | return -ENXIO; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 187 | |
Ralf Baechle | 38760d4 | 2007-10-29 14:23:43 +0000 | [diff] [blame] | 188 | /* |
| 189 | * With vectored interrupts things are getting platform specific. |
| 190 | * get_c0_compare_int is a hook to allow a platform to return the |
Bjorn Helgaas | ec0b9d3 | 2015-07-12 18:11:38 -0500 | [diff] [blame] | 191 | * interrupt number of its liking. |
Ralf Baechle | 38760d4 | 2007-10-29 14:23:43 +0000 | [diff] [blame] | 192 | */ |
Bjorn Helgaas | ec0b9d3 | 2015-07-12 18:11:38 -0500 | [diff] [blame] | 193 | irq = get_c0_compare_int(); |
Ralf Baechle | 38760d4 | 2007-10-29 14:23:43 +0000 | [diff] [blame] | 194 | |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 195 | cd = &per_cpu(mips_clockevent_device, cpu); |
| 196 | |
| 197 | cd->name = "MIPS"; |
Paul Burton | 5977d68 | 2014-02-14 09:20:15 +0000 | [diff] [blame] | 198 | cd->features = CLOCK_EVT_FEAT_ONESHOT | |
Paul Burton | d8107ef | 2014-04-15 12:05:24 +0100 | [diff] [blame] | 199 | CLOCK_EVT_FEAT_C3STOP | |
| 200 | CLOCK_EVT_FEAT_PERCPU; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 201 | |
David Daney | 4d2b112 | 2010-05-19 10:40:53 -0700 | [diff] [blame] | 202 | clockevent_set_clock(cd, mips_hpt_frequency); |
| 203 | |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 204 | /* Calculate the min / max delta */ |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 205 | cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); |
| 206 | cd->min_delta_ns = clockevent_delta2ns(0x300, cd); |
| 207 | |
| 208 | cd->rating = 300; |
| 209 | cd->irq = irq; |
Rusty Russell | 320ab2b | 2008-12-13 21:20:26 +1030 | [diff] [blame] | 210 | cd->cpumask = cpumask_of(cpu); |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 211 | cd->set_next_event = mips_next_event; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 212 | cd->event_handler = mips_event_handler; |
| 213 | |
| 214 | clockevents_register_device(cd); |
| 215 | |
Ralf Baechle | aea6863 | 2007-10-30 02:21:08 +0000 | [diff] [blame] | 216 | if (cp0_timer_irq_installed) |
Ralf Baechle | 5aa85c9 | 2007-11-21 16:39:44 +0000 | [diff] [blame] | 217 | return 0; |
Ralf Baechle | 38760d4 | 2007-10-29 14:23:43 +0000 | [diff] [blame] | 218 | |
| 219 | cp0_timer_irq_installed = 1; |
| 220 | |
Ralf Baechle | 38760d4 | 2007-10-29 14:23:43 +0000 | [diff] [blame] | 221 | setup_irq(irq, &c0_compare_irqaction); |
Ralf Baechle | 5aa85c9 | 2007-11-21 16:39:44 +0000 | [diff] [blame] | 222 | |
| 223 | return 0; |
Ralf Baechle | 42f7754 | 2007-10-18 17:48:11 +0100 | [diff] [blame] | 224 | } |
Kevin D. Kissell | 8531a35 | 2008-09-09 21:48:52 +0200 | [diff] [blame] | 225 | |