blob: 8dfe6a6e14809b992774bd7362761021b802bd15 [file] [log] [blame]
Ralf Baechle42f77542007-10-18 17:48:11 +01001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 MIPS Technologies, Inc.
7 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
8 */
9#include <linux/clockchips.h>
10#include <linux/interrupt.h>
11#include <linux/percpu.h>
Ralf Baechle631330f2009-06-19 14:05:26 +010012#include <linux/smp.h>
David Howellsca4d3e672010-10-07 14:08:54 +010013#include <linux/irq.h>
Ralf Baechle42f77542007-10-18 17:48:11 +010014
Ralf Baechle42f77542007-10-18 17:48:11 +010015#include <asm/time.h>
Kevin D. Kissell8531a352008-09-09 21:48:52 +020016#include <asm/cevt-r4k.h>
17
Ralf Baechle42f77542007-10-18 17:48:11 +010018static int mips_next_event(unsigned long delta,
Ralf Baechle70342282013-01-22 12:59:30 +010019 struct clock_event_device *evt)
Ralf Baechle42f77542007-10-18 17:48:11 +010020{
21 unsigned int cnt;
22 int res;
23
Ralf Baechle42f77542007-10-18 17:48:11 +010024 cnt = read_c0_count();
25 cnt += delta;
26 write_c0_compare(cnt);
Kevin Cernekee5878fc92010-11-23 10:26:44 -080027 res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;
Ralf Baechle42f77542007-10-18 17:48:11 +010028 return res;
29}
30
Kevin D. Kissell8531a352008-09-09 21:48:52 +020031DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
32int cp0_timer_irq_installed;
Ralf Baechle42f77542007-10-18 17:48:11 +010033
James Hogan19971c02015-01-27 21:45:47 +000034/*
35 * Possibly handle a performance counter interrupt.
36 * Return true if the timer interrupt should not be checked
37 */
38static inline int handle_perf_irq(int r2)
39{
40 /*
41 * The performance counter overflow interrupt may be shared with the
42 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
43 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
44 * and we can't reliably determine if a counter interrupt has also
45 * happened (!r2) then don't check for a timer interrupt.
46 */
47 return (cp0_perfcount_irq < 0) &&
48 perf_irq() == IRQ_HANDLED &&
49 !r2;
50}
51
Kevin D. Kissell8531a352008-09-09 21:48:52 +020052irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
Ralf Baechle42f77542007-10-18 17:48:11 +010053{
Leonid Yegoshin54dac952014-11-13 13:39:39 +000054 const int r2 = cpu_has_mips_r2_r6;
Ralf Baechle42f77542007-10-18 17:48:11 +010055 struct clock_event_device *cd;
56 int cpu = smp_processor_id();
57
58 /*
59 * Suckage alert:
60 * Before R2 of the architecture there was no way to see if a
61 * performance counter interrupt was pending, so we have to run
62 * the performance counter interrupt handler anyway.
63 */
64 if (handle_perf_irq(r2))
Ralf Baechlef0c5b892015-03-20 19:45:09 +010065 return IRQ_HANDLED;
Ralf Baechle42f77542007-10-18 17:48:11 +010066
67 /*
Ralf Baechle70342282013-01-22 12:59:30 +010068 * The same applies to performance counter interrupts. But with the
Ralf Baechle42f77542007-10-18 17:48:11 +010069 * above we now know that the reason we got here must be a timer
70 * interrupt. Being the paranoiacs we are we check anyway.
71 */
James Hogan3ba50402015-01-27 21:45:48 +000072 if (!r2 || (read_c0_cause() & CAUSEF_TI)) {
Kevin D. Kissell8531a352008-09-09 21:48:52 +020073 /* Clear Count/Compare Interrupt */
74 write_c0_compare(read_c0_compare());
Ralf Baechle42f77542007-10-18 17:48:11 +010075 cd = &per_cpu(mips_clockevent_device, cpu);
76 cd->event_handler(cd);
Ralf Baechlef0c5b892015-03-20 19:45:09 +010077
78 return IRQ_HANDLED;
Ralf Baechle42f77542007-10-18 17:48:11 +010079 }
80
Ralf Baechlef0c5b892015-03-20 19:45:09 +010081 return IRQ_NONE;
Ralf Baechle42f77542007-10-18 17:48:11 +010082}
83
Kevin D. Kissell8531a352008-09-09 21:48:52 +020084struct irqaction c0_compare_irqaction = {
Ralf Baechle42f77542007-10-18 17:48:11 +010085 .handler = c0_compare_interrupt,
James Hogan7dfe8192015-01-27 21:45:52 +000086 /*
87 * IRQF_SHARED: The timer interrupt may be shared with other interrupts
88 * such as perf counter and FDC interrupts.
89 */
90 .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED,
Ralf Baechle42f77542007-10-18 17:48:11 +010091 .name = "timer",
92};
93
Ralf Baechle42f77542007-10-18 17:48:11 +010094
Kevin D. Kissell8531a352008-09-09 21:48:52 +020095void mips_event_handler(struct clock_event_device *dev)
Ralf Baechle42f77542007-10-18 17:48:11 +010096{
97}
98
99/*
100 * FIXME: This doesn't hold for the relocated E9000 compare interrupt.
101 */
102static int c0_compare_int_pending(void)
103{
James Hoganae58d882015-01-19 12:00:55 +0000104 /* When cpu_has_mips_r2, this checks Cause.TI instead of Cause.IP7 */
David VomLehn010c1082009-12-21 17:49:22 -0800105 return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
Ralf Baechle42f77542007-10-18 17:48:11 +0100106}
107
Kevin D. Kissell8531a352008-09-09 21:48:52 +0200108/*
109 * Compare interrupt can be routed and latched outside the core,
Al Cooper4f1a1eb2011-11-08 09:59:01 -0500110 * so wait up to worst case number of cycle counter ticks for timer interrupt
111 * changes to propagate to the cause register.
Kevin D. Kissell8531a352008-09-09 21:48:52 +0200112 */
Al Cooper4f1a1eb2011-11-08 09:59:01 -0500113#define COMPARE_INT_SEEN_TICKS 50
Kevin D. Kissell8531a352008-09-09 21:48:52 +0200114
115int c0_compare_int_usable(void)
Ralf Baechle42f77542007-10-18 17:48:11 +0100116{
Atsushi Nemoto3a6c43a2007-10-23 21:55:42 +0900117 unsigned int delta;
Ralf Baechle42f77542007-10-18 17:48:11 +0100118 unsigned int cnt;
119
Sanjay Lal9843b032012-11-21 18:34:03 -0800120#ifdef CONFIG_KVM_GUEST
121 return 1;
122#endif
123
Ralf Baechle42f77542007-10-18 17:48:11 +0100124 /*
Ralf Baechle70342282013-01-22 12:59:30 +0100125 * IP7 already pending? Try to clear it by acking the timer.
Ralf Baechle42f77542007-10-18 17:48:11 +0100126 */
127 if (c0_compare_int_pending()) {
Al Cooper4f1a1eb2011-11-08 09:59:01 -0500128 cnt = read_c0_count();
129 write_c0_compare(cnt);
130 back_to_back_c0_hazard();
131 while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
132 if (!c0_compare_int_pending())
133 break;
Ralf Baechle42f77542007-10-18 17:48:11 +0100134 if (c0_compare_int_pending())
135 return 0;
136 }
137
Atsushi Nemoto3a6c43a2007-10-23 21:55:42 +0900138 for (delta = 0x10; delta <= 0x400000; delta <<= 1) {
139 cnt = read_c0_count();
140 cnt += delta;
141 write_c0_compare(cnt);
Al Cooper4f1a1eb2011-11-08 09:59:01 -0500142 back_to_back_c0_hazard();
Atsushi Nemoto3a6c43a2007-10-23 21:55:42 +0900143 if ((int)(read_c0_count() - cnt) < 0)
144 break;
145 /* increase delta if the timer was already expired */
146 }
Ralf Baechle42f77542007-10-18 17:48:11 +0100147
Atsushi Nemotoc637fec2007-10-23 21:51:19 +0900148 while ((int)(read_c0_count() - cnt) <= 0)
Ralf Baechle42f77542007-10-18 17:48:11 +0100149 ; /* Wait for expiry */
150
Al Cooper4f1a1eb2011-11-08 09:59:01 -0500151 while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
152 if (c0_compare_int_pending())
153 break;
Ralf Baechle42f77542007-10-18 17:48:11 +0100154 if (!c0_compare_int_pending())
155 return 0;
Al Cooper4f1a1eb2011-11-08 09:59:01 -0500156 cnt = read_c0_count();
157 write_c0_compare(cnt);
158 back_to_back_c0_hazard();
159 while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
160 if (!c0_compare_int_pending())
161 break;
Ralf Baechle42f77542007-10-18 17:48:11 +0100162 if (c0_compare_int_pending())
163 return 0;
164
165 /*
166 * Feels like a real count / compare timer.
167 */
168 return 1;
169}
170
Bjorn Helgaasec0b9d32015-07-12 18:11:38 -0500171unsigned int __weak get_c0_compare_int(void)
172{
173 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
174}
175
Paul Gortmaker078a55f2013-06-18 13:38:59 +0000176int r4k_clockevent_init(void)
Ralf Baechle42f77542007-10-18 17:48:11 +0100177{
Ralf Baechle42f77542007-10-18 17:48:11 +0100178 unsigned int cpu = smp_processor_id();
179 struct clock_event_device *cd;
Ralf Baechle38760d42007-10-29 14:23:43 +0000180 unsigned int irq;
Ralf Baechle42f77542007-10-18 17:48:11 +0100181
Yoichi Yuasa22df3f52007-10-26 22:27:05 +0900182 if (!cpu_has_counter || !mips_hpt_frequency)
Ralf Baechle5aa85c92007-11-21 16:39:44 +0000183 return -ENXIO;
Ralf Baechle42f77542007-10-18 17:48:11 +0100184
Ralf Baechle42f77542007-10-18 17:48:11 +0100185 if (!c0_compare_int_usable())
Ralf Baechle5aa85c92007-11-21 16:39:44 +0000186 return -ENXIO;
Ralf Baechle42f77542007-10-18 17:48:11 +0100187
Ralf Baechle38760d42007-10-29 14:23:43 +0000188 /*
189 * With vectored interrupts things are getting platform specific.
190 * get_c0_compare_int is a hook to allow a platform to return the
Bjorn Helgaasec0b9d32015-07-12 18:11:38 -0500191 * interrupt number of its liking.
Ralf Baechle38760d42007-10-29 14:23:43 +0000192 */
Bjorn Helgaasec0b9d32015-07-12 18:11:38 -0500193 irq = get_c0_compare_int();
Ralf Baechle38760d42007-10-29 14:23:43 +0000194
Ralf Baechle42f77542007-10-18 17:48:11 +0100195 cd = &per_cpu(mips_clockevent_device, cpu);
196
197 cd->name = "MIPS";
Paul Burton5977d682014-02-14 09:20:15 +0000198 cd->features = CLOCK_EVT_FEAT_ONESHOT |
Paul Burtond8107ef2014-04-15 12:05:24 +0100199 CLOCK_EVT_FEAT_C3STOP |
200 CLOCK_EVT_FEAT_PERCPU;
Ralf Baechle42f77542007-10-18 17:48:11 +0100201
David Daney4d2b1122010-05-19 10:40:53 -0700202 clockevent_set_clock(cd, mips_hpt_frequency);
203
Ralf Baechle42f77542007-10-18 17:48:11 +0100204 /* Calculate the min / max delta */
Ralf Baechle42f77542007-10-18 17:48:11 +0100205 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
206 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
207
208 cd->rating = 300;
209 cd->irq = irq;
Rusty Russell320ab2b2008-12-13 21:20:26 +1030210 cd->cpumask = cpumask_of(cpu);
Ralf Baechle42f77542007-10-18 17:48:11 +0100211 cd->set_next_event = mips_next_event;
Ralf Baechle42f77542007-10-18 17:48:11 +0100212 cd->event_handler = mips_event_handler;
213
214 clockevents_register_device(cd);
215
Ralf Baechleaea68632007-10-30 02:21:08 +0000216 if (cp0_timer_irq_installed)
Ralf Baechle5aa85c92007-11-21 16:39:44 +0000217 return 0;
Ralf Baechle38760d42007-10-29 14:23:43 +0000218
219 cp0_timer_irq_installed = 1;
220
Ralf Baechle38760d42007-10-29 14:23:43 +0000221 setup_irq(irq, &c0_compare_irqaction);
Ralf Baechle5aa85c92007-11-21 16:39:44 +0000222
223 return 0;
Ralf Baechle42f77542007-10-18 17:48:11 +0100224}
Kevin D. Kissell8531a352008-09-09 21:48:52 +0200225