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Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Russell Kingf8f98a92005-06-08 15:28:24 +01002/*
3 * linux/arch/arm/lib/copypage-xscale.S
4 *
5 * Copyright (C) 1995-2005 Russell King
6 *
Russell Kingf8f98a92005-06-08 15:28:24 +01007 * This handles the mini data cache, as found on SA11x0 and XScale
8 * processors. When we copy a user page page, we map it in such a way
9 * that accesses to this page will not touch the main data cache, but
10 * will be cached in the mini data cache. This prevents us thrashing
11 * the main data cache on page faults.
12 */
13#include <linux/init.h>
14#include <linux/mm.h>
Russell King063b0a42008-10-31 15:08:35 +000015#include <linux/highmem.h>
Russell Kingf8f98a92005-06-08 15:28:24 +010016
Russell Kingf8f98a92005-06-08 15:28:24 +010017#include <asm/tlbflush.h>
Richard Purdie1c9d3df2006-12-30 16:08:50 +010018#include <asm/cacheflush.h>
Russell Kingf8f98a92005-06-08 15:28:24 +010019
Russell King1b2e2b732006-08-21 17:06:38 +010020#include "mm.h"
21
Russell Kingf8f98a92005-06-08 15:28:24 +010022#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
Russell Kingbb30f362008-09-06 20:04:59 +010023 L_PTE_MT_MINICACHE)
Russell Kingf8f98a92005-06-08 15:28:24 +010024
Thomas Gleixnerbd31b852009-07-03 08:44:46 -050025static DEFINE_RAW_SPINLOCK(minicache_lock);
Russell Kingf8f98a92005-06-08 15:28:24 +010026
27/*
Russell King063b0a42008-10-31 15:08:35 +000028 * XScale mini-dcache optimised copy_user_highpage
Russell Kingf8f98a92005-06-08 15:28:24 +010029 *
30 * We flush the destination cache lines just before we write the data into the
31 * corresponding address. Since the Dcache is read-allocate, this removes the
32 * Dcache aliasing issue. The writes will be forwarded to the write buffer,
33 * and merged as appropriate.
34 */
Nicolas Pitreb99afae2018-11-07 17:49:00 +010035static void mc_copy_user_page(void *from, void *to)
Russell Kingf8f98a92005-06-08 15:28:24 +010036{
Nicolas Pitreb99afae2018-11-07 17:49:00 +010037 int tmp;
38
Russell Kingf8f98a92005-06-08 15:28:24 +010039 /*
40 * Strangely enough, best performance is achieved
41 * when prefetching destination as well. (NP)
42 */
Nicolas Pitreb99afae2018-11-07 17:49:00 +010043 asm volatile ("\
Arnd Bergmannc7b68042019-08-09 18:33:19 +020044.arch xscale \n\
Nicolas Pitreb99afae2018-11-07 17:49:00 +010045 pld [%0, #0] \n\
46 pld [%0, #32] \n\
47 pld [%1, #0] \n\
48 pld [%1, #32] \n\
491: pld [%0, #64] \n\
50 pld [%0, #96] \n\
51 pld [%1, #64] \n\
52 pld [%1, #96] \n\
Nicolas Pitrebc2eca92018-11-09 04:26:39 +0100532: ldrd r2, r3, [%0], #8 \n\
54 ldrd r4, r5, [%0], #8 \n\
Nicolas Pitreb99afae2018-11-07 17:49:00 +010055 mov ip, %1 \n\
Nicolas Pitrebc2eca92018-11-09 04:26:39 +010056 strd r2, r3, [%1], #8 \n\
57 ldrd r2, r3, [%0], #8 \n\
58 strd r4, r5, [%1], #8 \n\
59 ldrd r4, r5, [%0], #8 \n\
60 strd r2, r3, [%1], #8 \n\
61 strd r4, r5, [%1], #8 \n\
Russell Kingf8f98a92005-06-08 15:28:24 +010062 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
Nicolas Pitrebc2eca92018-11-09 04:26:39 +010063 ldrd r2, r3, [%0], #8 \n\
Russell Kingf8f98a92005-06-08 15:28:24 +010064 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
Nicolas Pitrebc2eca92018-11-09 04:26:39 +010065 ldrd r4, r5, [%0], #8 \n\
Nicolas Pitreb99afae2018-11-07 17:49:00 +010066 mov ip, %1 \n\
Nicolas Pitrebc2eca92018-11-09 04:26:39 +010067 strd r2, r3, [%1], #8 \n\
68 ldrd r2, r3, [%0], #8 \n\
69 strd r4, r5, [%1], #8 \n\
70 ldrd r4, r5, [%0], #8 \n\
71 strd r2, r3, [%1], #8 \n\
72 strd r4, r5, [%1], #8 \n\
Russell Kingf8f98a92005-06-08 15:28:24 +010073 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
Nicolas Pitreb99afae2018-11-07 17:49:00 +010074 subs %2, %2, #1 \n\
Russell Kingf8f98a92005-06-08 15:28:24 +010075 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
76 bgt 1b \n\
Nicolas Pitreb99afae2018-11-07 17:49:00 +010077 beq 2b "
78 : "+&r" (from), "+&r" (to), "=&r" (tmp)
79 : "2" (PAGE_SIZE / 64 - 1)
80 : "r2", "r3", "r4", "r5", "ip");
Russell Kingf8f98a92005-06-08 15:28:24 +010081}
82
Russell King063b0a42008-10-31 15:08:35 +000083void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
Russell Kingf00a75c2009-10-05 15:17:45 +010084 unsigned long vaddr, struct vm_area_struct *vma)
Russell Kingf8f98a92005-06-08 15:28:24 +010085{
Cong Wang5472e862011-11-25 23:14:15 +080086 void *kto = kmap_atomic(to);
Richard Purdie1c9d3df2006-12-30 16:08:50 +010087
Catalin Marinasc0177802010-09-13 15:57:36 +010088 if (!test_and_set_bit(PG_dcache_clean, &from->flags))
Huang Yingcb9f7532018-04-05 16:24:39 -070089 __flush_dcache_page(page_mapping_file(from), from);
Richard Purdie1c9d3df2006-12-30 16:08:50 +010090
Thomas Gleixnerbd31b852009-07-03 08:44:46 -050091 raw_spin_lock(&minicache_lock);
Russell Kingf8f98a92005-06-08 15:28:24 +010092
Russell King67ece142011-07-02 15:20:44 +010093 set_top_pte(COPYPAGE_MINICACHE, mk_pte(from, minicache_pgprot));
Russell Kingf8f98a92005-06-08 15:28:24 +010094
95 mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
96
Thomas Gleixnerbd31b852009-07-03 08:44:46 -050097 raw_spin_unlock(&minicache_lock);
Russell King063b0a42008-10-31 15:08:35 +000098
Cong Wang5472e862011-11-25 23:14:15 +080099 kunmap_atomic(kto);
Russell Kingf8f98a92005-06-08 15:28:24 +0100100}
101
102/*
103 * XScale optimised clear_user_page
104 */
Russell King303c6442008-10-31 16:32:19 +0000105void
106xscale_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
Russell Kingf8f98a92005-06-08 15:28:24 +0100107{
Cong Wang5472e862011-11-25 23:14:15 +0800108 void *ptr, *kaddr = kmap_atomic(page);
Arnd Bergmannc7b68042019-08-09 18:33:19 +0200109 asm volatile("\
110.arch xscale \n\
111 mov r1, %2 \n\
Russell Kingf8f98a92005-06-08 15:28:24 +0100112 mov r2, #0 \n\
113 mov r3, #0 \n\
Russell King303c6442008-10-31 16:32:19 +00001141: mov ip, %0 \n\
Nicolas Pitrebc2eca92018-11-09 04:26:39 +0100115 strd r2, r3, [%0], #8 \n\
116 strd r2, r3, [%0], #8 \n\
117 strd r2, r3, [%0], #8 \n\
118 strd r2, r3, [%0], #8 \n\
Russell Kingf8f98a92005-06-08 15:28:24 +0100119 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
120 subs r1, r1, #1 \n\
121 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
Russell King303c6442008-10-31 16:32:19 +0000122 bne 1b"
Nicolas Pitre43ae2862008-11-04 02:42:27 -0500123 : "=r" (ptr)
124 : "0" (kaddr), "I" (PAGE_SIZE / 32)
Russell King303c6442008-10-31 16:32:19 +0000125 : "r1", "r2", "r3", "ip");
Cong Wang5472e862011-11-25 23:14:15 +0800126 kunmap_atomic(kaddr);
Russell Kingf8f98a92005-06-08 15:28:24 +0100127}
128
129struct cpu_user_fns xscale_mc_user_fns __initdata = {
Russell King303c6442008-10-31 16:32:19 +0000130 .cpu_clear_user_highpage = xscale_mc_clear_user_highpage,
Russell King063b0a42008-10-31 15:08:35 +0000131 .cpu_copy_user_highpage = xscale_mc_copy_user_highpage,
Russell Kingf8f98a92005-06-08 15:28:24 +0100132};