blob: 5559c943f03f973137432de01f1972aec58f94b6 [file] [log] [blame]
Thomas Gleixner1802d0b2019-05-27 08:55:21 +02001// SPDX-License-Identifier: GPL-2.0-only
Florian Fainelli7f646e92014-05-23 17:40:53 -07002/*
3 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
4 *
Doug Berger49aa6ef2017-09-18 17:59:58 -07005 * Copyright (C) 2014-2017 Broadcom
Florian Fainelli7f646e92014-05-23 17:40:53 -07006 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/init.h>
11#include <linux/slab.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
Kevin Cernekee05f12752014-11-06 22:44:20 -080014#include <linux/spinlock.h>
Florian Fainelli7f646e92014-05-23 17:40:53 -070015#include <linux/of.h>
16#include <linux/of_irq.h>
17#include <linux/of_address.h>
Florian Fainelli7f646e92014-05-23 17:40:53 -070018#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21#include <linux/irqdomain.h>
22#include <linux/irqchip.h>
23#include <linux/irqchip/chained_irq.h>
24
Doug Bergerc0ca7262017-09-18 18:00:00 -070025struct brcmstb_intc_init_params {
26 irq_flow_handler_t handler;
27 int cpu_status;
28 int cpu_clear;
29 int cpu_mask_status;
30 int cpu_mask_set;
31 int cpu_mask_clear;
32};
33
34/* Register offsets in the L2 latched interrupt controller */
35static const struct brcmstb_intc_init_params l2_edge_intc_init = {
36 .handler = handle_edge_irq,
37 .cpu_status = 0x00,
38 .cpu_clear = 0x08,
39 .cpu_mask_status = 0x0c,
40 .cpu_mask_set = 0x10,
41 .cpu_mask_clear = 0x14
42};
43
44/* Register offsets in the L2 level interrupt controller */
45static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
46 .handler = handle_level_irq,
47 .cpu_status = 0x00,
48 .cpu_clear = -1, /* Register not present */
49 .cpu_mask_status = 0x04,
50 .cpu_mask_set = 0x08,
51 .cpu_mask_clear = 0x0C
52};
Florian Fainelli7f646e92014-05-23 17:40:53 -070053
54/* L2 intc private data structure */
55struct brcmstb_l2_intc_data {
Florian Fainelli7f646e92014-05-23 17:40:53 -070056 struct irq_domain *domain;
Doug Berger49aa6ef2017-09-18 17:59:58 -070057 struct irq_chip_generic *gc;
Doug Berger8480ca42017-09-18 17:59:59 -070058 int status_offset;
59 int mask_offset;
Florian Fainelli7f646e92014-05-23 17:40:53 -070060 bool can_wake;
61 u32 saved_mask; /* for suspend/resume */
62};
63
Doug Berger49aa6ef2017-09-18 17:59:58 -070064/**
65 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
66 * @d: irq_data
67 *
68 * Chip has separate enable/disable registers instead of a single mask
69 * register and pending interrupt is acknowledged by setting a bit.
70 *
71 * Note: This function is generic and could easily be added to the
72 * generic irqchip implementation if there ever becomes a will to do so.
73 * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
74 *
75 * e.g.: https://patchwork.kernel.org/patch/9831047/
76 */
77static void brcmstb_l2_mask_and_ack(struct irq_data *d)
78{
79 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
80 struct irq_chip_type *ct = irq_data_get_chip_type(d);
81 u32 mask = d->mask;
82
83 irq_gc_lock(gc);
84 irq_reg_writel(gc, mask, ct->regs.disable);
85 *ct->mask_cache &= ~mask;
86 irq_reg_writel(gc, mask, ct->regs.ack);
87 irq_gc_unlock(gc);
88}
89
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +020090static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
Florian Fainelli7f646e92014-05-23 17:40:53 -070091{
92 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
93 struct irq_chip *chip = irq_desc_get_chip(desc);
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +020094 unsigned int irq;
Florian Fainelli7f646e92014-05-23 17:40:53 -070095 u32 status;
96
97 chained_irq_enter(chip, desc);
98
Doug Berger8480ca42017-09-18 17:59:59 -070099 status = irq_reg_readl(b->gc, b->status_offset) &
100 ~(irq_reg_readl(b->gc, b->mask_offset));
Florian Fainelli7f646e92014-05-23 17:40:53 -0700101
102 if (status == 0) {
Kevin Cernekee05f12752014-11-06 22:44:20 -0800103 raw_spin_lock(&desc->lock);
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200104 handle_bad_irq(desc);
Kevin Cernekee05f12752014-11-06 22:44:20 -0800105 raw_spin_unlock(&desc->lock);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700106 goto out;
107 }
108
109 do {
110 irq = ffs(status) - 1;
Florian Fainelli7f646e92014-05-23 17:40:53 -0700111 status &= ~(1 << irq);
Marc Zyngier046a6ee2021-05-04 17:42:18 +0100112 generic_handle_domain_irq(b->domain, irq);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700113 } while (status);
114out:
115 chained_irq_exit(chip, desc);
116}
117
118static void brcmstb_l2_intc_suspend(struct irq_data *d)
119{
120 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
Doug Berger8480ca42017-09-18 17:59:59 -0700121 struct irq_chip_type *ct = irq_data_get_chip_type(d);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700122 struct brcmstb_l2_intc_data *b = gc->private;
Doug Berger33517882019-02-20 14:15:28 -0800123 unsigned long flags;
Florian Fainelli7f646e92014-05-23 17:40:53 -0700124
Doug Berger33517882019-02-20 14:15:28 -0800125 irq_gc_lock_irqsave(gc, flags);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700126 /* Save the current mask */
Doug Berger8480ca42017-09-18 17:59:59 -0700127 b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700128
129 if (b->can_wake) {
130 /* Program the wakeup mask */
Doug Berger8480ca42017-09-18 17:59:59 -0700131 irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
132 irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700133 }
Doug Berger33517882019-02-20 14:15:28 -0800134 irq_gc_unlock_irqrestore(gc, flags);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700135}
136
137static void brcmstb_l2_intc_resume(struct irq_data *d)
138{
139 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
Doug Berger8480ca42017-09-18 17:59:59 -0700140 struct irq_chip_type *ct = irq_data_get_chip_type(d);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700141 struct brcmstb_l2_intc_data *b = gc->private;
Doug Berger33517882019-02-20 14:15:28 -0800142 unsigned long flags;
Florian Fainelli7f646e92014-05-23 17:40:53 -0700143
Doug Berger33517882019-02-20 14:15:28 -0800144 irq_gc_lock_irqsave(gc, flags);
Doug Bergerc0ca7262017-09-18 18:00:00 -0700145 if (ct->chip.irq_ack) {
Doug Berger8480ca42017-09-18 17:59:59 -0700146 /* Clear unmasked non-wakeup interrupts */
147 irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
148 ct->regs.ack);
149 }
Florian Fainelli7f646e92014-05-23 17:40:53 -0700150
151 /* Restore the saved mask */
Doug Berger8480ca42017-09-18 17:59:59 -0700152 irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
153 irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
Doug Berger33517882019-02-20 14:15:28 -0800154 irq_gc_unlock_irqrestore(gc, flags);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700155}
156
Ben Dooks2ae9add2016-06-08 19:02:20 +0100157static int __init brcmstb_l2_intc_of_init(struct device_node *np,
Doug Bergerc0ca7262017-09-18 18:00:00 -0700158 struct device_node *parent,
159 const struct brcmstb_intc_init_params
160 *init_params)
Florian Fainelli7f646e92014-05-23 17:40:53 -0700161{
162 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
Florian Fainelli94debe02022-12-16 15:09:33 -0800163 unsigned int set = 0;
Florian Fainelli7f646e92014-05-23 17:40:53 -0700164 struct brcmstb_l2_intc_data *data;
Florian Fainelli7f646e92014-05-23 17:40:53 -0700165 struct irq_chip_type *ct;
166 int ret;
Kevin Cernekee1abbdba2014-11-06 22:44:29 -0800167 unsigned int flags;
Doug Berger49aa6ef2017-09-18 17:59:58 -0700168 int parent_irq;
169 void __iomem *base;
Florian Fainelli7f646e92014-05-23 17:40:53 -0700170
171 data = kzalloc(sizeof(*data), GFP_KERNEL);
172 if (!data)
173 return -ENOMEM;
174
Doug Berger49aa6ef2017-09-18 17:59:58 -0700175 base = of_iomap(np, 0);
176 if (!base) {
Florian Fainelli7f646e92014-05-23 17:40:53 -0700177 pr_err("failed to remap intc L2 registers\n");
178 ret = -ENOMEM;
179 goto out_free;
180 }
181
182 /* Disable all interrupts by default */
Doug Bergerc0ca7262017-09-18 18:00:00 -0700183 writel(0xffffffff, base + init_params->cpu_mask_set);
Brian Norrisc9ae71e2014-12-25 09:49:02 -0800184
185 /* Wakeup interrupts may be retained from S5 (cold boot) */
186 data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
Doug Bergerc0ca7262017-09-18 18:00:00 -0700187 if (!data->can_wake && (init_params->cpu_clear >= 0))
188 writel(0xffffffff, base + init_params->cpu_clear);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700189
Doug Berger49aa6ef2017-09-18 17:59:58 -0700190 parent_irq = irq_of_parse_and_map(np, 0);
191 if (!parent_irq) {
Florian Fainelli7f646e92014-05-23 17:40:53 -0700192 pr_err("failed to find parent interrupt\n");
Dmitry Torokhovd99ba442014-11-14 14:16:42 -0800193 ret = -EINVAL;
Florian Fainelli7f646e92014-05-23 17:40:53 -0700194 goto out_unmap;
195 }
196
197 data->domain = irq_domain_add_linear(np, 32,
198 &irq_generic_chip_ops, NULL);
199 if (!data->domain) {
200 ret = -ENOMEM;
201 goto out_unmap;
202 }
203
Kevin Cernekee1abbdba2014-11-06 22:44:29 -0800204 /* MIPS chips strapped for BE will automagically configure the
205 * peripheral registers for CPU-native byte order.
206 */
207 flags = 0;
208 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
209 flags |= IRQ_GC_BE_IO;
210
Florian Fainelli94debe02022-12-16 15:09:33 -0800211 if (init_params->handler == handle_level_irq)
212 set |= IRQ_LEVEL;
213
Florian Fainelli7f646e92014-05-23 17:40:53 -0700214 /* Allocate a single Generic IRQ chip for this node */
215 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
Florian Fainelli94debe02022-12-16 15:09:33 -0800216 np->full_name, init_params->handler, clr, set, flags);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700217 if (ret) {
218 pr_err("failed to allocate generic irq chip\n");
219 goto out_free_domain;
220 }
221
222 /* Set the IRQ chaining logic */
Doug Berger49aa6ef2017-09-18 17:59:58 -0700223 irq_set_chained_handler_and_data(parent_irq,
Thomas Gleixnerf286c172015-06-21 21:10:52 +0200224 brcmstb_l2_intc_irq_handle, data);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700225
Doug Berger49aa6ef2017-09-18 17:59:58 -0700226 data->gc = irq_get_domain_generic_chip(data->domain, 0);
227 data->gc->reg_base = base;
228 data->gc->private = data;
Doug Bergerc0ca7262017-09-18 18:00:00 -0700229 data->status_offset = init_params->cpu_status;
230 data->mask_offset = init_params->cpu_mask_status;
Doug Berger8480ca42017-09-18 17:59:59 -0700231
Doug Berger49aa6ef2017-09-18 17:59:58 -0700232 ct = data->gc->chip_types;
Florian Fainelli7f646e92014-05-23 17:40:53 -0700233
Doug Bergerc0ca7262017-09-18 18:00:00 -0700234 if (init_params->cpu_clear >= 0) {
235 ct->regs.ack = init_params->cpu_clear;
236 ct->chip.irq_ack = irq_gc_ack_set_bit;
237 ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
238 } else {
239 /* No Ack - but still slightly more efficient to define this */
240 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
241 }
Florian Fainelli7f646e92014-05-23 17:40:53 -0700242
243 ct->chip.irq_mask = irq_gc_mask_disable_reg;
Doug Bergerc0ca7262017-09-18 18:00:00 -0700244 ct->regs.disable = init_params->cpu_mask_set;
245 ct->regs.mask = init_params->cpu_mask_status;
Florian Fainelli7f646e92014-05-23 17:40:53 -0700246
247 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
Doug Bergerc0ca7262017-09-18 18:00:00 -0700248 ct->regs.enable = init_params->cpu_mask_clear;
Florian Fainelli7f646e92014-05-23 17:40:53 -0700249
250 ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
251 ct->chip.irq_resume = brcmstb_l2_intc_resume;
Florian Fainellic017d212017-07-27 15:38:17 -0700252 ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;
Florian Fainelli7f646e92014-05-23 17:40:53 -0700253
Brian Norrisc9ae71e2014-12-25 09:49:02 -0800254 if (data->can_wake) {
Florian Fainelli7f646e92014-05-23 17:40:53 -0700255 /* This IRQ chip can wake the system, set all child interrupts
256 * in wake_enabled mask
257 */
Doug Berger49aa6ef2017-09-18 17:59:58 -0700258 data->gc->wake_enabled = 0xffffffff;
Florian Fainelli7f646e92014-05-23 17:40:53 -0700259 ct->chip.irq_set_wake = irq_gc_set_wake;
Justin Chenc8d8d6f2020-07-09 15:30:12 -0700260 enable_irq_wake(parent_irq);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700261 }
262
Florian Fainelli082ce272019-03-20 12:39:19 -0700263 pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);
264
Florian Fainelli7f646e92014-05-23 17:40:53 -0700265 return 0;
266
267out_free_domain:
268 irq_domain_remove(data->domain);
269out_unmap:
Doug Berger49aa6ef2017-09-18 17:59:58 -0700270 iounmap(base);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700271out_free:
272 kfree(data);
273 return ret;
274}
Doug Bergerc0ca7262017-09-18 18:00:00 -0700275
YueHaibingdc3173c2019-03-20 22:22:20 +0800276static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
Doug Bergerc0ca7262017-09-18 18:00:00 -0700277 struct device_node *parent)
278{
279 return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
280}
Doug Bergerc0ca7262017-09-18 18:00:00 -0700281
YueHaibingdc3173c2019-03-20 22:22:20 +0800282static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
Doug Bergerc0ca7262017-09-18 18:00:00 -0700283 struct device_node *parent)
284{
285 return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
286}
Florian Fainelli51d9db52021-10-20 11:48:54 -0700287
288IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2)
289IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init)
290IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init)
291IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init)
292IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init)
293IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2)
294MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller");
295MODULE_LICENSE("GPL v2");