Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2016 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include <linux/firmware.h> |
| 25 | #include <drm/drmP.h> |
| 26 | #include "amdgpu.h" |
| 27 | #include "amdgpu_vcn.h" |
Christian König | 9096d6e | 2018-01-12 21:57:53 +0100 | [diff] [blame] | 28 | #include "soc15.h" |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 29 | #include "soc15d.h" |
| 30 | #include "soc15_common.h" |
| 31 | |
Feifei Xu | b1ebd7c0 | 2017-11-27 17:57:30 +0800 | [diff] [blame] | 32 | #include "vcn/vcn_1_0_offset.h" |
| 33 | #include "vcn/vcn_1_0_sh_mask.h" |
Feifei Xu | 75199b8 | 2017-11-15 18:09:33 +0800 | [diff] [blame] | 34 | #include "hdp/hdp_4_0_offset.h" |
Feifei Xu | 95c1f7a | 2017-11-27 17:16:06 +0800 | [diff] [blame] | 35 | #include "mmhub/mmhub_9_1_offset.h" |
| 36 | #include "mmhub/mmhub_9_1_sh_mask.h" |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 37 | |
| 38 | static int vcn_v1_0_start(struct amdgpu_device *adev); |
| 39 | static int vcn_v1_0_stop(struct amdgpu_device *adev); |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 40 | static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 41 | static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); |
Leo Liu | a319f44 | 2016-12-28 13:22:18 -0500 | [diff] [blame] | 42 | static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 43 | |
| 44 | /** |
| 45 | * vcn_v1_0_early_init - set function pointers |
| 46 | * |
| 47 | * @handle: amdgpu_device pointer |
| 48 | * |
| 49 | * Set ring and irq function pointers |
| 50 | */ |
| 51 | static int vcn_v1_0_early_init(void *handle) |
| 52 | { |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 53 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 54 | |
Leo Liu | 101c6fe | 2017-02-21 15:21:18 -0500 | [diff] [blame] | 55 | adev->vcn.num_enc_rings = 2; |
| 56 | |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 57 | vcn_v1_0_set_dec_ring_funcs(adev); |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 58 | vcn_v1_0_set_enc_ring_funcs(adev); |
Leo Liu | a319f44 | 2016-12-28 13:22:18 -0500 | [diff] [blame] | 59 | vcn_v1_0_set_irq_funcs(adev); |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 60 | |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 61 | return 0; |
| 62 | } |
| 63 | |
| 64 | /** |
| 65 | * vcn_v1_0_sw_init - sw init for VCN block |
| 66 | * |
| 67 | * @handle: amdgpu_device pointer |
| 68 | * |
| 69 | * Load firmware and sw initialization |
| 70 | */ |
| 71 | static int vcn_v1_0_sw_init(void *handle) |
| 72 | { |
Leo Liu | a4bf608b | 2016-12-28 12:16:48 -0500 | [diff] [blame] | 73 | struct amdgpu_ring *ring; |
Leo Liu | 101c6fe | 2017-02-21 15:21:18 -0500 | [diff] [blame] | 74 | int i, r; |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 75 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 76 | |
Leo Liu | 9b25711 | 2017-02-21 15:19:18 -0500 | [diff] [blame] | 77 | /* VCN DEC TRAP */ |
Oak Zeng | 3760f76 | 2018-03-08 16:44:47 -0500 | [diff] [blame] | 78 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 124, &adev->vcn.irq); |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 79 | if (r) |
| 80 | return r; |
| 81 | |
Leo Liu | 9b25711 | 2017-02-21 15:19:18 -0500 | [diff] [blame] | 82 | /* VCN ENC TRAP */ |
| 83 | for (i = 0; i < adev->vcn.num_enc_rings; ++i) { |
Oak Zeng | 3760f76 | 2018-03-08 16:44:47 -0500 | [diff] [blame] | 84 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + 119, |
Leo Liu | 9b25711 | 2017-02-21 15:19:18 -0500 | [diff] [blame] | 85 | &adev->vcn.irq); |
| 86 | if (r) |
| 87 | return r; |
| 88 | } |
| 89 | |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 90 | r = amdgpu_vcn_sw_init(adev); |
| 91 | if (r) |
| 92 | return r; |
| 93 | |
| 94 | r = amdgpu_vcn_resume(adev); |
| 95 | if (r) |
| 96 | return r; |
| 97 | |
Leo Liu | a4bf608b | 2016-12-28 12:16:48 -0500 | [diff] [blame] | 98 | ring = &adev->vcn.ring_dec; |
| 99 | sprintf(ring->name, "vcn_dec"); |
| 100 | r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); |
Leo Liu | 101c6fe | 2017-02-21 15:21:18 -0500 | [diff] [blame] | 101 | if (r) |
| 102 | return r; |
| 103 | |
| 104 | for (i = 0; i < adev->vcn.num_enc_rings; ++i) { |
| 105 | ring = &adev->vcn.ring_enc[i]; |
| 106 | sprintf(ring->name, "vcn_enc%d", i); |
| 107 | r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0); |
| 108 | if (r) |
| 109 | return r; |
| 110 | } |
Leo Liu | a4bf608b | 2016-12-28 12:16:48 -0500 | [diff] [blame] | 111 | |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 112 | return r; |
| 113 | } |
| 114 | |
| 115 | /** |
| 116 | * vcn_v1_0_sw_fini - sw fini for VCN block |
| 117 | * |
| 118 | * @handle: amdgpu_device pointer |
| 119 | * |
| 120 | * VCN suspend and free up sw allocation |
| 121 | */ |
| 122 | static int vcn_v1_0_sw_fini(void *handle) |
| 123 | { |
| 124 | int r; |
| 125 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 126 | |
| 127 | r = amdgpu_vcn_suspend(adev); |
| 128 | if (r) |
| 129 | return r; |
| 130 | |
| 131 | r = amdgpu_vcn_sw_fini(adev); |
| 132 | |
| 133 | return r; |
| 134 | } |
| 135 | |
| 136 | /** |
| 137 | * vcn_v1_0_hw_init - start and test VCN block |
| 138 | * |
| 139 | * @handle: amdgpu_device pointer |
| 140 | * |
| 141 | * Initialize the hardware, boot up the VCPU and do some testing |
| 142 | */ |
| 143 | static int vcn_v1_0_hw_init(void *handle) |
| 144 | { |
| 145 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 146 | struct amdgpu_ring *ring = &adev->vcn.ring_dec; |
Leo Liu | c3bd304 | 2017-02-21 10:38:42 -0500 | [diff] [blame] | 147 | int i, r; |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 148 | |
| 149 | r = vcn_v1_0_start(adev); |
| 150 | if (r) |
| 151 | goto done; |
| 152 | |
| 153 | ring->ready = true; |
| 154 | r = amdgpu_ring_test_ring(ring); |
| 155 | if (r) { |
| 156 | ring->ready = false; |
| 157 | goto done; |
| 158 | } |
| 159 | |
Leo Liu | c3bd304 | 2017-02-21 10:38:42 -0500 | [diff] [blame] | 160 | for (i = 0; i < adev->vcn.num_enc_rings; ++i) { |
| 161 | ring = &adev->vcn.ring_enc[i]; |
| 162 | ring->ready = true; |
| 163 | r = amdgpu_ring_test_ring(ring); |
| 164 | if (r) { |
| 165 | ring->ready = false; |
| 166 | goto done; |
| 167 | } |
| 168 | } |
| 169 | |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 170 | done: |
| 171 | if (!r) |
Leo Liu | c3bd304 | 2017-02-21 10:38:42 -0500 | [diff] [blame] | 172 | DRM_INFO("VCN decode and encode initialized successfully.\n"); |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 173 | |
| 174 | return r; |
| 175 | } |
| 176 | |
| 177 | /** |
| 178 | * vcn_v1_0_hw_fini - stop the hardware block |
| 179 | * |
| 180 | * @handle: amdgpu_device pointer |
| 181 | * |
| 182 | * Stop the VCN block, mark ring as not ready any more |
| 183 | */ |
| 184 | static int vcn_v1_0_hw_fini(void *handle) |
| 185 | { |
| 186 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 187 | struct amdgpu_ring *ring = &adev->vcn.ring_dec; |
| 188 | int r; |
| 189 | |
| 190 | r = vcn_v1_0_stop(adev); |
| 191 | if (r) |
| 192 | return r; |
| 193 | |
| 194 | ring->ready = false; |
| 195 | |
| 196 | return 0; |
| 197 | } |
| 198 | |
| 199 | /** |
| 200 | * vcn_v1_0_suspend - suspend VCN block |
| 201 | * |
| 202 | * @handle: amdgpu_device pointer |
| 203 | * |
| 204 | * HW fini and suspend VCN block |
| 205 | */ |
| 206 | static int vcn_v1_0_suspend(void *handle) |
| 207 | { |
| 208 | int r; |
| 209 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 210 | |
| 211 | r = vcn_v1_0_hw_fini(adev); |
| 212 | if (r) |
| 213 | return r; |
| 214 | |
| 215 | r = amdgpu_vcn_suspend(adev); |
| 216 | |
| 217 | return r; |
| 218 | } |
| 219 | |
| 220 | /** |
| 221 | * vcn_v1_0_resume - resume VCN block |
| 222 | * |
| 223 | * @handle: amdgpu_device pointer |
| 224 | * |
| 225 | * Resume firmware and hw init VCN block |
| 226 | */ |
| 227 | static int vcn_v1_0_resume(void *handle) |
| 228 | { |
| 229 | int r; |
| 230 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 231 | |
| 232 | r = amdgpu_vcn_resume(adev); |
| 233 | if (r) |
| 234 | return r; |
| 235 | |
| 236 | r = vcn_v1_0_hw_init(adev); |
| 237 | |
| 238 | return r; |
| 239 | } |
| 240 | |
| 241 | /** |
| 242 | * vcn_v1_0_mc_resume - memory controller programming |
| 243 | * |
| 244 | * @adev: amdgpu_device pointer |
| 245 | * |
| 246 | * Let the VCN memory controller know it's offsets |
| 247 | */ |
| 248 | static void vcn_v1_0_mc_resume(struct amdgpu_device *adev) |
| 249 | { |
Leo Liu | 8143965 | 2017-02-07 16:11:20 -0500 | [diff] [blame] | 250 | uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 251 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 252 | WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 253 | lower_32_bits(adev->vcn.gpu_addr)); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 254 | WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 255 | upper_32_bits(adev->vcn.gpu_addr)); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 256 | WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, |
Leo Liu | 62a9f37 | 2017-03-29 14:15:15 -0400 | [diff] [blame] | 257 | AMDGPU_UVD_FIRMWARE_OFFSET >> 3); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 258 | WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 259 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 260 | WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, |
Leo Liu | 8143965 | 2017-02-07 16:11:20 -0500 | [diff] [blame] | 261 | lower_32_bits(adev->vcn.gpu_addr + size)); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 262 | WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, |
Leo Liu | 8143965 | 2017-02-07 16:11:20 -0500 | [diff] [blame] | 263 | upper_32_bits(adev->vcn.gpu_addr + size)); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 264 | WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); |
| 265 | WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE); |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 266 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 267 | WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, |
Leo Liu | 8143965 | 2017-02-07 16:11:20 -0500 | [diff] [blame] | 268 | lower_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE)); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 269 | WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, |
Leo Liu | 8143965 | 2017-02-07 16:11:20 -0500 | [diff] [blame] | 270 | upper_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE)); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 271 | WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); |
| 272 | WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, |
Leo Liu | 8143965 | 2017-02-07 16:11:20 -0500 | [diff] [blame] | 273 | AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40)); |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 274 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 275 | WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 276 | adev->gfx.config.gb_addr_config); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 277 | WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 278 | adev->gfx.config.gb_addr_config); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 279 | WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 280 | adev->gfx.config.gb_addr_config); |
| 281 | } |
| 282 | |
| 283 | /** |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 284 | * vcn_v1_0_disable_clock_gating - disable VCN clock gating |
| 285 | * |
| 286 | * @adev: amdgpu_device pointer |
| 287 | * @sw: enable SW clock gating |
| 288 | * |
| 289 | * Disable clock gating for VCN block |
| 290 | */ |
| 291 | static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev, bool sw) |
| 292 | { |
| 293 | uint32_t data; |
| 294 | |
| 295 | /* JPEG disable CGC */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 296 | data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 297 | |
| 298 | if (sw) |
| 299 | data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; |
| 300 | else |
| 301 | data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; |
| 302 | |
| 303 | data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; |
| 304 | data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 305 | WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 306 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 307 | data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 308 | data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 309 | WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 310 | |
| 311 | /* UVD disable CGC */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 312 | data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 313 | if (sw) |
| 314 | data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; |
| 315 | else |
| 316 | data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; |
| 317 | |
| 318 | data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; |
| 319 | data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 320 | WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 321 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 322 | data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 323 | data &= ~(UVD_CGC_GATE__SYS_MASK |
| 324 | | UVD_CGC_GATE__UDEC_MASK |
| 325 | | UVD_CGC_GATE__MPEG2_MASK |
| 326 | | UVD_CGC_GATE__REGS_MASK |
| 327 | | UVD_CGC_GATE__RBC_MASK |
| 328 | | UVD_CGC_GATE__LMI_MC_MASK |
| 329 | | UVD_CGC_GATE__LMI_UMC_MASK |
| 330 | | UVD_CGC_GATE__IDCT_MASK |
| 331 | | UVD_CGC_GATE__MPRD_MASK |
| 332 | | UVD_CGC_GATE__MPC_MASK |
| 333 | | UVD_CGC_GATE__LBSI_MASK |
| 334 | | UVD_CGC_GATE__LRBBM_MASK |
| 335 | | UVD_CGC_GATE__UDEC_RE_MASK |
| 336 | | UVD_CGC_GATE__UDEC_CM_MASK |
| 337 | | UVD_CGC_GATE__UDEC_IT_MASK |
| 338 | | UVD_CGC_GATE__UDEC_DB_MASK |
| 339 | | UVD_CGC_GATE__UDEC_MP_MASK |
| 340 | | UVD_CGC_GATE__WCB_MASK |
| 341 | | UVD_CGC_GATE__VCPU_MASK |
| 342 | | UVD_CGC_GATE__SCPU_MASK); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 343 | WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 344 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 345 | data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 346 | data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
| 347 | | UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
| 348 | | UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
| 349 | | UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
| 350 | | UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
| 351 | | UVD_CGC_CTRL__SYS_MODE_MASK |
| 352 | | UVD_CGC_CTRL__UDEC_MODE_MASK |
| 353 | | UVD_CGC_CTRL__MPEG2_MODE_MASK |
| 354 | | UVD_CGC_CTRL__REGS_MODE_MASK |
| 355 | | UVD_CGC_CTRL__RBC_MODE_MASK |
| 356 | | UVD_CGC_CTRL__LMI_MC_MODE_MASK |
| 357 | | UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
| 358 | | UVD_CGC_CTRL__IDCT_MODE_MASK |
| 359 | | UVD_CGC_CTRL__MPRD_MODE_MASK |
| 360 | | UVD_CGC_CTRL__MPC_MODE_MASK |
| 361 | | UVD_CGC_CTRL__LBSI_MODE_MASK |
| 362 | | UVD_CGC_CTRL__LRBBM_MODE_MASK |
| 363 | | UVD_CGC_CTRL__WCB_MODE_MASK |
| 364 | | UVD_CGC_CTRL__VCPU_MODE_MASK |
| 365 | | UVD_CGC_CTRL__SCPU_MODE_MASK); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 366 | WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 367 | |
| 368 | /* turn on */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 369 | data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 370 | data |= (UVD_SUVD_CGC_GATE__SRE_MASK |
| 371 | | UVD_SUVD_CGC_GATE__SIT_MASK |
| 372 | | UVD_SUVD_CGC_GATE__SMP_MASK |
| 373 | | UVD_SUVD_CGC_GATE__SCM_MASK |
| 374 | | UVD_SUVD_CGC_GATE__SDB_MASK |
| 375 | | UVD_SUVD_CGC_GATE__SRE_H264_MASK |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 376 | | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
| 377 | | UVD_SUVD_CGC_GATE__SIT_H264_MASK |
| 378 | | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
| 379 | | UVD_SUVD_CGC_GATE__SCM_H264_MASK |
| 380 | | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
| 381 | | UVD_SUVD_CGC_GATE__SDB_H264_MASK |
| 382 | | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK |
| 383 | | UVD_SUVD_CGC_GATE__SCLR_MASK |
| 384 | | UVD_SUVD_CGC_GATE__UVD_SC_MASK |
| 385 | | UVD_SUVD_CGC_GATE__ENT_MASK |
| 386 | | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK |
| 387 | | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK |
| 388 | | UVD_SUVD_CGC_GATE__SITE_MASK |
| 389 | | UVD_SUVD_CGC_GATE__SRE_VP9_MASK |
| 390 | | UVD_SUVD_CGC_GATE__SCM_VP9_MASK |
| 391 | | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK |
| 392 | | UVD_SUVD_CGC_GATE__SDB_VP9_MASK |
| 393 | | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 394 | WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 395 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 396 | data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 397 | data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
| 398 | | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
| 399 | | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
| 400 | | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
| 401 | | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK |
| 402 | | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK |
| 403 | | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK |
| 404 | | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK |
| 405 | | UVD_SUVD_CGC_CTRL__IME_MODE_MASK |
| 406 | | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 407 | WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 408 | } |
| 409 | |
| 410 | /** |
| 411 | * vcn_v1_0_enable_clock_gating - enable VCN clock gating |
| 412 | * |
| 413 | * @adev: amdgpu_device pointer |
| 414 | * @sw: enable SW clock gating |
| 415 | * |
| 416 | * Enable clock gating for VCN block |
| 417 | */ |
| 418 | static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev, bool sw) |
| 419 | { |
| 420 | uint32_t data = 0; |
| 421 | |
| 422 | /* enable JPEG CGC */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 423 | data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 424 | if (sw) |
| 425 | data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; |
| 426 | else |
| 427 | data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; |
| 428 | data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; |
| 429 | data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 430 | WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 431 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 432 | data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 433 | data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 434 | WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 435 | |
| 436 | /* enable UVD CGC */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 437 | data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 438 | if (sw) |
| 439 | data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; |
| 440 | else |
| 441 | data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; |
| 442 | data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; |
| 443 | data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 444 | WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 445 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 446 | data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 447 | data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
| 448 | | UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
| 449 | | UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
| 450 | | UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
| 451 | | UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
| 452 | | UVD_CGC_CTRL__SYS_MODE_MASK |
| 453 | | UVD_CGC_CTRL__UDEC_MODE_MASK |
| 454 | | UVD_CGC_CTRL__MPEG2_MODE_MASK |
| 455 | | UVD_CGC_CTRL__REGS_MODE_MASK |
| 456 | | UVD_CGC_CTRL__RBC_MODE_MASK |
| 457 | | UVD_CGC_CTRL__LMI_MC_MODE_MASK |
| 458 | | UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
| 459 | | UVD_CGC_CTRL__IDCT_MODE_MASK |
| 460 | | UVD_CGC_CTRL__MPRD_MODE_MASK |
| 461 | | UVD_CGC_CTRL__MPC_MODE_MASK |
| 462 | | UVD_CGC_CTRL__LBSI_MODE_MASK |
| 463 | | UVD_CGC_CTRL__LRBBM_MODE_MASK |
| 464 | | UVD_CGC_CTRL__WCB_MODE_MASK |
| 465 | | UVD_CGC_CTRL__VCPU_MODE_MASK |
| 466 | | UVD_CGC_CTRL__SCPU_MODE_MASK); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 467 | WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 468 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 469 | data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 470 | data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
| 471 | | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
| 472 | | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
| 473 | | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
| 474 | | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK |
| 475 | | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK |
| 476 | | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK |
| 477 | | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK |
| 478 | | UVD_SUVD_CGC_CTRL__IME_MODE_MASK |
| 479 | | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 480 | WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 481 | } |
| 482 | |
| 483 | /** |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 484 | * vcn_v1_0_start - start VCN block |
| 485 | * |
| 486 | * @adev: amdgpu_device pointer |
| 487 | * |
| 488 | * Setup and start the VCN block |
| 489 | */ |
| 490 | static int vcn_v1_0_start(struct amdgpu_device *adev) |
| 491 | { |
Leo Liu | a4bf608b | 2016-12-28 12:16:48 -0500 | [diff] [blame] | 492 | struct amdgpu_ring *ring = &adev->vcn.ring_dec; |
| 493 | uint32_t rb_bufsz, tmp; |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 494 | uint32_t lmi_swap_cntl; |
| 495 | int i, j, r; |
| 496 | |
| 497 | /* disable byte swapping */ |
| 498 | lmi_swap_cntl = 0; |
| 499 | |
| 500 | vcn_v1_0_mc_resume(adev); |
| 501 | |
| 502 | /* disable clock gating */ |
Huang Rui | d2a3387 | 2017-04-20 10:18:13 +0800 | [diff] [blame] | 503 | vcn_v1_0_disable_clock_gating(adev, true); |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 504 | |
| 505 | /* disable interupt */ |
| 506 | WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, |
| 507 | ~UVD_MASTINT_EN__VCPU_EN_MASK); |
| 508 | |
| 509 | /* stall UMC and register bus before resetting VCPU */ |
| 510 | WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), |
| 511 | UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, |
| 512 | ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); |
| 513 | mdelay(1); |
| 514 | |
| 515 | /* put LMI, VCPU, RBC etc... into reset */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 516 | WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 517 | UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | |
| 518 | UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | |
| 519 | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | |
| 520 | UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | |
| 521 | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | |
| 522 | UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | |
| 523 | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | |
| 524 | UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); |
| 525 | mdelay(5); |
| 526 | |
| 527 | /* initialize VCN memory controller */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 528 | WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 529 | (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | |
| 530 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | |
| 531 | UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | |
| 532 | UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | |
| 533 | UVD_LMI_CTRL__REQ_MODE_MASK | |
| 534 | 0x00100000L); |
| 535 | |
| 536 | #ifdef __BIG_ENDIAN |
| 537 | /* swap (8 in 32) RB and IB */ |
| 538 | lmi_swap_cntl = 0xa; |
| 539 | #endif |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 540 | WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 541 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 542 | WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040); |
| 543 | WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0); |
| 544 | WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040); |
| 545 | WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0); |
| 546 | WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0); |
| 547 | WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88); |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 548 | |
| 549 | /* take all subblocks out of reset, except VCPU */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 550 | WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 551 | UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); |
| 552 | mdelay(5); |
| 553 | |
| 554 | /* enable VCPU clock */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 555 | WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 556 | UVD_VCPU_CNTL__CLK_EN_MASK); |
| 557 | |
| 558 | /* enable UMC */ |
| 559 | WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, |
| 560 | ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); |
| 561 | |
| 562 | /* boot up the VCPU */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 563 | WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0); |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 564 | mdelay(10); |
| 565 | |
| 566 | for (i = 0; i < 10; ++i) { |
| 567 | uint32_t status; |
| 568 | |
| 569 | for (j = 0; j < 100; ++j) { |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 570 | status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 571 | if (status & 2) |
| 572 | break; |
| 573 | mdelay(10); |
| 574 | } |
| 575 | r = 0; |
| 576 | if (status & 2) |
| 577 | break; |
| 578 | |
| 579 | DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); |
| 580 | WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), |
| 581 | UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, |
| 582 | ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); |
| 583 | mdelay(10); |
| 584 | WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, |
| 585 | ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); |
| 586 | mdelay(10); |
| 587 | r = -1; |
| 588 | } |
| 589 | |
| 590 | if (r) { |
| 591 | DRM_ERROR("VCN decode not responding, giving up!!!\n"); |
| 592 | return r; |
| 593 | } |
| 594 | /* enable master interrupt */ |
| 595 | WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), |
| 596 | (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), |
| 597 | ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); |
| 598 | |
| 599 | /* clear the bit 4 of VCN_STATUS */ |
| 600 | WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, |
| 601 | ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); |
| 602 | |
Leo Liu | a4bf608b | 2016-12-28 12:16:48 -0500 | [diff] [blame] | 603 | /* force RBC into idle state */ |
| 604 | rb_bufsz = order_base_2(ring->ring_size); |
| 605 | tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); |
| 606 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); |
| 607 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); |
| 608 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); |
| 609 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); |
| 610 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 611 | WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); |
Leo Liu | a4bf608b | 2016-12-28 12:16:48 -0500 | [diff] [blame] | 612 | |
| 613 | /* set the write pointer delay */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 614 | WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); |
Leo Liu | a4bf608b | 2016-12-28 12:16:48 -0500 | [diff] [blame] | 615 | |
| 616 | /* set the wb address */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 617 | WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, |
Leo Liu | a4bf608b | 2016-12-28 12:16:48 -0500 | [diff] [blame] | 618 | (upper_32_bits(ring->gpu_addr) >> 2)); |
| 619 | |
| 620 | /* programm the RB_BASE for ring buffer */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 621 | WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, |
Leo Liu | a4bf608b | 2016-12-28 12:16:48 -0500 | [diff] [blame] | 622 | lower_32_bits(ring->gpu_addr)); |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 623 | WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, |
Leo Liu | a4bf608b | 2016-12-28 12:16:48 -0500 | [diff] [blame] | 624 | upper_32_bits(ring->gpu_addr)); |
| 625 | |
| 626 | /* Initialize the ring buffer's read and write pointers */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 627 | WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); |
Leo Liu | a4bf608b | 2016-12-28 12:16:48 -0500 | [diff] [blame] | 628 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 629 | ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); |
| 630 | WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, |
Leo Liu | a4bf608b | 2016-12-28 12:16:48 -0500 | [diff] [blame] | 631 | lower_32_bits(ring->wptr)); |
| 632 | |
| 633 | WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, |
| 634 | ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); |
| 635 | |
Leo Liu | 101c6fe | 2017-02-21 15:21:18 -0500 | [diff] [blame] | 636 | ring = &adev->vcn.ring_enc[0]; |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 637 | WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); |
| 638 | WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); |
| 639 | WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); |
| 640 | WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); |
| 641 | WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); |
Leo Liu | 101c6fe | 2017-02-21 15:21:18 -0500 | [diff] [blame] | 642 | |
| 643 | ring = &adev->vcn.ring_enc[1]; |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 644 | WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); |
| 645 | WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); |
| 646 | WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); |
| 647 | WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); |
| 648 | WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); |
Leo Liu | 101c6fe | 2017-02-21 15:21:18 -0500 | [diff] [blame] | 649 | |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 650 | return 0; |
| 651 | } |
| 652 | |
| 653 | /** |
| 654 | * vcn_v1_0_stop - stop VCN block |
| 655 | * |
| 656 | * @adev: amdgpu_device pointer |
| 657 | * |
| 658 | * stop the VCN block |
| 659 | */ |
| 660 | static int vcn_v1_0_stop(struct amdgpu_device *adev) |
| 661 | { |
Leo Liu | a4bf608b | 2016-12-28 12:16:48 -0500 | [diff] [blame] | 662 | /* force RBC into idle state */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 663 | WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101); |
Leo Liu | a4bf608b | 2016-12-28 12:16:48 -0500 | [diff] [blame] | 664 | |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 665 | /* Stall UMC and register bus before resetting VCPU */ |
| 666 | WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), |
| 667 | UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, |
| 668 | ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); |
| 669 | mdelay(1); |
| 670 | |
| 671 | /* put VCPU into reset */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 672 | WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 673 | UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); |
| 674 | mdelay(5); |
| 675 | |
| 676 | /* disable VCPU clock */ |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 677 | WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0); |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 678 | |
| 679 | /* Unstall UMC and register bus */ |
| 680 | WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, |
| 681 | ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); |
| 682 | |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 683 | /* enable clock gating */ |
Huang Rui | d2a3387 | 2017-04-20 10:18:13 +0800 | [diff] [blame] | 684 | vcn_v1_0_enable_clock_gating(adev, true); |
Huang Rui | fb4d56f | 2017-04-20 09:42:41 +0800 | [diff] [blame] | 685 | |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 686 | return 0; |
| 687 | } |
| 688 | |
| 689 | static int vcn_v1_0_set_clockgating_state(void *handle, |
| 690 | enum amd_clockgating_state state) |
| 691 | { |
| 692 | /* needed for driver unload*/ |
| 693 | return 0; |
| 694 | } |
| 695 | |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 696 | /** |
| 697 | * vcn_v1_0_dec_ring_get_rptr - get read pointer |
| 698 | * |
| 699 | * @ring: amdgpu_ring pointer |
| 700 | * |
| 701 | * Returns the current hardware read pointer |
| 702 | */ |
| 703 | static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) |
| 704 | { |
| 705 | struct amdgpu_device *adev = ring->adev; |
| 706 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 707 | return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 708 | } |
| 709 | |
| 710 | /** |
| 711 | * vcn_v1_0_dec_ring_get_wptr - get write pointer |
| 712 | * |
| 713 | * @ring: amdgpu_ring pointer |
| 714 | * |
| 715 | * Returns the current hardware write pointer |
| 716 | */ |
| 717 | static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) |
| 718 | { |
| 719 | struct amdgpu_device *adev = ring->adev; |
| 720 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 721 | return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 722 | } |
| 723 | |
| 724 | /** |
| 725 | * vcn_v1_0_dec_ring_set_wptr - set write pointer |
| 726 | * |
| 727 | * @ring: amdgpu_ring pointer |
| 728 | * |
| 729 | * Commits the write pointer to the hardware |
| 730 | */ |
| 731 | static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) |
| 732 | { |
| 733 | struct amdgpu_device *adev = ring->adev; |
| 734 | |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 735 | WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 736 | } |
| 737 | |
| 738 | /** |
Leo Liu | e7501c3 | 2017-02-07 11:52:00 -0500 | [diff] [blame] | 739 | * vcn_v1_0_dec_ring_insert_start - insert a start command |
| 740 | * |
| 741 | * @ring: amdgpu_ring pointer |
| 742 | * |
| 743 | * Write a start command to the ring. |
| 744 | */ |
| 745 | static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) |
| 746 | { |
Shaoyun Liu | cd29253 | 2017-11-29 13:51:32 -0500 | [diff] [blame] | 747 | struct amdgpu_device *adev = ring->adev; |
| 748 | |
Leo Liu | e7501c3 | 2017-02-07 11:52:00 -0500 | [diff] [blame] | 749 | amdgpu_ring_write(ring, |
| 750 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); |
| 751 | amdgpu_ring_write(ring, 0); |
| 752 | amdgpu_ring_write(ring, |
| 753 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); |
Leo Liu | 3639f7d | 2017-02-15 10:16:25 -0500 | [diff] [blame] | 754 | amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); |
Leo Liu | e7501c3 | 2017-02-07 11:52:00 -0500 | [diff] [blame] | 755 | } |
| 756 | |
| 757 | /** |
Leo Liu | a4c424c | 2017-01-25 14:37:41 -0500 | [diff] [blame] | 758 | * vcn_v1_0_dec_ring_insert_end - insert a end command |
| 759 | * |
| 760 | * @ring: amdgpu_ring pointer |
| 761 | * |
| 762 | * Write a end command to the ring. |
| 763 | */ |
| 764 | static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) |
| 765 | { |
Shaoyun Liu | cd29253 | 2017-11-29 13:51:32 -0500 | [diff] [blame] | 766 | struct amdgpu_device *adev = ring->adev; |
| 767 | |
Leo Liu | a4c424c | 2017-01-25 14:37:41 -0500 | [diff] [blame] | 768 | amdgpu_ring_write(ring, |
| 769 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); |
Leo Liu | 3639f7d | 2017-02-15 10:16:25 -0500 | [diff] [blame] | 770 | amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); |
Leo Liu | a4c424c | 2017-01-25 14:37:41 -0500 | [diff] [blame] | 771 | } |
| 772 | |
| 773 | /** |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 774 | * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command |
| 775 | * |
| 776 | * @ring: amdgpu_ring pointer |
| 777 | * @fence: fence to emit |
| 778 | * |
| 779 | * Write a fence and a trap command to the ring. |
| 780 | */ |
| 781 | static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, |
| 782 | unsigned flags) |
| 783 | { |
Shaoyun Liu | cd29253 | 2017-11-29 13:51:32 -0500 | [diff] [blame] | 784 | struct amdgpu_device *adev = ring->adev; |
| 785 | |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 786 | WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); |
| 787 | |
| 788 | amdgpu_ring_write(ring, |
| 789 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); |
| 790 | amdgpu_ring_write(ring, seq); |
| 791 | amdgpu_ring_write(ring, |
| 792 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); |
| 793 | amdgpu_ring_write(ring, addr & 0xffffffff); |
| 794 | amdgpu_ring_write(ring, |
| 795 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); |
| 796 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); |
| 797 | amdgpu_ring_write(ring, |
| 798 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); |
Leo Liu | 3639f7d | 2017-02-15 10:16:25 -0500 | [diff] [blame] | 799 | amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 800 | |
| 801 | amdgpu_ring_write(ring, |
| 802 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); |
| 803 | amdgpu_ring_write(ring, 0); |
| 804 | amdgpu_ring_write(ring, |
| 805 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); |
| 806 | amdgpu_ring_write(ring, 0); |
| 807 | amdgpu_ring_write(ring, |
| 808 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); |
Leo Liu | 3639f7d | 2017-02-15 10:16:25 -0500 | [diff] [blame] | 809 | amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 810 | } |
| 811 | |
| 812 | /** |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 813 | * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer |
| 814 | * |
| 815 | * @ring: amdgpu_ring pointer |
| 816 | * @ib: indirect buffer to execute |
| 817 | * |
| 818 | * Write ring commands to execute the indirect buffer |
| 819 | */ |
| 820 | static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, |
| 821 | struct amdgpu_ib *ib, |
Christian König | c4f46f2 | 2017-12-18 17:08:25 +0100 | [diff] [blame] | 822 | unsigned vmid, bool ctx_switch) |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 823 | { |
Shaoyun Liu | cd29253 | 2017-11-29 13:51:32 -0500 | [diff] [blame] | 824 | struct amdgpu_device *adev = ring->adev; |
| 825 | |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 826 | amdgpu_ring_write(ring, |
| 827 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); |
Christian König | c4f46f2 | 2017-12-18 17:08:25 +0100 | [diff] [blame] | 828 | amdgpu_ring_write(ring, vmid); |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 829 | |
| 830 | amdgpu_ring_write(ring, |
| 831 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); |
| 832 | amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); |
| 833 | amdgpu_ring_write(ring, |
| 834 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); |
| 835 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); |
| 836 | amdgpu_ring_write(ring, |
| 837 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); |
| 838 | amdgpu_ring_write(ring, ib->length_dw); |
| 839 | } |
| 840 | |
Christian König | 2b124b0 | 2018-01-26 14:31:07 +0100 | [diff] [blame] | 841 | static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, |
| 842 | uint32_t reg, uint32_t val, |
| 843 | uint32_t mask) |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 844 | { |
Shaoyun Liu | cd29253 | 2017-11-29 13:51:32 -0500 | [diff] [blame] | 845 | struct amdgpu_device *adev = ring->adev; |
| 846 | |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 847 | amdgpu_ring_write(ring, |
| 848 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); |
Christian König | 2b124b0 | 2018-01-26 14:31:07 +0100 | [diff] [blame] | 849 | amdgpu_ring_write(ring, reg << 2); |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 850 | amdgpu_ring_write(ring, |
| 851 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); |
Christian König | 2b124b0 | 2018-01-26 14:31:07 +0100 | [diff] [blame] | 852 | amdgpu_ring_write(ring, val); |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 853 | amdgpu_ring_write(ring, |
| 854 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); |
| 855 | amdgpu_ring_write(ring, mask); |
| 856 | amdgpu_ring_write(ring, |
| 857 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); |
Leo Liu | 3639f7d | 2017-02-15 10:16:25 -0500 | [diff] [blame] | 858 | amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 859 | } |
| 860 | |
| 861 | static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, |
Christian König | c633c00 | 2018-02-04 10:32:35 +0100 | [diff] [blame] | 862 | unsigned vmid, uint64_t pd_addr) |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 863 | { |
| 864 | struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; |
Christian König | 3de676d | 2017-11-29 13:27:26 +0100 | [diff] [blame] | 865 | uint32_t data0, data1, mask; |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 866 | |
Christian König | c633c00 | 2018-02-04 10:32:35 +0100 | [diff] [blame] | 867 | pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 868 | |
Christian König | 9096d6e | 2018-01-12 21:57:53 +0100 | [diff] [blame] | 869 | /* wait for register write */ |
Christian König | 2b124b0 | 2018-01-26 14:31:07 +0100 | [diff] [blame] | 870 | data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 871 | data1 = lower_32_bits(pd_addr); |
| 872 | mask = 0xffffffff; |
Christian König | 2b124b0 | 2018-01-26 14:31:07 +0100 | [diff] [blame] | 873 | vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 874 | } |
| 875 | |
Christian König | 4383736 | 2018-01-26 14:20:55 +0100 | [diff] [blame] | 876 | static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, |
| 877 | uint32_t reg, uint32_t val) |
| 878 | { |
| 879 | struct amdgpu_device *adev = ring->adev; |
| 880 | |
| 881 | amdgpu_ring_write(ring, |
| 882 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); |
| 883 | amdgpu_ring_write(ring, reg << 2); |
| 884 | amdgpu_ring_write(ring, |
| 885 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); |
| 886 | amdgpu_ring_write(ring, val); |
| 887 | amdgpu_ring_write(ring, |
| 888 | PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); |
| 889 | amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); |
| 890 | } |
| 891 | |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 892 | /** |
| 893 | * vcn_v1_0_enc_ring_get_rptr - get enc read pointer |
| 894 | * |
| 895 | * @ring: amdgpu_ring pointer |
| 896 | * |
| 897 | * Returns the current hardware enc read pointer |
| 898 | */ |
| 899 | static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) |
| 900 | { |
| 901 | struct amdgpu_device *adev = ring->adev; |
| 902 | |
| 903 | if (ring == &adev->vcn.ring_enc[0]) |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 904 | return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 905 | else |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 906 | return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 907 | } |
| 908 | |
| 909 | /** |
| 910 | * vcn_v1_0_enc_ring_get_wptr - get enc write pointer |
| 911 | * |
| 912 | * @ring: amdgpu_ring pointer |
| 913 | * |
| 914 | * Returns the current hardware enc write pointer |
| 915 | */ |
| 916 | static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) |
| 917 | { |
| 918 | struct amdgpu_device *adev = ring->adev; |
| 919 | |
| 920 | if (ring == &adev->vcn.ring_enc[0]) |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 921 | return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 922 | else |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 923 | return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 924 | } |
| 925 | |
| 926 | /** |
| 927 | * vcn_v1_0_enc_ring_set_wptr - set enc write pointer |
| 928 | * |
| 929 | * @ring: amdgpu_ring pointer |
| 930 | * |
| 931 | * Commits the enc write pointer to the hardware |
| 932 | */ |
| 933 | static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) |
| 934 | { |
| 935 | struct amdgpu_device *adev = ring->adev; |
| 936 | |
| 937 | if (ring == &adev->vcn.ring_enc[0]) |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 938 | WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 939 | lower_32_bits(ring->wptr)); |
| 940 | else |
Tom St Denis | 0ad6f0d | 2017-06-12 13:50:53 -0400 | [diff] [blame] | 941 | WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 942 | lower_32_bits(ring->wptr)); |
| 943 | } |
| 944 | |
| 945 | /** |
| 946 | * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command |
| 947 | * |
| 948 | * @ring: amdgpu_ring pointer |
| 949 | * @fence: fence to emit |
| 950 | * |
| 951 | * Write enc a fence and a trap command to the ring. |
| 952 | */ |
| 953 | static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, |
| 954 | u64 seq, unsigned flags) |
| 955 | { |
| 956 | WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); |
| 957 | |
| 958 | amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); |
| 959 | amdgpu_ring_write(ring, addr); |
| 960 | amdgpu_ring_write(ring, upper_32_bits(addr)); |
| 961 | amdgpu_ring_write(ring, seq); |
| 962 | amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); |
| 963 | } |
| 964 | |
| 965 | static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) |
| 966 | { |
| 967 | amdgpu_ring_write(ring, VCN_ENC_CMD_END); |
| 968 | } |
| 969 | |
| 970 | /** |
| 971 | * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer |
| 972 | * |
| 973 | * @ring: amdgpu_ring pointer |
| 974 | * @ib: indirect buffer to execute |
| 975 | * |
| 976 | * Write enc ring commands to execute the indirect buffer |
| 977 | */ |
| 978 | static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, |
Christian König | c4f46f2 | 2017-12-18 17:08:25 +0100 | [diff] [blame] | 979 | struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch) |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 980 | { |
| 981 | amdgpu_ring_write(ring, VCN_ENC_CMD_IB); |
Christian König | c4f46f2 | 2017-12-18 17:08:25 +0100 | [diff] [blame] | 982 | amdgpu_ring_write(ring, vmid); |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 983 | amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); |
| 984 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); |
| 985 | amdgpu_ring_write(ring, ib->length_dw); |
| 986 | } |
| 987 | |
Christian König | 2b124b0 | 2018-01-26 14:31:07 +0100 | [diff] [blame] | 988 | static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, |
| 989 | uint32_t reg, uint32_t val, |
| 990 | uint32_t mask) |
| 991 | { |
| 992 | amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); |
| 993 | amdgpu_ring_write(ring, reg << 2); |
| 994 | amdgpu_ring_write(ring, mask); |
| 995 | amdgpu_ring_write(ring, val); |
| 996 | } |
| 997 | |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 998 | static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, |
Christian König | c633c00 | 2018-02-04 10:32:35 +0100 | [diff] [blame] | 999 | unsigned int vmid, uint64_t pd_addr) |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 1000 | { |
| 1001 | struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 1002 | |
Christian König | c633c00 | 2018-02-04 10:32:35 +0100 | [diff] [blame] | 1003 | pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 1004 | |
Christian König | 9096d6e | 2018-01-12 21:57:53 +0100 | [diff] [blame] | 1005 | /* wait for reg writes */ |
Christian König | 2b124b0 | 2018-01-26 14:31:07 +0100 | [diff] [blame] | 1006 | vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, |
| 1007 | lower_32_bits(pd_addr), 0xffffffff); |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 1008 | } |
| 1009 | |
Christian König | 0b5f83a | 2018-01-12 16:35:16 +0100 | [diff] [blame] | 1010 | static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, |
| 1011 | uint32_t reg, uint32_t val) |
| 1012 | { |
| 1013 | amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); |
| 1014 | amdgpu_ring_write(ring, reg << 2); |
| 1015 | amdgpu_ring_write(ring, val); |
| 1016 | } |
| 1017 | |
Leo Liu | a319f44 | 2016-12-28 13:22:18 -0500 | [diff] [blame] | 1018 | static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, |
| 1019 | struct amdgpu_irq_src *source, |
| 1020 | unsigned type, |
| 1021 | enum amdgpu_interrupt_state state) |
| 1022 | { |
| 1023 | return 0; |
| 1024 | } |
| 1025 | |
| 1026 | static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, |
| 1027 | struct amdgpu_irq_src *source, |
| 1028 | struct amdgpu_iv_entry *entry) |
| 1029 | { |
| 1030 | DRM_DEBUG("IH: VCN TRAP\n"); |
| 1031 | |
Leo Liu | 9b25711 | 2017-02-21 15:19:18 -0500 | [diff] [blame] | 1032 | switch (entry->src_id) { |
| 1033 | case 124: |
| 1034 | amdgpu_fence_process(&adev->vcn.ring_dec); |
| 1035 | break; |
| 1036 | case 119: |
| 1037 | amdgpu_fence_process(&adev->vcn.ring_enc[0]); |
| 1038 | break; |
| 1039 | case 120: |
| 1040 | amdgpu_fence_process(&adev->vcn.ring_enc[1]); |
| 1041 | break; |
| 1042 | default: |
| 1043 | DRM_ERROR("Unhandled interrupt: %d %d\n", |
| 1044 | entry->src_id, entry->src_data[0]); |
| 1045 | break; |
| 1046 | } |
Leo Liu | a319f44 | 2016-12-28 13:22:18 -0500 | [diff] [blame] | 1047 | |
| 1048 | return 0; |
| 1049 | } |
| 1050 | |
Shaoyun Liu | 946a4d5 | 2017-11-28 17:01:21 -0500 | [diff] [blame] | 1051 | static void vcn_v1_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) |
| 1052 | { |
| 1053 | int i; |
| 1054 | struct amdgpu_device *adev = ring->adev; |
| 1055 | |
| 1056 | for (i = 0; i < count; i++) |
| 1057 | amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); |
| 1058 | |
| 1059 | } |
| 1060 | |
| 1061 | |
Leo Liu | 88b5af7 | 2016-12-28 11:57:38 -0500 | [diff] [blame] | 1062 | static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { |
| 1063 | .name = "vcn_v1_0", |
| 1064 | .early_init = vcn_v1_0_early_init, |
| 1065 | .late_init = NULL, |
| 1066 | .sw_init = vcn_v1_0_sw_init, |
| 1067 | .sw_fini = vcn_v1_0_sw_fini, |
| 1068 | .hw_init = vcn_v1_0_hw_init, |
| 1069 | .hw_fini = vcn_v1_0_hw_fini, |
| 1070 | .suspend = vcn_v1_0_suspend, |
| 1071 | .resume = vcn_v1_0_resume, |
| 1072 | .is_idle = NULL /* vcn_v1_0_is_idle */, |
| 1073 | .wait_for_idle = NULL /* vcn_v1_0_wait_for_idle */, |
| 1074 | .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, |
| 1075 | .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, |
| 1076 | .soft_reset = NULL /* vcn_v1_0_soft_reset */, |
| 1077 | .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, |
| 1078 | .set_clockgating_state = vcn_v1_0_set_clockgating_state, |
| 1079 | .set_powergating_state = NULL /* vcn_v1_0_set_powergating_state */, |
| 1080 | }; |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 1081 | |
| 1082 | static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { |
| 1083 | .type = AMDGPU_RING_TYPE_VCN_DEC, |
| 1084 | .align_mask = 0xf, |
Shaoyun Liu | 946a4d5 | 2017-11-28 17:01:21 -0500 | [diff] [blame] | 1085 | .nop = PACKET0(0x81ff, 0), |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 1086 | .support_64bit_ptrs = false, |
Hawking Zhang | 04e5f2a | 2017-05-15 17:03:02 +0800 | [diff] [blame] | 1087 | .vmhub = AMDGPU_MMHUB, |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 1088 | .get_rptr = vcn_v1_0_dec_ring_get_rptr, |
| 1089 | .get_wptr = vcn_v1_0_dec_ring_get_wptr, |
| 1090 | .set_wptr = vcn_v1_0_dec_ring_set_wptr, |
| 1091 | .emit_frame_size = |
Christian König | 2ee150c | 2018-01-19 15:19:16 +0100 | [diff] [blame] | 1092 | 6 + 6 + /* hdp invalidate / flush */ |
Christian König | f732b6b | 2018-01-26 15:00:43 +0100 | [diff] [blame] | 1093 | SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + |
| 1094 | SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + |
| 1095 | 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */ |
Leo Liu | e7501c3 | 2017-02-07 11:52:00 -0500 | [diff] [blame] | 1096 | 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ |
Leo Liu | a4c424c | 2017-01-25 14:37:41 -0500 | [diff] [blame] | 1097 | 6, |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 1098 | .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ |
| 1099 | .emit_ib = vcn_v1_0_dec_ring_emit_ib, |
| 1100 | .emit_fence = vcn_v1_0_dec_ring_emit_fence, |
| 1101 | .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, |
Leo Liu | 8c303c0 | 2017-02-06 11:52:46 -0500 | [diff] [blame] | 1102 | .test_ring = amdgpu_vcn_dec_ring_test_ring, |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 1103 | .test_ib = amdgpu_vcn_dec_ring_test_ib, |
Shaoyun Liu | 946a4d5 | 2017-11-28 17:01:21 -0500 | [diff] [blame] | 1104 | .insert_nop = vcn_v1_0_ring_insert_nop, |
Leo Liu | e7501c3 | 2017-02-07 11:52:00 -0500 | [diff] [blame] | 1105 | .insert_start = vcn_v1_0_dec_ring_insert_start, |
Leo Liu | a4c424c | 2017-01-25 14:37:41 -0500 | [diff] [blame] | 1106 | .insert_end = vcn_v1_0_dec_ring_insert_end, |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 1107 | .pad_ib = amdgpu_ring_generic_pad_ib, |
| 1108 | .begin_use = amdgpu_vcn_ring_begin_use, |
| 1109 | .end_use = amdgpu_vcn_ring_end_use, |
Christian König | 4383736 | 2018-01-26 14:20:55 +0100 | [diff] [blame] | 1110 | .emit_wreg = vcn_v1_0_dec_ring_emit_wreg, |
Christian König | 2b124b0 | 2018-01-26 14:31:07 +0100 | [diff] [blame] | 1111 | .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait, |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 1112 | }; |
| 1113 | |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 1114 | static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { |
| 1115 | .type = AMDGPU_RING_TYPE_VCN_ENC, |
| 1116 | .align_mask = 0x3f, |
| 1117 | .nop = VCN_ENC_CMD_NO_OP, |
| 1118 | .support_64bit_ptrs = false, |
Hawking Zhang | 04e5f2a | 2017-05-15 17:03:02 +0800 | [diff] [blame] | 1119 | .vmhub = AMDGPU_MMHUB, |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 1120 | .get_rptr = vcn_v1_0_enc_ring_get_rptr, |
| 1121 | .get_wptr = vcn_v1_0_enc_ring_get_wptr, |
| 1122 | .set_wptr = vcn_v1_0_enc_ring_set_wptr, |
| 1123 | .emit_frame_size = |
Christian König | f732b6b | 2018-01-26 15:00:43 +0100 | [diff] [blame] | 1124 | SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + |
| 1125 | SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + |
| 1126 | 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */ |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 1127 | 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ |
| 1128 | 1, /* vcn_v1_0_enc_ring_insert_end */ |
| 1129 | .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ |
| 1130 | .emit_ib = vcn_v1_0_enc_ring_emit_ib, |
| 1131 | .emit_fence = vcn_v1_0_enc_ring_emit_fence, |
| 1132 | .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, |
Leo Liu | c3bd304 | 2017-02-21 10:38:42 -0500 | [diff] [blame] | 1133 | .test_ring = amdgpu_vcn_enc_ring_test_ring, |
Leo Liu | 25547cf | 2017-05-08 17:31:31 -0400 | [diff] [blame] | 1134 | .test_ib = amdgpu_vcn_enc_ring_test_ib, |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 1135 | .insert_nop = amdgpu_ring_insert_nop, |
| 1136 | .insert_end = vcn_v1_0_enc_ring_insert_end, |
| 1137 | .pad_ib = amdgpu_ring_generic_pad_ib, |
| 1138 | .begin_use = amdgpu_vcn_ring_begin_use, |
| 1139 | .end_use = amdgpu_vcn_ring_end_use, |
Christian König | 4383736 | 2018-01-26 14:20:55 +0100 | [diff] [blame] | 1140 | .emit_wreg = vcn_v1_0_enc_ring_emit_wreg, |
Christian König | 2b124b0 | 2018-01-26 14:31:07 +0100 | [diff] [blame] | 1141 | .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait, |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 1142 | }; |
| 1143 | |
Leo Liu | cca69fe | 2017-05-05 11:40:59 -0400 | [diff] [blame] | 1144 | static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) |
| 1145 | { |
| 1146 | adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; |
| 1147 | DRM_INFO("VCN decode is enabled in VM mode\n"); |
| 1148 | } |
Leo Liu | a319f44 | 2016-12-28 13:22:18 -0500 | [diff] [blame] | 1149 | |
Leo Liu | 8ace845f | 2017-02-21 10:36:15 -0500 | [diff] [blame] | 1150 | static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) |
| 1151 | { |
| 1152 | int i; |
| 1153 | |
| 1154 | for (i = 0; i < adev->vcn.num_enc_rings; ++i) |
| 1155 | adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; |
| 1156 | |
| 1157 | DRM_INFO("VCN encode is enabled in VM mode\n"); |
| 1158 | } |
| 1159 | |
Leo Liu | a319f44 | 2016-12-28 13:22:18 -0500 | [diff] [blame] | 1160 | static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { |
| 1161 | .set = vcn_v1_0_set_interrupt_state, |
| 1162 | .process = vcn_v1_0_process_interrupt, |
| 1163 | }; |
| 1164 | |
| 1165 | static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) |
| 1166 | { |
Michel Dänzer | 89ce6e0 | 2017-11-22 15:55:21 +0100 | [diff] [blame] | 1167 | adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 1; |
Leo Liu | a319f44 | 2016-12-28 13:22:18 -0500 | [diff] [blame] | 1168 | adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs; |
| 1169 | } |
Leo Liu | 3ea975e | 2016-12-28 13:04:16 -0500 | [diff] [blame] | 1170 | |
| 1171 | const struct amdgpu_ip_block_version vcn_v1_0_ip_block = |
| 1172 | { |
| 1173 | .type = AMD_IP_BLOCK_TYPE_VCN, |
| 1174 | .major = 1, |
| 1175 | .minor = 0, |
| 1176 | .rev = 0, |
| 1177 | .funcs = &vcn_v1_0_ip_funcs, |
| 1178 | }; |