blob: a5b326754124dee3b86496a14243999cdea19cb4 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Jamie Iles7779b3452014-02-25 17:01:01 -06002/*
3 * Copyright (c) 2011 Jamie Iles
4 *
Jamie Iles7779b3452014-02-25 17:01:01 -06005 * All enquiries to support@picochip.com
6 */
Jiang Qiue6cb3482016-04-28 17:32:03 +08007#include <linux/acpi.h>
Phil Edworthye6bf3772018-03-12 18:30:56 +00008#include <linux/clk.h>
Jamie Iles7779b3452014-02-25 17:01:01 -06009#include <linux/err.h>
Phil Edworthye6bf3772018-03-12 18:30:56 +000010#include <linux/gpio/driver.h>
Jamie Iles7779b3452014-02-25 17:01:01 -060011#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/ioport.h>
15#include <linux/irq.h>
Jamie Iles7779b3452014-02-25 17:01:01 -060016#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
Hoan Trana72b8c42017-02-21 11:32:43 -080019#include <linux/of_device.h>
Jamie Iles7779b3452014-02-25 17:01:01 -060020#include <linux/of_irq.h>
21#include <linux/platform_device.h>
Jiang Qiu4ba8cfa2016-04-28 17:32:02 +080022#include <linux/property.h>
Alan Tull07901a92017-10-11 11:34:44 -050023#include <linux/reset.h>
Jamie Iles7779b3452014-02-25 17:01:01 -060024#include <linux/spinlock.h>
Weike Chen3d2613c2014-09-17 09:18:39 -070025#include <linux/platform_data/gpio-dwapb.h>
26#include <linux/slab.h>
Jamie Iles7779b3452014-02-25 17:01:01 -060027
Jiang Qiue6cb3482016-04-28 17:32:03 +080028#include "gpiolib.h"
Andy Shevchenko77cb9072019-07-30 13:43:36 +030029#include "gpiolib-acpi.h"
Jiang Qiue6cb3482016-04-28 17:32:03 +080030
Jamie Iles7779b3452014-02-25 17:01:01 -060031#define GPIO_SWPORTA_DR 0x00
32#define GPIO_SWPORTA_DDR 0x04
33#define GPIO_SWPORTB_DR 0x0c
34#define GPIO_SWPORTB_DDR 0x10
35#define GPIO_SWPORTC_DR 0x18
36#define GPIO_SWPORTC_DDR 0x1c
37#define GPIO_SWPORTD_DR 0x24
38#define GPIO_SWPORTD_DDR 0x28
39#define GPIO_INTEN 0x30
40#define GPIO_INTMASK 0x34
41#define GPIO_INTTYPE_LEVEL 0x38
42#define GPIO_INT_POLARITY 0x3c
43#define GPIO_INTSTATUS 0x40
Weike Chen5d60d9e2014-09-17 09:18:41 -070044#define GPIO_PORTA_DEBOUNCE 0x48
Jamie Iles7779b3452014-02-25 17:01:01 -060045#define GPIO_PORTA_EOI 0x4c
46#define GPIO_EXT_PORTA 0x50
47#define GPIO_EXT_PORTB 0x54
48#define GPIO_EXT_PORTC 0x58
49#define GPIO_EXT_PORTD 0x5c
50
Andy Shevchenkoc58220c2020-04-15 17:15:21 +030051#define DWAPB_DRIVER_NAME "gpio-dwapb"
Jamie Iles7779b3452014-02-25 17:01:01 -060052#define DWAPB_MAX_PORTS 4
Andy Shevchenkoc58220c2020-04-15 17:15:21 +030053
Linus Walleij89f99fe2018-02-08 17:03:58 +010054#define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
55#define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
56#define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
Jamie Iles7779b3452014-02-25 17:01:01 -060057
Hoan Trana72b8c42017-02-21 11:32:43 -080058#define GPIO_REG_OFFSET_V2 1
59
60#define GPIO_INTMASK_V2 0x44
61#define GPIO_INTTYPE_LEVEL_V2 0x34
62#define GPIO_INT_POLARITY_V2 0x38
63#define GPIO_INTSTATUS_V2 0x3c
64#define GPIO_PORTA_EOI_V2 0x40
65
Serge Semin5c544c92020-03-23 22:54:00 +030066#define DWAPB_NR_CLOCKS 2
67
Jamie Iles7779b3452014-02-25 17:01:01 -060068struct dwapb_gpio;
69
Weike Chen1e960db2014-09-17 09:18:42 -070070#ifdef CONFIG_PM_SLEEP
71/* Store GPIO context across system-wide suspend/resume transitions */
72struct dwapb_context {
73 u32 data;
74 u32 dir;
75 u32 ext;
76 u32 int_en;
77 u32 int_mask;
78 u32 int_type;
79 u32 int_pol;
80 u32 int_deb;
Hoan Tran6437c7b2017-09-08 15:41:15 -070081 u32 wake_en;
Weike Chen1e960db2014-09-17 09:18:42 -070082};
83#endif
84
Serge Semin0ea68392020-07-30 18:28:02 +030085struct dwapb_gpio_port_irqchip {
86 struct irq_chip irqchip;
87 unsigned int nr_irqs;
88 unsigned int irq[DWAPB_MAX_GPIOS];
89};
90
Jamie Iles7779b3452014-02-25 17:01:01 -060091struct dwapb_gpio_port {
Linus Walleij0f4630f2015-12-04 14:02:58 +010092 struct gpio_chip gc;
Serge Semin0ea68392020-07-30 18:28:02 +030093 struct dwapb_gpio_port_irqchip *pirq;
Jamie Iles7779b3452014-02-25 17:01:01 -060094 struct dwapb_gpio *gpio;
Weike Chen1e960db2014-09-17 09:18:42 -070095#ifdef CONFIG_PM_SLEEP
96 struct dwapb_context *ctx;
97#endif
98 unsigned int idx;
Jamie Iles7779b3452014-02-25 17:01:01 -060099};
Serge Semin0ea68392020-07-30 18:28:02 +0300100#define to_dwapb_gpio(_gc) \
101 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
Jamie Iles7779b3452014-02-25 17:01:01 -0600102
103struct dwapb_gpio {
104 struct device *dev;
105 void __iomem *regs;
106 struct dwapb_gpio_port *ports;
107 unsigned int nr_ports;
Hoan Trana72b8c42017-02-21 11:32:43 -0800108 unsigned int flags;
Alan Tull07901a92017-10-11 11:34:44 -0500109 struct reset_control *rst;
Serge Semin5c544c92020-03-23 22:54:00 +0300110 struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
Jamie Iles7779b3452014-02-25 17:01:01 -0600111};
112
Hoan Trana72b8c42017-02-21 11:32:43 -0800113static inline u32 gpio_reg_v2_convert(unsigned int offset)
114{
115 switch (offset) {
116 case GPIO_INTMASK:
117 return GPIO_INTMASK_V2;
118 case GPIO_INTTYPE_LEVEL:
119 return GPIO_INTTYPE_LEVEL_V2;
120 case GPIO_INT_POLARITY:
121 return GPIO_INT_POLARITY_V2;
122 case GPIO_INTSTATUS:
123 return GPIO_INTSTATUS_V2;
124 case GPIO_PORTA_EOI:
125 return GPIO_PORTA_EOI_V2;
126 }
127
128 return offset;
129}
130
131static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
132{
133 if (gpio->flags & GPIO_REG_OFFSET_V2)
134 return gpio_reg_v2_convert(offset);
135
136 return offset;
137}
138
Weike Chen67809b92014-09-17 09:18:40 -0700139static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
140{
Linus Walleij0f4630f2015-12-04 14:02:58 +0100141 struct gpio_chip *gc = &gpio->ports[0].gc;
Weike Chen67809b92014-09-17 09:18:40 -0700142 void __iomem *reg_base = gpio->regs;
143
Hoan Trana72b8c42017-02-21 11:32:43 -0800144 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
Weike Chen67809b92014-09-17 09:18:40 -0700145}
146
147static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
148 u32 val)
149{
Linus Walleij0f4630f2015-12-04 14:02:58 +0100150 struct gpio_chip *gc = &gpio->ports[0].gc;
Weike Chen67809b92014-09-17 09:18:40 -0700151 void __iomem *reg_base = gpio->regs;
152
Hoan Trana72b8c42017-02-21 11:32:43 -0800153 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
Weike Chen67809b92014-09-17 09:18:40 -0700154}
155
Linus Walleij62c16232018-02-08 18:00:05 +0100156static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
157{
158 struct dwapb_gpio_port *port;
159 int i;
160
161 for (i = 0; i < gpio->nr_ports; i++) {
162 port = &gpio->ports[i];
Serge Seminf9f890b2020-07-30 18:28:01 +0300163 if (port->idx == offs / DWAPB_MAX_GPIOS)
Linus Walleij62c16232018-02-08 18:00:05 +0100164 return port;
165 }
166
167 return NULL;
168}
169
Jamie Iles7779b3452014-02-25 17:01:01 -0600170static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
171{
Linus Walleij62c16232018-02-08 18:00:05 +0100172 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
173 struct gpio_chip *gc;
174 u32 pol;
175 int val;
Jamie Iles7779b3452014-02-25 17:01:01 -0600176
Linus Walleij62c16232018-02-08 18:00:05 +0100177 if (!port)
178 return;
179 gc = &port->gc;
180
181 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
182 /* Just read the current value right out of the data register */
Serge Seminf9f890b2020-07-30 18:28:01 +0300183 val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
Linus Walleij62c16232018-02-08 18:00:05 +0100184 if (val)
185 pol &= ~BIT(offs);
Jamie Iles7779b3452014-02-25 17:01:01 -0600186 else
Linus Walleij62c16232018-02-08 18:00:05 +0100187 pol |= BIT(offs);
Jamie Iles7779b3452014-02-25 17:01:01 -0600188
Linus Walleij62c16232018-02-08 18:00:05 +0100189 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
Jamie Iles7779b3452014-02-25 17:01:01 -0600190}
191
Weike Chen3d2613c2014-09-17 09:18:39 -0700192static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
Jamie Iles7779b3452014-02-25 17:01:01 -0600193{
Serge Semin0ea68392020-07-30 18:28:02 +0300194 struct gpio_chip *gc = &gpio->ports[0].gc;
Andy Shevchenko038aa1f2020-04-15 17:15:22 +0300195 unsigned long irq_status;
Andy Shevchenkoe092bc52020-04-15 17:15:26 +0300196 irq_hw_number_t hwirq;
Jamie Iles7779b3452014-02-25 17:01:01 -0600197
Andy Shevchenko038aa1f2020-04-15 17:15:22 +0300198 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
Serge Seminf9f890b2020-07-30 18:28:01 +0300199 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
Serge Semin0ea68392020-07-30 18:28:02 +0300200 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);
Andy Shevchenko038aa1f2020-04-15 17:15:22 +0300201 u32 irq_type = irq_get_trigger_type(gpio_irq);
Jamie Iles7779b3452014-02-25 17:01:01 -0600202
203 generic_handle_irq(gpio_irq);
Jamie Iles7779b3452014-02-25 17:01:01 -0600204
Andy Shevchenko038aa1f2020-04-15 17:15:22 +0300205 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
Jamie Iles7779b3452014-02-25 17:01:01 -0600206 dwapb_toggle_trigger(gpio, hwirq);
207 }
208
Andy Shevchenko038aa1f2020-04-15 17:15:22 +0300209 return irq_status;
Weike Chen3d2613c2014-09-17 09:18:39 -0700210}
211
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200212static void dwapb_irq_handler(struct irq_desc *desc)
Weike Chen3d2613c2014-09-17 09:18:39 -0700213{
Jiang Liu476f8b42015-06-04 12:13:15 +0800214 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
Weike Chen3d2613c2014-09-17 09:18:39 -0700215 struct irq_chip *chip = irq_desc_get_chip(desc);
216
Andy Shevchenko9b0aef32020-04-15 17:15:23 +0300217 chained_irq_enter(chip, desc);
Weike Chen3d2613c2014-09-17 09:18:39 -0700218 dwapb_do_irq(gpio);
Andy Shevchenko9b0aef32020-04-15 17:15:23 +0300219 chained_irq_exit(chip, desc);
Jamie Iles7779b3452014-02-25 17:01:01 -0600220}
221
Serge Semin75c12362020-07-30 18:28:00 +0300222static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
223{
224 return IRQ_RETVAL(dwapb_do_irq(dev_id));
225}
226
Serge Semin0ea68392020-07-30 18:28:02 +0300227static void dwapb_irq_ack(struct irq_data *d)
228{
229 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
230 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
231 u32 val = BIT(irqd_to_hwirq(d));
232 unsigned long flags;
233
234 spin_lock_irqsave(&gc->bgpio_lock, flags);
235 dwapb_write(gpio, GPIO_PORTA_EOI, val);
236 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
237}
238
239static void dwapb_irq_mask(struct irq_data *d)
240{
241 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
242 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
243 unsigned long flags;
244 u32 val;
245
246 spin_lock_irqsave(&gc->bgpio_lock, flags);
247 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d));
248 dwapb_write(gpio, GPIO_INTMASK, val);
249 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
250}
251
252static void dwapb_irq_unmask(struct irq_data *d)
253{
254 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
255 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
256 unsigned long flags;
257 u32 val;
258
259 spin_lock_irqsave(&gc->bgpio_lock, flags);
260 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d));
261 dwapb_write(gpio, GPIO_INTMASK, val);
262 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
263}
264
Jamie Iles7779b3452014-02-25 17:01:01 -0600265static void dwapb_irq_enable(struct irq_data *d)
266{
Serge Semin0ea68392020-07-30 18:28:02 +0300267 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
268 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
Jamie Iles7779b3452014-02-25 17:01:01 -0600269 unsigned long flags;
270 u32 val;
271
Linus Walleij0f4630f2015-12-04 14:02:58 +0100272 spin_lock_irqsave(&gc->bgpio_lock, flags);
Weike Chen67809b92014-09-17 09:18:40 -0700273 val = dwapb_read(gpio, GPIO_INTEN);
Andy Shevchenkoe092bc52020-04-15 17:15:26 +0300274 val |= BIT(irqd_to_hwirq(d));
Weike Chen67809b92014-09-17 09:18:40 -0700275 dwapb_write(gpio, GPIO_INTEN, val);
Linus Walleij0f4630f2015-12-04 14:02:58 +0100276 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
Jamie Iles7779b3452014-02-25 17:01:01 -0600277}
278
279static void dwapb_irq_disable(struct irq_data *d)
280{
Serge Semin0ea68392020-07-30 18:28:02 +0300281 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
282 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
Jamie Iles7779b3452014-02-25 17:01:01 -0600283 unsigned long flags;
284 u32 val;
285
Linus Walleij0f4630f2015-12-04 14:02:58 +0100286 spin_lock_irqsave(&gc->bgpio_lock, flags);
Weike Chen67809b92014-09-17 09:18:40 -0700287 val = dwapb_read(gpio, GPIO_INTEN);
Andy Shevchenkoe092bc52020-04-15 17:15:26 +0300288 val &= ~BIT(irqd_to_hwirq(d));
Weike Chen67809b92014-09-17 09:18:40 -0700289 dwapb_write(gpio, GPIO_INTEN, val);
Linus Walleij0f4630f2015-12-04 14:02:58 +0100290 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
Jamie Iles7779b3452014-02-25 17:01:01 -0600291}
292
Jamie Iles7779b3452014-02-25 17:01:01 -0600293static int dwapb_irq_set_type(struct irq_data *d, u32 type)
294{
Serge Semin0ea68392020-07-30 18:28:02 +0300295 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
296 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
Andy Shevchenkoe092bc52020-04-15 17:15:26 +0300297 irq_hw_number_t bit = irqd_to_hwirq(d);
Jamie Iles7779b3452014-02-25 17:01:01 -0600298 unsigned long level, polarity, flags;
299
Andy Shevchenkod31275a2020-04-15 17:15:28 +0300300 if (type & ~IRQ_TYPE_SENSE_MASK)
Jamie Iles7779b3452014-02-25 17:01:01 -0600301 return -EINVAL;
302
Linus Walleij0f4630f2015-12-04 14:02:58 +0100303 spin_lock_irqsave(&gc->bgpio_lock, flags);
Weike Chen67809b92014-09-17 09:18:40 -0700304 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
305 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
Jamie Iles7779b3452014-02-25 17:01:01 -0600306
307 switch (type) {
308 case IRQ_TYPE_EDGE_BOTH:
309 level |= BIT(bit);
310 dwapb_toggle_trigger(gpio, bit);
311 break;
312 case IRQ_TYPE_EDGE_RISING:
313 level |= BIT(bit);
314 polarity |= BIT(bit);
315 break;
316 case IRQ_TYPE_EDGE_FALLING:
317 level |= BIT(bit);
318 polarity &= ~BIT(bit);
319 break;
320 case IRQ_TYPE_LEVEL_HIGH:
321 level &= ~BIT(bit);
322 polarity |= BIT(bit);
323 break;
324 case IRQ_TYPE_LEVEL_LOW:
325 level &= ~BIT(bit);
326 polarity &= ~BIT(bit);
327 break;
328 }
329
Serge Semin0ea68392020-07-30 18:28:02 +0300330 if (type & IRQ_TYPE_LEVEL_MASK)
331 irq_set_handler_locked(d, handle_level_irq);
332 else if (type & IRQ_TYPE_EDGE_BOTH)
333 irq_set_handler_locked(d, handle_edge_irq);
Sebastian Andrzej Siewior6a2f4b72014-05-26 22:58:14 +0200334
Weike Chen67809b92014-09-17 09:18:40 -0700335 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
Xiaoguang Chenedadced2017-06-02 07:27:15 +0800336 if (type != IRQ_TYPE_EDGE_BOTH)
337 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
Linus Walleij0f4630f2015-12-04 14:02:58 +0100338 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
Jamie Iles7779b3452014-02-25 17:01:01 -0600339
340 return 0;
341}
342
Hoan Tran6437c7b2017-09-08 15:41:15 -0700343#ifdef CONFIG_PM_SLEEP
344static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
345{
346 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
347 struct dwapb_gpio *gpio = igc->private;
348 struct dwapb_context *ctx = gpio->ports[0].ctx;
Andy Shevchenkoe092bc52020-04-15 17:15:26 +0300349 irq_hw_number_t bit = irqd_to_hwirq(d);
Hoan Tran6437c7b2017-09-08 15:41:15 -0700350
351 if (enable)
Andy Shevchenkoe092bc52020-04-15 17:15:26 +0300352 ctx->wake_en |= BIT(bit);
Hoan Tran6437c7b2017-09-08 15:41:15 -0700353 else
Andy Shevchenkoe092bc52020-04-15 17:15:26 +0300354 ctx->wake_en &= ~BIT(bit);
Hoan Tran6437c7b2017-09-08 15:41:15 -0700355
356 return 0;
357}
358#endif
359
Weike Chen5d60d9e2014-09-17 09:18:41 -0700360static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
361 unsigned offset, unsigned debounce)
362{
Linus Walleij0f4630f2015-12-04 14:02:58 +0100363 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
Weike Chen5d60d9e2014-09-17 09:18:41 -0700364 struct dwapb_gpio *gpio = port->gpio;
365 unsigned long flags, val_deb;
Linus Walleijd97a1b52017-10-20 12:26:51 +0200366 unsigned long mask = BIT(offset);
Weike Chen5d60d9e2014-09-17 09:18:41 -0700367
Linus Walleij0f4630f2015-12-04 14:02:58 +0100368 spin_lock_irqsave(&gc->bgpio_lock, flags);
Weike Chen5d60d9e2014-09-17 09:18:41 -0700369
370 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
371 if (debounce)
Andy Shevchenko48ce8052020-04-15 17:15:29 +0300372 val_deb |= mask;
Weike Chen5d60d9e2014-09-17 09:18:41 -0700373 else
Andy Shevchenko48ce8052020-04-15 17:15:29 +0300374 val_deb &= ~mask;
375 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
Weike Chen5d60d9e2014-09-17 09:18:41 -0700376
Linus Walleij0f4630f2015-12-04 14:02:58 +0100377 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
Weike Chen5d60d9e2014-09-17 09:18:41 -0700378
379 return 0;
380}
381
Mika Westerberg2956b5d2017-01-23 15:34:34 +0300382static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
383 unsigned long config)
384{
385 u32 debounce;
386
387 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
388 return -ENOTSUPP;
389
390 debounce = pinconf_to_config_argument(config);
391 return dwapb_gpio_set_debounce(gc, offset, debounce);
392}
393
Serge Semin0ea68392020-07-30 18:28:02 +0300394static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
395 struct dwapb_port_property *pp)
396{
397 int i;
398
399 /* Group all available IRQs into an array of parental IRQs. */
400 for (i = 0; i < pp->ngpio; ++i) {
401 if (!pp->irq[i])
402 continue;
403
404 pirq->irq[pirq->nr_irqs++] = pp->irq[i];
405 }
406
407 return pirq->nr_irqs ? 0 : -ENOENT;
408}
409
Jamie Iles7779b3452014-02-25 17:01:01 -0600410static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
Weike Chen3d2613c2014-09-17 09:18:39 -0700411 struct dwapb_gpio_port *port,
412 struct dwapb_port_property *pp)
Jamie Iles7779b3452014-02-25 17:01:01 -0600413{
Serge Semin0ea68392020-07-30 18:28:02 +0300414 struct dwapb_gpio_port_irqchip *pirq;
Linus Walleij0f4630f2015-12-04 14:02:58 +0100415 struct gpio_chip *gc = &port->gc;
Serge Semin0ea68392020-07-30 18:28:02 +0300416 struct gpio_irq_chip *girq;
417 int err;
Jamie Iles7779b3452014-02-25 17:01:01 -0600418
Serge Semin0ea68392020-07-30 18:28:02 +0300419 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
420 if (!pirq)
421 return;
422
423 if (dwapb_convert_irqs(pirq, pp)) {
Andy Shevchenko551cb862020-05-19 16:12:33 +0300424 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
Serge Semin0ea68392020-07-30 18:28:02 +0300425 goto err_kfree_pirq;
Andy Shevchenko551cb862020-05-19 16:12:33 +0300426 }
427
Serge Semin0ea68392020-07-30 18:28:02 +0300428 girq = &gc->irq;
429 girq->handler = handle_bad_irq;
430 girq->default_type = IRQ_TYPE_NONE;
Jamie Iles7779b3452014-02-25 17:01:01 -0600431
Serge Semin0ea68392020-07-30 18:28:02 +0300432 port->pirq = pirq;
433 pirq->irqchip.name = DWAPB_DRIVER_NAME;
434 pirq->irqchip.irq_ack = dwapb_irq_ack;
435 pirq->irqchip.irq_mask = dwapb_irq_mask;
436 pirq->irqchip.irq_unmask = dwapb_irq_unmask;
437 pirq->irqchip.irq_set_type = dwapb_irq_set_type;
438 pirq->irqchip.irq_enable = dwapb_irq_enable;
439 pirq->irqchip.irq_disable = dwapb_irq_disable;
Hoan Tran6437c7b2017-09-08 15:41:15 -0700440#ifdef CONFIG_PM_SLEEP
Serge Semin0ea68392020-07-30 18:28:02 +0300441 pirq->irqchip.irq_set_wake = dwapb_irq_set_wake;
Hoan Tran6437c7b2017-09-08 15:41:15 -0700442#endif
Jamie Iles7779b3452014-02-25 17:01:01 -0600443
Weike Chen3d2613c2014-09-17 09:18:39 -0700444 if (!pp->irq_shared) {
Serge Semin0ea68392020-07-30 18:28:02 +0300445 girq->num_parents = pirq->nr_irqs;
446 girq->parents = pirq->irq;
447 girq->parent_handler_data = gpio;
448 girq->parent_handler = dwapb_irq_handler;
Weike Chen3d2613c2014-09-17 09:18:39 -0700449 } else {
Serge Semin0ea68392020-07-30 18:28:02 +0300450 /* This will let us handle the parent IRQ in the driver */
451 girq->num_parents = 0;
452 girq->parents = NULL;
453 girq->parent_handler = NULL;
454
Weike Chen3d2613c2014-09-17 09:18:39 -0700455 /*
456 * Request a shared IRQ since where MFD would have devices
457 * using the same irq pin
458 */
Phil Edworthye6ca26a2018-04-26 17:19:47 +0100459 err = devm_request_irq(gpio->dev, pp->irq[0],
Weike Chen3d2613c2014-09-17 09:18:39 -0700460 dwapb_irq_handler_mfd,
Andy Shevchenkoc58220c2020-04-15 17:15:21 +0300461 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
Weike Chen3d2613c2014-09-17 09:18:39 -0700462 if (err) {
463 dev_err(gpio->dev, "error requesting IRQ\n");
Serge Semin0ea68392020-07-30 18:28:02 +0300464 goto err_kfree_pirq;
Weike Chen3d2613c2014-09-17 09:18:39 -0700465 }
466 }
Jamie Iles7779b3452014-02-25 17:01:01 -0600467
Serge Semin0ea68392020-07-30 18:28:02 +0300468 girq->chip = &pirq->irqchip;
Jamie Iles7779b3452014-02-25 17:01:01 -0600469
Serge Semin0ea68392020-07-30 18:28:02 +0300470 return;
Jamie Iles7779b3452014-02-25 17:01:01 -0600471
Serge Semin0ea68392020-07-30 18:28:02 +0300472err_kfree_pirq:
473 devm_kfree(gpio->dev, pirq);
Jamie Iles7779b3452014-02-25 17:01:01 -0600474}
475
476static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
Weike Chen3d2613c2014-09-17 09:18:39 -0700477 struct dwapb_port_property *pp,
Jamie Iles7779b3452014-02-25 17:01:01 -0600478 unsigned int offs)
479{
480 struct dwapb_gpio_port *port;
Jamie Iles7779b3452014-02-25 17:01:01 -0600481 void __iomem *dat, *set, *dirout;
482 int err;
483
Jamie Iles7779b3452014-02-25 17:01:01 -0600484 port = &gpio->ports[offs];
485 port->gpio = gpio;
Weike Chen1e960db2014-09-17 09:18:42 -0700486 port->idx = pp->idx;
487
488#ifdef CONFIG_PM_SLEEP
489 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
490 if (!port->ctx)
491 return -ENOMEM;
492#endif
Jamie Iles7779b3452014-02-25 17:01:01 -0600493
Andy Shevchenko1475b622020-04-22 14:06:54 +0300494 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
495 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
496 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
Jamie Iles7779b3452014-02-25 17:01:01 -0600497
Linus Walleij62c16232018-02-08 18:00:05 +0100498 /* This registers 32 GPIO lines per port */
Linus Walleij0f4630f2015-12-04 14:02:58 +0100499 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
Linus Walleijd97a1b52017-10-20 12:26:51 +0200500 NULL, 0);
Jamie Iles7779b3452014-02-25 17:01:01 -0600501 if (err) {
Jiang Qiue8159182016-04-28 17:32:01 +0800502 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
503 port->idx);
Jamie Iles7779b3452014-02-25 17:01:01 -0600504 return err;
505 }
506
Weike Chen3d2613c2014-09-17 09:18:39 -0700507#ifdef CONFIG_OF_GPIO
Jiang Qiu4ba8cfa2016-04-28 17:32:02 +0800508 port->gc.of_node = to_of_node(pp->fwnode);
Weike Chen3d2613c2014-09-17 09:18:39 -0700509#endif
Linus Walleij0f4630f2015-12-04 14:02:58 +0100510 port->gc.ngpio = pp->ngpio;
511 port->gc.base = pp->gpio_base;
Jamie Iles7779b3452014-02-25 17:01:01 -0600512
Weike Chen5d60d9e2014-09-17 09:18:41 -0700513 /* Only port A support debounce */
514 if (pp->idx == 0)
Mika Westerberg2956b5d2017-01-23 15:34:34 +0300515 port->gc.set_config = dwapb_gpio_set_config;
Weike Chen5d60d9e2014-09-17 09:18:41 -0700516
Andy Shevchenko551cb862020-05-19 16:12:33 +0300517 /* Only port A can provide interrupts in all configurations of the IP */
518 if (pp->idx == 0)
Weike Chen3d2613c2014-09-17 09:18:39 -0700519 dwapb_configure_irqs(gpio, port, pp);
Jamie Iles7779b3452014-02-25 17:01:01 -0600520
Serge Seminfeeaefd2020-07-30 18:28:07 +0300521 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
Andy Shevchenko494a94e32020-05-19 16:12:30 +0300522 if (err) {
Jiang Qiue8159182016-04-28 17:32:01 +0800523 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
524 port->idx);
Andy Shevchenko494a94e32020-05-19 16:12:30 +0300525 return err;
526 }
Jamie Iles7779b3452014-02-25 17:01:01 -0600527
Andy Shevchenko494a94e32020-05-19 16:12:30 +0300528 return 0;
Jamie Iles7779b3452014-02-25 17:01:01 -0600529}
530
Andy Shevchenko4c2b54f2020-04-15 17:15:32 +0300531static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
532 struct dwapb_port_property *pp)
533{
534 struct device_node *np = NULL;
Andy Shevchenkoaa909392020-05-19 16:12:32 +0300535 int irq = -ENXIO, j;
Andy Shevchenko4c2b54f2020-04-15 17:15:32 +0300536
537 if (fwnode_property_read_bool(fwnode, "interrupt-controller"))
538 np = to_of_node(fwnode);
539
540 for (j = 0; j < pp->ngpio; j++) {
Andy Shevchenko4c2b54f2020-04-15 17:15:32 +0300541 if (np)
Andy Shevchenkoaa909392020-05-19 16:12:32 +0300542 irq = of_irq_get(np, j);
Andy Shevchenko4c2b54f2020-04-15 17:15:32 +0300543 else if (has_acpi_companion(dev))
Andy Shevchenkoaa909392020-05-19 16:12:32 +0300544 irq = platform_get_irq_optional(to_platform_device(dev), j);
545 if (irq > 0)
546 pp->irq[j] = irq;
Andy Shevchenko4c2b54f2020-04-15 17:15:32 +0300547 }
Andy Shevchenko4c2b54f2020-04-15 17:15:32 +0300548}
549
550static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
Weike Chen3d2613c2014-09-17 09:18:39 -0700551{
Jiang Qiu4ba8cfa2016-04-28 17:32:02 +0800552 struct fwnode_handle *fwnode;
Weike Chen3d2613c2014-09-17 09:18:39 -0700553 struct dwapb_platform_data *pdata;
554 struct dwapb_port_property *pp;
555 int nports;
Andy Shevchenko4c2b54f2020-04-15 17:15:32 +0300556 int i;
Weike Chen3d2613c2014-09-17 09:18:39 -0700557
Jiang Qiu4ba8cfa2016-04-28 17:32:02 +0800558 nports = device_get_child_node_count(dev);
Weike Chen3d2613c2014-09-17 09:18:39 -0700559 if (nports == 0)
560 return ERR_PTR(-ENODEV);
561
Axel Linda9df932014-12-28 15:23:14 +0800562 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
Weike Chen3d2613c2014-09-17 09:18:39 -0700563 if (!pdata)
564 return ERR_PTR(-ENOMEM);
565
Axel Linda9df932014-12-28 15:23:14 +0800566 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
567 if (!pdata->properties)
Weike Chen3d2613c2014-09-17 09:18:39 -0700568 return ERR_PTR(-ENOMEM);
Weike Chen3d2613c2014-09-17 09:18:39 -0700569
570 pdata->nports = nports;
571
572 i = 0;
Jiang Qiu4ba8cfa2016-04-28 17:32:02 +0800573 device_for_each_child_node(dev, fwnode) {
Weike Chen3d2613c2014-09-17 09:18:39 -0700574 pp = &pdata->properties[i++];
Jiang Qiu4ba8cfa2016-04-28 17:32:02 +0800575 pp->fwnode = fwnode;
Weike Chen3d2613c2014-09-17 09:18:39 -0700576
Jiang Qiu4ba8cfa2016-04-28 17:32:02 +0800577 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
Weike Chen3d2613c2014-09-17 09:18:39 -0700578 pp->idx >= DWAPB_MAX_PORTS) {
Jiang Qiue8159182016-04-28 17:32:01 +0800579 dev_err(dev,
580 "missing/invalid port index for port%d\n", i);
Wei Yongjunbfab7c82016-07-10 02:17:36 +0000581 fwnode_handle_put(fwnode);
Weike Chen3d2613c2014-09-17 09:18:39 -0700582 return ERR_PTR(-EINVAL);
583 }
584
Serge Semin75694862020-07-30 18:27:59 +0300585 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
586 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
Jiang Qiue8159182016-04-28 17:32:01 +0800587 dev_info(dev,
588 "failed to get number of gpios for port%d\n",
589 i);
Serge Seminf9f890b2020-07-30 18:28:01 +0300590 pp->ngpio = DWAPB_MAX_GPIOS;
Weike Chen3d2613c2014-09-17 09:18:39 -0700591 }
592
Phil Edworthyda069d52018-05-23 09:52:44 +0100593 pp->irq_shared = false;
594 pp->gpio_base = -1;
595
Weike Chen3d2613c2014-09-17 09:18:39 -0700596 /*
597 * Only port A can provide interrupts in all configurations of
598 * the IP.
599 */
Andy Shevchenko4c2b54f2020-04-15 17:15:32 +0300600 if (pp->idx == 0)
601 dwapb_get_irq(dev, fwnode, pp);
Weike Chen3d2613c2014-09-17 09:18:39 -0700602 }
603
604 return pdata;
605}
606
Serge Semin4731d802020-07-30 18:28:05 +0300607static void dwapb_assert_reset(void *data)
608{
609 struct dwapb_gpio *gpio = data;
610
611 reset_control_assert(gpio->rst);
612}
613
614static int dwapb_get_reset(struct dwapb_gpio *gpio)
615{
616 int err;
617
618 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
619 if (IS_ERR(gpio->rst)) {
620 dev_err(gpio->dev, "Cannot get reset descriptor\n");
621 return PTR_ERR(gpio->rst);
622 }
623
624 err = reset_control_deassert(gpio->rst);
625 if (err) {
626 dev_err(gpio->dev, "Cannot deassert reset lane\n");
627 return err;
628 }
629
630 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
631}
632
Serge Semindaa3f582020-07-30 18:28:06 +0300633static void dwapb_disable_clks(void *data)
634{
635 struct dwapb_gpio *gpio = data;
636
637 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
638}
639
640static int dwapb_get_clks(struct dwapb_gpio *gpio)
641{
642 int err;
643
644 /* Optional bus and debounce clocks */
645 gpio->clks[0].id = "bus";
646 gpio->clks[1].id = "db";
647 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
648 gpio->clks);
649 if (err) {
650 dev_err(gpio->dev, "Cannot get APB/Debounce clocks\n");
651 return err;
652 }
653
654 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
655 if (err) {
656 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
657 return err;
658 }
659
660 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
661}
662
Hoan Trana72b8c42017-02-21 11:32:43 -0800663static const struct of_device_id dwapb_of_match[] = {
664 { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
665 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
666 { /* Sentinel */ }
667};
668MODULE_DEVICE_TABLE(of, dwapb_of_match);
669
670static const struct acpi_device_id dwapb_acpi_match[] = {
671 {"HISI0181", 0},
672 {"APMC0D07", 0},
673 {"APMC0D81", GPIO_REG_OFFSET_V2},
674 { }
675};
676MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
677
Jamie Iles7779b3452014-02-25 17:01:01 -0600678static int dwapb_gpio_probe(struct platform_device *pdev)
679{
Weike Chen3d2613c2014-09-17 09:18:39 -0700680 unsigned int i;
Jamie Iles7779b3452014-02-25 17:01:01 -0600681 struct dwapb_gpio *gpio;
Jamie Iles7779b3452014-02-25 17:01:01 -0600682 int err;
Weike Chen3d2613c2014-09-17 09:18:39 -0700683 struct device *dev = &pdev->dev;
684 struct dwapb_platform_data *pdata = dev_get_platdata(dev);
Jamie Iles7779b3452014-02-25 17:01:01 -0600685
Axel Linda9df932014-12-28 15:23:14 +0800686 if (!pdata) {
Jiang Qiu4ba8cfa2016-04-28 17:32:02 +0800687 pdata = dwapb_gpio_get_pdata(dev);
Weike Chen3d2613c2014-09-17 09:18:39 -0700688 if (IS_ERR(pdata))
689 return PTR_ERR(pdata);
690 }
Jamie Iles7779b3452014-02-25 17:01:01 -0600691
Axel Linda9df932014-12-28 15:23:14 +0800692 if (!pdata->nports)
693 return -ENODEV;
Weike Chen3d2613c2014-09-17 09:18:39 -0700694
695 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
Axel Linda9df932014-12-28 15:23:14 +0800696 if (!gpio)
697 return -ENOMEM;
698
Weike Chen3d2613c2014-09-17 09:18:39 -0700699 gpio->dev = &pdev->dev;
700 gpio->nr_ports = pdata->nports;
701
Serge Semin4731d802020-07-30 18:28:05 +0300702 err = dwapb_get_reset(gpio);
703 if (err)
704 return err;
Alan Tull07901a92017-10-11 11:34:44 -0500705
Weike Chen3d2613c2014-09-17 09:18:39 -0700706 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
Jamie Iles7779b3452014-02-25 17:01:01 -0600707 sizeof(*gpio->ports), GFP_KERNEL);
Axel Linda9df932014-12-28 15:23:14 +0800708 if (!gpio->ports)
709 return -ENOMEM;
Jamie Iles7779b3452014-02-25 17:01:01 -0600710
Enrico Weigelt, metux IT consult2a7194e2019-03-11 19:54:47 +0100711 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
Axel Linda9df932014-12-28 15:23:14 +0800712 if (IS_ERR(gpio->regs))
713 return PTR_ERR(gpio->regs);
Jamie Iles7779b3452014-02-25 17:01:01 -0600714
Serge Semindaa3f582020-07-30 18:28:06 +0300715 err = dwapb_get_clks(gpio);
716 if (err)
Serge Semin5c544c92020-03-23 22:54:00 +0300717 return err;
Phil Edworthye6bf3772018-03-12 18:30:56 +0000718
Andy Shevchenko9826bbe2020-04-15 17:15:27 +0300719 gpio->flags = (uintptr_t)device_get_match_data(dev);
Hoan Trana72b8c42017-02-21 11:32:43 -0800720
Weike Chen3d2613c2014-09-17 09:18:39 -0700721 for (i = 0; i < gpio->nr_ports; i++) {
722 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
Jamie Iles7779b3452014-02-25 17:01:01 -0600723 if (err)
Serge Seminfeeaefd2020-07-30 18:28:07 +0300724 return err;
Jamie Iles7779b3452014-02-25 17:01:01 -0600725 }
Jamie Iles7779b3452014-02-25 17:01:01 -0600726
727 return 0;
728}
729
Weike Chen1e960db2014-09-17 09:18:42 -0700730#ifdef CONFIG_PM_SLEEP
731static int dwapb_gpio_suspend(struct device *dev)
732{
Wolfram Sangdeb19ac2018-10-21 21:59:56 +0200733 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
Linus Walleij0f4630f2015-12-04 14:02:58 +0100734 struct gpio_chip *gc = &gpio->ports[0].gc;
Weike Chen1e960db2014-09-17 09:18:42 -0700735 unsigned long flags;
736 int i;
737
Linus Walleij0f4630f2015-12-04 14:02:58 +0100738 spin_lock_irqsave(&gc->bgpio_lock, flags);
Weike Chen1e960db2014-09-17 09:18:42 -0700739 for (i = 0; i < gpio->nr_ports; i++) {
740 unsigned int offset;
741 unsigned int idx = gpio->ports[i].idx;
742 struct dwapb_context *ctx = gpio->ports[i].ctx;
743
Linus Walleij89f99fe2018-02-08 17:03:58 +0100744 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
Weike Chen1e960db2014-09-17 09:18:42 -0700745 ctx->dir = dwapb_read(gpio, offset);
746
Linus Walleij89f99fe2018-02-08 17:03:58 +0100747 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
Weike Chen1e960db2014-09-17 09:18:42 -0700748 ctx->data = dwapb_read(gpio, offset);
749
Linus Walleij89f99fe2018-02-08 17:03:58 +0100750 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
Weike Chen1e960db2014-09-17 09:18:42 -0700751 ctx->ext = dwapb_read(gpio, offset);
752
753 /* Only port A can provide interrupts */
754 if (idx == 0) {
755 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
756 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
757 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
758 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
759 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
760
761 /* Mask out interrupts */
Andy Shevchenko1afbc802020-04-22 14:06:53 +0300762 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
Weike Chen1e960db2014-09-17 09:18:42 -0700763 }
764 }
Linus Walleij0f4630f2015-12-04 14:02:58 +0100765 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
Weike Chen1e960db2014-09-17 09:18:42 -0700766
Serge Semin5c544c92020-03-23 22:54:00 +0300767 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
Phil Edworthye6bf3772018-03-12 18:30:56 +0000768
Weike Chen1e960db2014-09-17 09:18:42 -0700769 return 0;
770}
771
772static int dwapb_gpio_resume(struct device *dev)
773{
Wolfram Sangdeb19ac2018-10-21 21:59:56 +0200774 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
Linus Walleij0f4630f2015-12-04 14:02:58 +0100775 struct gpio_chip *gc = &gpio->ports[0].gc;
Weike Chen1e960db2014-09-17 09:18:42 -0700776 unsigned long flags;
Serge Semin5c544c92020-03-23 22:54:00 +0300777 int i, err;
Weike Chen1e960db2014-09-17 09:18:42 -0700778
Serge Semin5c544c92020-03-23 22:54:00 +0300779 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
780 if (err) {
781 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
782 return err;
783 }
Phil Edworthye6bf3772018-03-12 18:30:56 +0000784
Linus Walleij0f4630f2015-12-04 14:02:58 +0100785 spin_lock_irqsave(&gc->bgpio_lock, flags);
Weike Chen1e960db2014-09-17 09:18:42 -0700786 for (i = 0; i < gpio->nr_ports; i++) {
787 unsigned int offset;
788 unsigned int idx = gpio->ports[i].idx;
789 struct dwapb_context *ctx = gpio->ports[i].ctx;
790
Linus Walleij89f99fe2018-02-08 17:03:58 +0100791 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
Weike Chen1e960db2014-09-17 09:18:42 -0700792 dwapb_write(gpio, offset, ctx->data);
793
Linus Walleij89f99fe2018-02-08 17:03:58 +0100794 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
Weike Chen1e960db2014-09-17 09:18:42 -0700795 dwapb_write(gpio, offset, ctx->dir);
796
Linus Walleij89f99fe2018-02-08 17:03:58 +0100797 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
Weike Chen1e960db2014-09-17 09:18:42 -0700798 dwapb_write(gpio, offset, ctx->ext);
799
800 /* Only port A can provide interrupts */
801 if (idx == 0) {
802 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
803 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
804 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
805 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
806 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
807
808 /* Clear out spurious interrupts */
809 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
810 }
811 }
Linus Walleij0f4630f2015-12-04 14:02:58 +0100812 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
Weike Chen1e960db2014-09-17 09:18:42 -0700813
814 return 0;
815}
816#endif
817
818static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
819 dwapb_gpio_resume);
820
Jamie Iles7779b3452014-02-25 17:01:01 -0600821static struct platform_driver dwapb_gpio_driver = {
822 .driver = {
Andy Shevchenkoc58220c2020-04-15 17:15:21 +0300823 .name = DWAPB_DRIVER_NAME,
Weike Chen1e960db2014-09-17 09:18:42 -0700824 .pm = &dwapb_gpio_pm_ops,
Andy Shevchenkoc59042e2020-04-15 17:15:31 +0300825 .of_match_table = dwapb_of_match,
826 .acpi_match_table = dwapb_acpi_match,
Jamie Iles7779b3452014-02-25 17:01:01 -0600827 },
828 .probe = dwapb_gpio_probe,
Jamie Iles7779b3452014-02-25 17:01:01 -0600829};
830
831module_platform_driver(dwapb_gpio_driver);
832
833MODULE_LICENSE("GPL");
834MODULE_AUTHOR("Jamie Iles");
835MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
Andy Shevchenkoc58220c2020-04-15 17:15:21 +0300836MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);