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Gregory CLEMENTe7822262018-03-15 16:57:25 +01001// SPDX-License-Identifier: GPL-2.0
Andrew Lunn7e0a6b82014-05-26 21:29:49 +02002/*
3 * Device Tree file for LaCie 5Big Network v2
4 *
5 * Copyright (C) 2014
6 *
7 * Andrew Lunn <andrew@lunn.ch>
8 *
9 * Based on netxbig_v2-setup.c,
10 * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
11 *
Andrew Lunn7e0a6b82014-05-26 21:29:49 +020012*/
13
14/dts-v1/;
15
16#include "kirkwood.dtsi"
17#include "kirkwood-6281.dtsi"
18#include "kirkwood-netxbig.dtsi"
19
20/ {
21 model = "LaCie 5Big Network v2";
22 compatible = "lacie,net5big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood";
23
24 memory {
25 device_type = "memory";
26 reg = <0x00000000 0x20000000>;
27 };
28
29};
30
31&regulators {
Simon Guinot2d4cd2c2014-07-08 16:42:24 +020032 regulator@2 {
33 compatible = "regulator-fixed";
34 reg = <2>;
35 regulator-name = "hdd1power";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 enable-active-high;
39 regulator-always-on;
40 regulator-boot-on;
41 gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
42 };
43
Andrew Lunn7e0a6b82014-05-26 21:29:49 +020044 regulator@3 {
45 compatible = "regulator-fixed";
46 reg = <3>;
47 regulator-name = "hdd2power";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 enable-active-high;
51 regulator-always-on;
52 regulator-boot-on;
Jason Cooperd854fa82014-06-21 19:21:13 +000053 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
Andrew Lunn7e0a6b82014-05-26 21:29:49 +020054 };
55
56 regulator@4 {
57 compatible = "regulator-fixed";
58 reg = <4>;
59 regulator-name = "hdd3power";
60 regulator-min-microvolt = <5000000>;
61 regulator-max-microvolt = <5000000>;
62 enable-active-high;
63 regulator-always-on;
64 regulator-boot-on;
Jason Cooperd854fa82014-06-21 19:21:13 +000065 gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
Andrew Lunn7e0a6b82014-05-26 21:29:49 +020066 };
67
68 regulator@5 {
69 compatible = "regulator-fixed";
70 reg = <5>;
71 regulator-name = "hdd4power";
72 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <5000000>;
74 enable-active-high;
75 regulator-always-on;
76 regulator-boot-on;
Jason Cooperd854fa82014-06-21 19:21:13 +000077 gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
Andrew Lunn7e0a6b82014-05-26 21:29:49 +020078 };
Simon Guinot2d4cd2c2014-07-08 16:42:24 +020079
80 clocks {
Krzysztof Kozlowskieab1e912022-10-02 11:20:05 +020081 g762_clk: g762-oscillator {
82 compatible = "fixed-clock";
83 #clock-cells = <0>;
84 clock-frequency = <32768>;
85 };
Simon Guinot2d4cd2c2014-07-08 16:42:24 +020086 };
Simon Guinot767361f2015-09-26 23:02:35 +020087
88 netxbig-leds {
89 blue-sata2 {
90 label = "netxbig:blue:sata2";
91 mode-addr = <5>;
92 mode-val = <NETXBIG_LED_OFF 0
93 NETXBIG_LED_ON 7
94 NETXBIG_LED_SATA 1
95 NETXBIG_LED_TIMER1 3>;
96 bright-addr = <2>;
97 max-brightness = <7>;
98 };
99 red-sata2 {
100 label = "netxbig:red:sata2";
101 mode-addr = <5>;
102 mode-val = <NETXBIG_LED_OFF 0
103 NETXBIG_LED_ON 2
104 NETXBIG_LED_TIMER1 4>;
105 bright-addr = <2>;
106 max-brightness = <7>;
107 };
108 blue-sata3 {
109 label = "netxbig:blue:sata3";
110 mode-addr = <6>;
111 mode-val = <NETXBIG_LED_OFF 0
112 NETXBIG_LED_ON 7
113 NETXBIG_LED_SATA 1
114 NETXBIG_LED_TIMER1 3>;
115 bright-addr = <2>;
116 max-brightness = <7>;
117 };
118 red-sata3 {
119 label = "netxbig:red:sata3";
120 mode-addr = <6>;
121 mode-val = <NETXBIG_LED_OFF 0
122 NETXBIG_LED_ON 2
123 NETXBIG_LED_TIMER1 4>;
124 bright-addr = <2>;
125 max-brightness = <7>;
126 };
127 blue-sata4 {
128 label = "netxbig:blue:sata4";
129 mode-addr = <7>;
130 mode-val = <NETXBIG_LED_OFF 0
131 NETXBIG_LED_ON 7
132 NETXBIG_LED_SATA 1
133 NETXBIG_LED_TIMER1 3>;
134 bright-addr = <2>;
135 max-brightness = <7>;
136 };
137 red-sata4 {
138 label = "netxbig:red:sata4";
139 mode-addr = <7>;
140 mode-val = <NETXBIG_LED_OFF 0
141 NETXBIG_LED_ON 2
142 NETXBIG_LED_TIMER1 4>;
143 bright-addr = <2>;
144 max-brightness = <7>;
145 };
146 };
Andrew Lunn7e0a6b82014-05-26 21:29:49 +0200147};
148
149&mdio {
150 ethphy1: ethernet-phy@1 {
151 reg = <0>;
152 };
153};
154
155&eth1 {
156 status = "okay";
157 ethernet1-port@0 {
158 phy-handle = <&ethphy1>;
159 };
160};
161
Simon Guinot2d4cd2c2014-07-08 16:42:24 +0200162
163&i2c0 {
164 g762@3e {
165 compatible = "gmt,g762";
166 reg = <0x3e>;
167 clocks = <&g762_clk>;
168 };
169};