blob: d3090a7537bb9576c89f69d17541eadbf9353d8c [file] [log] [blame]
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001/*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
David Howells760285e2012-10-02 18:01:07 +010032#include <drm/drmP.h>
Ben Widawsky714244e2017-08-01 09:58:16 -070033#include <drm/drm_atomic_helper.h>
David Howells760285e2012-10-02 18:01:07 +010034#include <drm/drm_crtc.h>
35#include <drm/drm_fourcc.h>
Ville Syrjälä17316932013-04-24 18:52:38 +030036#include <drm/drm_rect.h>
Chandra Konduruc3318792015-04-15 15:15:02 -070037#include <drm/drm_atomic.h>
Matt Roperea2c67b2014-12-23 10:41:52 -080038#include <drm/drm_plane_helper.h>
Jesse Barnesb840d907f2011-12-13 13:19:38 -080039#include "intel_drv.h"
Chris Wilson5d723d72016-08-04 16:32:35 +010040#include "intel_frontbuffer.h"
David Howells760285e2012-10-02 18:01:07 +010041#include <drm/i915_drm.h>
Jesse Barnesb840d907f2011-12-13 13:19:38 -080042#include "i915_drv.h"
43
Ville Syrjälädfd2e9a2016-05-18 11:34:38 +030044int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
45 int usecs)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030046{
47 /* paranoia */
Ville Syrjälä5e7234c2015-09-25 16:37:43 +030048 if (!adjusted_mode->crtc_htotal)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030049 return 1;
50
Ville Syrjälä5e7234c2015-09-25 16:37:43 +030051 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
52 1000 * adjusted_mode->crtc_htotal);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030053}
54
Daniel Vetter69208c92017-10-10 11:18:16 +020055/* FIXME: We should instead only take spinlocks once for the entire update
56 * instead of once per mmio. */
57#if IS_ENABLED(CONFIG_PROVE_LOCKING)
58#define VBLANK_EVASION_TIME_US 250
59#else
Maarten Lankhorste1edbd42017-02-28 15:28:48 +010060#define VBLANK_EVASION_TIME_US 100
Daniel Vetter69208c92017-10-10 11:18:16 +020061#endif
Maarten Lankhorste1edbd42017-02-28 15:28:48 +010062
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +020063/**
64 * intel_pipe_update_start() - start update of a set of display registers
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +030065 * @new_crtc_state: the new crtc state
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +020066 *
67 * Mark the start of an update to pipe registers that should be updated
68 * atomically regarding vblank. If the next vblank will happens within
69 * the next 100 us, this function waits until the vblank passes.
70 *
71 * After a successful call to this function, interrupts will be disabled
72 * until a subsequent call to intel_pipe_update_end(). That is done to
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +030073 * avoid random delays.
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +020074 */
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +030075void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030076{
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +030077 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
Ville Syrjäläec1b4ee2016-12-15 19:47:34 +020078 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +030079 const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030080 long timeout = msecs_to_jiffies_timeout(1);
81 int scanline, min, max, vblank_start;
Ville Syrjälä210871b62014-05-22 19:00:50 +030082 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
Ville Syrjäläec1b4ee2016-12-15 19:47:34 +020083 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +030084 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030085 DEFINE_WAIT(wait);
Dhinakaran Pandiyan63ec1322018-08-21 15:11:54 -070086 u32 psr_status;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030087
Ville Syrjälä124abe02015-09-08 13:40:45 +030088 vblank_start = adjusted_mode->crtc_vblank_start;
89 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030090 vblank_start = DIV_ROUND_UP(vblank_start, 2);
91
92 /* FIXME needs to be calibrated sensibly */
Maarten Lankhorste1edbd42017-02-28 15:28:48 +010093 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
94 VBLANK_EVASION_TIME_US);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030095 max = vblank_start - 1;
96
97 if (min <= 0 || max <= 0)
Tarun Vyasa6089872018-06-27 13:02:50 -070098 goto irq_disable;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030099
Daniel Vetter1e3feef2015-02-13 21:03:45 +0100100 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
Tarun Vyasa6089872018-06-27 13:02:50 -0700101 goto irq_disable;
102
103 /*
104 * Wait for psr to idle out after enabling the VBL interrupts
105 * VBL interrupts will start the PSR exit and prevent a PSR
106 * re-entry as well.
107 */
Dhinakaran Pandiyan63ec1322018-08-21 15:11:54 -0700108 if (intel_psr_wait_for_idle(new_crtc_state, &psr_status))
109 DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n",
110 psr_status);
Tarun Vyasa6089872018-06-27 13:02:50 -0700111
112 local_irq_disable();
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300113
Jesse Barnesd637ce32015-09-17 08:08:32 -0700114 crtc->debug.min_vbl = min;
115 crtc->debug.max_vbl = max;
116 trace_i915_pipe_update_start(crtc);
Ville Syrjälä25ef2842014-04-29 13:35:48 +0300117
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300118 for (;;) {
119 /*
120 * prepare_to_wait() has a memory barrier, which guarantees
121 * other CPUs can see the task state update by the time we
122 * read the scanline.
123 */
Ville Syrjälä210871b62014-05-22 19:00:50 +0300124 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300125
126 scanline = intel_get_crtc_scanline(crtc);
127 if (scanline < min || scanline > max)
128 break;
129
Tarun9ba59b72018-05-02 16:33:00 -0700130 if (!timeout) {
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300131 DRM_ERROR("Potential atomic update failure on pipe %c\n",
132 pipe_name(crtc->pipe));
133 break;
134 }
135
136 local_irq_enable();
137
138 timeout = schedule_timeout(timeout);
139
140 local_irq_disable();
141 }
142
Ville Syrjälä210871b62014-05-22 19:00:50 +0300143 finish_wait(wq, &wait);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300144
Daniel Vetter1e3feef2015-02-13 21:03:45 +0100145 drm_crtc_vblank_put(&crtc->base);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300146
Ville Syrjäläec1b4ee2016-12-15 19:47:34 +0200147 /*
148 * On VLV/CHV DSI the scanline counter would appear to
149 * increment approx. 1/3 of a scanline before start of vblank.
150 * The registers still get latched at start of vblank however.
151 * This means we must not write any registers on the first
152 * line of vblank (since not the whole line is actually in
153 * vblank). And unfortunately we can't use the interrupt to
154 * wait here since it will fire too soon. We could use the
155 * frame start interrupt instead since it will fire after the
156 * critical scanline, but that would require more changes
157 * in the interrupt code. So for now we'll just do the nasty
158 * thing and poll for the bad scanline to pass us by.
159 *
160 * FIXME figure out if BXT+ DSI suffers from this as well
161 */
162 while (need_vlv_dsi_wa && scanline == vblank_start)
163 scanline = intel_get_crtc_scanline(crtc);
164
Jesse Barneseb120ef2015-09-15 14:19:32 -0700165 crtc->debug.scanline_start = scanline;
166 crtc->debug.start_vbl_time = ktime_get();
Maarten Lankhorsta2991412016-05-17 15:07:48 +0200167 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300168
Jesse Barnesd637ce32015-09-17 08:08:32 -0700169 trace_i915_pipe_update_vblank_evaded(crtc);
Tarun Vyasa6089872018-06-27 13:02:50 -0700170 return;
171
172irq_disable:
173 local_irq_disable();
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300174}
175
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +0200176/**
177 * intel_pipe_update_end() - end update of a set of display registers
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +0300178 * @new_crtc_state: the new crtc state
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +0200179 *
180 * Mark the end of an update started with intel_pipe_update_start(). This
181 * re-enables interrupts and verifies the update was actually completed
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +0300182 * before a vblank.
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +0200183 */
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +0300184void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300185{
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +0300186 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300187 enum pipe pipe = crtc->pipe;
Jesse Barneseb120ef2015-09-15 14:19:32 -0700188 int scanline_end = intel_get_crtc_scanline(crtc);
Maarten Lankhorsta2991412016-05-17 15:07:48 +0200189 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
Maarten Lankhorst85a62bf2015-09-01 12:15:33 +0200190 ktime_t end_vbl_time = ktime_get();
Bing Niua94f2b92017-03-08 15:14:03 -0500191 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300192
Jesse Barnesd637ce32015-09-17 08:08:32 -0700193 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
Ville Syrjälä25ef2842014-04-29 13:35:48 +0300194
Daniel Vetter1f7528c2016-06-13 16:13:45 +0200195 /* We're still in the vblank-evade critical section, this can't race.
196 * Would be slightly nice to just grab the vblank count and arm the
197 * event outside of the critical section - the spinlock might spin for a
198 * while ... */
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +0300199 if (new_crtc_state->base.event) {
Daniel Vetter1f7528c2016-06-13 16:13:45 +0200200 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
201
202 spin_lock(&crtc->base.dev->event_lock);
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +0300203 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
Daniel Vetter1f7528c2016-06-13 16:13:45 +0200204 spin_unlock(&crtc->base.dev->event_lock);
205
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +0300206 new_crtc_state->base.event = NULL;
Daniel Vetter1f7528c2016-06-13 16:13:45 +0200207 }
208
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300209 local_irq_enable();
210
Bing Niua94f2b92017-03-08 15:14:03 -0500211 if (intel_vgpu_active(dev_priv))
212 return;
213
Jesse Barneseb120ef2015-09-15 14:19:32 -0700214 if (crtc->debug.start_vbl_count &&
215 crtc->debug.start_vbl_count != end_vbl_count) {
216 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
217 pipe_name(pipe), crtc->debug.start_vbl_count,
218 end_vbl_count,
219 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
220 crtc->debug.min_vbl, crtc->debug.max_vbl,
221 crtc->debug.scanline_start, scanline_end);
Ville Syrjälä7b8cd332017-05-07 20:12:52 +0300222 }
223#ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
224 else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
225 VBLANK_EVASION_TIME_US)
Maarten Lankhorste1edbd42017-02-28 15:28:48 +0100226 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
227 pipe_name(pipe),
228 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
229 VBLANK_EVASION_TIME_US);
Ville Syrjälä7b8cd332017-05-07 20:12:52 +0300230#endif
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300231}
232
Ville Syrjälä3f6d5ba2018-09-18 17:02:43 +0300233int intel_plane_check_stride(const struct intel_plane_state *plane_state)
234{
235 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
236 const struct drm_framebuffer *fb = plane_state->base.fb;
237 unsigned int rotation = plane_state->base.rotation;
238 u32 stride, max_stride;
239
240 /* FIXME other color planes? */
241 stride = plane_state->color_plane[0].stride;
242 max_stride = plane->max_stride(plane, fb->format->format,
243 fb->modifier, rotation);
244
245 if (stride > max_stride) {
246 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
247 fb->base.id, stride,
248 plane->base.base.id, plane->base.name, max_stride);
249 return -EINVAL;
250 }
251
252 return 0;
253}
254
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +0300255int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
256{
257 const struct drm_framebuffer *fb = plane_state->base.fb;
258 struct drm_rect *src = &plane_state->base.src;
259 u32 src_x, src_y, src_w, src_h;
260
261 /*
262 * Hardware doesn't handle subpixel coordinates.
263 * Adjust to (macro)pixel boundary, but be careful not to
264 * increase the source viewport size, because that could
265 * push the downscaling factor out of bounds.
266 */
267 src_x = src->x1 >> 16;
268 src_w = drm_rect_width(src) >> 16;
269 src_y = src->y1 >> 16;
270 src_h = drm_rect_height(src) >> 16;
271
272 src->x1 = src_x << 16;
273 src->x2 = (src_x + src_w) << 16;
274 src->y1 = src_y << 16;
275 src->y2 = (src_y + src_h) << 16;
276
277 if (fb->format->is_yuv &&
278 fb->format->format != DRM_FORMAT_NV12 &&
279 (src_x & 1 || src_w & 1)) {
280 DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
281 src_x, src_w);
282 return -EINVAL;
283 }
284
285 return 0;
286}
287
Ville Syrjäläddd57132018-09-07 18:24:02 +0300288unsigned int
289skl_plane_max_stride(struct intel_plane *plane,
290 u32 pixel_format, u64 modifier,
291 unsigned int rotation)
292{
293 int cpp = drm_format_plane_cpp(pixel_format, 0);
294
295 /*
296 * "The stride in bytes must not exceed the
297 * of the size of 8K pixels and 32K bytes."
298 */
299 if (drm_rotation_90_or_270(rotation))
300 return min(8192, 32768 / cpp);
301 else
302 return min(8192 * cpp, 32768);
303}
304
Maarten Lankhorst2a277792018-11-14 13:49:23 +0200305static void
Ville Syrjälä27971d62018-11-14 13:49:24 +0200306skl_program_scaler(struct intel_plane *plane,
Maarten Lankhorst2a277792018-11-14 13:49:23 +0200307 const struct intel_crtc_state *crtc_state,
308 const struct intel_plane_state *plane_state)
309{
Ville Syrjälä27971d62018-11-14 13:49:24 +0200310 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
Maarten Lankhorst2a277792018-11-14 13:49:23 +0200311 enum pipe pipe = plane->pipe;
312 int scaler_id = plane_state->scaler_id;
313 const struct intel_scaler *scaler =
314 &crtc_state->scaler_state.scalers[scaler_id];
315 int crtc_x = plane_state->base.dst.x1;
316 int crtc_y = plane_state->base.dst.y1;
317 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
318 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
319 u16 y_hphase, uv_rgb_hphase;
320 u16 y_vphase, uv_rgb_vphase;
Ville Syrjälä6e8adf62018-11-14 15:32:55 +0200321 int hscale, vscale;
322
323 hscale = drm_rect_calc_hscale(&plane_state->base.src,
324 &plane_state->base.dst,
325 0, INT_MAX);
326 vscale = drm_rect_calc_vscale(&plane_state->base.src,
327 &plane_state->base.dst,
328 0, INT_MAX);
Maarten Lankhorst2a277792018-11-14 13:49:23 +0200329
Maarten Lankhorst2a277792018-11-14 13:49:23 +0200330 /* TODO: handle sub-pixel coordinates */
331 if (plane_state->base.fb->format->format == DRM_FORMAT_NV12) {
Ville Syrjälä6e8adf62018-11-14 15:32:55 +0200332 y_hphase = skl_scaler_calc_phase(1, hscale, false);
333 y_vphase = skl_scaler_calc_phase(1, vscale, false);
Maarten Lankhorst2a277792018-11-14 13:49:23 +0200334
335 /* MPEG2 chroma siting convention */
Ville Syrjälä6e8adf62018-11-14 15:32:55 +0200336 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
337 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
Maarten Lankhorst2a277792018-11-14 13:49:23 +0200338 } else {
339 /* not used */
340 y_hphase = 0;
341 y_vphase = 0;
342
Ville Syrjälä6e8adf62018-11-14 15:32:55 +0200343 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
344 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
Maarten Lankhorst2a277792018-11-14 13:49:23 +0200345 }
346
347 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
Ville Syrjälä27971d62018-11-14 13:49:24 +0200348 PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode);
Maarten Lankhorst2a277792018-11-14 13:49:23 +0200349 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
350 I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id),
351 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
352 I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id),
353 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
354 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
Ville Syrjälä27971d62018-11-14 13:49:24 +0200355 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h);
Maarten Lankhorst2a277792018-11-14 13:49:23 +0200356}
357
Juha-Pekka Heikkila9a8cc572017-10-17 23:08:09 +0300358void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300359skl_update_plane(struct intel_plane *plane,
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100360 const struct intel_crtc_state *crtc_state,
361 const struct intel_plane_state *plane_state)
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000362{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300363 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300364 enum plane_id plane_id = plane->id;
365 enum pipe pipe = plane->pipe;
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200366 u32 plane_ctl = plane_state->ctl;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100367 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
Ville Syrjäläc11ada02018-09-07 18:24:04 +0300368 u32 surf_addr = plane_state->color_plane[0].offset;
Ville Syrjälädf79cf42018-09-11 18:01:39 +0300369 u32 stride = skl_plane_stride(plane_state, 0);
370 u32 aux_stride = skl_plane_stride(plane_state, 1);
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300371 int crtc_x = plane_state->base.dst.x1;
372 int crtc_y = plane_state->base.dst.y1;
Ville Syrjäläc11ada02018-09-07 18:24:04 +0300373 uint32_t x = plane_state->color_plane[0].x;
374 uint32_t y = plane_state->color_plane[0].y;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300375 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
376 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200377 unsigned long irqflags;
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000378
Ville Syrjälä6687c902015-09-15 13:16:41 +0300379 /* Sizes are 0 based */
380 src_w--;
381 src_h--;
Ville Syrjälä6687c902015-09-15 13:16:41 +0300382
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200383 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
384
James Ausmus4036c782017-11-13 10:11:28 -0800385 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200386 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
James Ausmus4036c782017-11-13 10:11:28 -0800387 plane_state->color_ctl);
Ville Syrjälä38f24f22018-02-14 21:23:24 +0200388
Ville Syrjälä78587de2017-03-09 17:44:32 +0200389 if (key->flags) {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200390 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
391 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
392 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
Ville Syrjälä78587de2017-03-09 17:44:32 +0200393 }
394
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200395 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
396 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
397 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
Ville Syrjälä2e2adb02017-08-01 09:58:13 -0700398 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
Ville Syrjäläc11ada02018-09-07 18:24:04 +0300399 (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
Ville Syrjälä2e2adb02017-08-01 09:58:13 -0700400 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
Ville Syrjäläc11ada02018-09-07 18:24:04 +0300401 (plane_state->color_plane[1].y << 16) |
402 plane_state->color_plane[1].x);
Chandra Konduruc3318792015-04-15 15:15:02 -0700403
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100404 if (plane_state->scaler_id >= 0) {
Ville Syrjälä27971d62018-11-14 13:49:24 +0200405 skl_program_scaler(plane, crtc_state, plane_state);
Chandra Konduruc3318792015-04-15 15:15:02 -0700406
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200407 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
Chandra Konduruc3318792015-04-15 15:15:02 -0700408 } else {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200409 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
Chandra Konduruc3318792015-04-15 15:15:02 -0700410 }
411
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200412 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
413 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
414 intel_plane_ggtt_offset(plane_state) + surf_addr);
415 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
416
417 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000418}
419
Juha-Pekka Heikkila779d4d82017-10-17 23:08:10 +0300420void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300421skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000422{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300423 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
424 enum plane_id plane_id = plane->id;
425 enum pipe pipe = plane->pipe;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200426 unsigned long irqflags;
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000427
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200428 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000429
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200430 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
431
432 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
433 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
434
435 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000436}
437
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200438bool
Ville Syrjäläeade6c82018-01-30 22:38:03 +0200439skl_plane_get_hw_state(struct intel_plane *plane,
440 enum pipe *pipe)
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200441{
442 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
443 enum intel_display_power_domain power_domain;
444 enum plane_id plane_id = plane->id;
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200445 bool ret;
446
Ville Syrjäläeade6c82018-01-30 22:38:03 +0200447 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200448 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
449 return false;
450
Ville Syrjäläeade6c82018-01-30 22:38:03 +0200451 ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
452
453 *pipe = plane->pipe;
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200454
455 intel_display_power_put(dev_priv, power_domain);
456
457 return ret;
458}
459
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000460static void
Ville Syrjälä5deae912018-02-14 21:23:23 +0200461chv_update_csc(const struct intel_plane_state *plane_state)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300462{
Ville Syrjälä5deae912018-02-14 21:23:23 +0200463 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300464 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
Ville Syrjälä5deae912018-02-14 21:23:23 +0200465 const struct drm_framebuffer *fb = plane_state->base.fb;
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300466 enum plane_id plane_id = plane->id;
Ville Syrjäläb0f5c0b2018-02-14 21:23:25 +0200467 /*
468 * |r| | c0 c1 c2 | |cr|
469 * |g| = | c3 c4 c5 | x |y |
470 * |b| | c6 c7 c8 | |cb|
471 *
472 * Coefficients are s3.12.
473 *
474 * Cb and Cr apparently come in as signed already, and
475 * we always get full range data in on account of CLRC0/1.
476 */
477 static const s16 csc_matrix[][9] = {
478 /* BT.601 full range YCbCr -> full range RGB */
479 [DRM_COLOR_YCBCR_BT601] = {
480 5743, 4096, 0,
481 -2925, 4096, -1410,
482 0, 4096, 7258,
483 },
484 /* BT.709 full range YCbCr -> full range RGB */
485 [DRM_COLOR_YCBCR_BT709] = {
486 6450, 4096, 0,
487 -1917, 4096, -767,
488 0, 4096, 7601,
489 },
490 };
491 const s16 *csc = csc_matrix[plane_state->base.color_encoding];
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300492
493 /* Seems RGB data bypasses the CSC always */
Ayan Kumar Halder9bace652018-07-17 18:13:43 +0100494 if (!fb->format->is_yuv)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300495 return;
496
Ville Syrjälä5deae912018-02-14 21:23:23 +0200497 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200498 I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
499 I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300500
Ville Syrjäläb0f5c0b2018-02-14 21:23:25 +0200501 I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0]));
502 I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2]));
503 I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4]));
504 I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6]));
505 I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8]));
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300506
Ville Syrjälä5deae912018-02-14 21:23:23 +0200507 I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
508 I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
509 I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300510
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200511 I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
512 I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
513 I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300514}
515
Ville Syrjälä5deae912018-02-14 21:23:23 +0200516#define SIN_0 0
517#define COS_0 1
518
519static void
520vlv_update_clrc(const struct intel_plane_state *plane_state)
521{
522 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
523 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
524 const struct drm_framebuffer *fb = plane_state->base.fb;
525 enum pipe pipe = plane->pipe;
526 enum plane_id plane_id = plane->id;
527 int contrast, brightness, sh_scale, sh_sin, sh_cos;
528
Ayan Kumar Halder9bace652018-07-17 18:13:43 +0100529 if (fb->format->is_yuv &&
Ville Syrjäläc8624ed2018-02-14 21:23:27 +0200530 plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
Ville Syrjälä5deae912018-02-14 21:23:23 +0200531 /*
532 * Expand limited range to full range:
533 * Contrast is applied first and is used to expand Y range.
534 * Brightness is applied second and is used to remove the
535 * offset from Y. Saturation/hue is used to expand CbCr range.
536 */
537 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
538 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
539 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
540 sh_sin = SIN_0 * sh_scale;
541 sh_cos = COS_0 * sh_scale;
542 } else {
543 /* Pass-through everything. */
544 contrast = 1 << 6;
545 brightness = 0;
546 sh_scale = 1 << 7;
547 sh_sin = SIN_0 * sh_scale;
548 sh_cos = COS_0 * sh_scale;
549 }
550
551 /* FIXME these register are single buffered :( */
552 I915_WRITE_FW(SPCLRC0(pipe, plane_id),
553 SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
554 I915_WRITE_FW(SPCLRC1(pipe, plane_id),
555 SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
556}
557
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200558static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
559 const struct intel_plane_state *plane_state)
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700560{
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200561 const struct drm_framebuffer *fb = plane_state->base.fb;
Ville Syrjälä11df4d92016-11-07 22:20:55 +0200562 unsigned int rotation = plane_state->base.rotation;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100563 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200564 u32 sprctl;
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700565
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200566 sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700567
Ville Syrjälä438b74a2016-12-14 23:32:55 +0200568 switch (fb->format->format) {
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700569 case DRM_FORMAT_YUYV:
570 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
571 break;
572 case DRM_FORMAT_YVYU:
573 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
574 break;
575 case DRM_FORMAT_UYVY:
576 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
577 break;
578 case DRM_FORMAT_VYUY:
579 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
580 break;
581 case DRM_FORMAT_RGB565:
582 sprctl |= SP_FORMAT_BGR565;
583 break;
584 case DRM_FORMAT_XRGB8888:
585 sprctl |= SP_FORMAT_BGRX8888;
586 break;
587 case DRM_FORMAT_ARGB8888:
588 sprctl |= SP_FORMAT_BGRA8888;
589 break;
590 case DRM_FORMAT_XBGR2101010:
591 sprctl |= SP_FORMAT_RGBX1010102;
592 break;
593 case DRM_FORMAT_ABGR2101010:
594 sprctl |= SP_FORMAT_RGBA1010102;
595 break;
596 case DRM_FORMAT_XBGR8888:
597 sprctl |= SP_FORMAT_RGBX8888;
598 break;
599 case DRM_FORMAT_ABGR8888:
600 sprctl |= SP_FORMAT_RGBA8888;
601 break;
602 default:
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200603 MISSING_CASE(fb->format->format);
604 return 0;
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700605 }
606
Ville Syrjäläb0f5c0b2018-02-14 21:23:25 +0200607 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
608 sprctl |= SP_YUV_FORMAT_BT709;
609
Ville Syrjäläbae781b2016-11-16 13:33:16 +0200610 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700611 sprctl |= SP_TILED;
612
Robert Fossc2c446a2017-05-19 16:50:17 -0400613 if (rotation & DRM_MODE_ROTATE_180)
Ville Syrjälädf0cd452016-11-14 18:53:59 +0200614 sprctl |= SP_ROTATE_180;
615
Robert Fossc2c446a2017-05-19 16:50:17 -0400616 if (rotation & DRM_MODE_REFLECT_X)
Ville Syrjälä4ea7be22016-11-14 18:54:00 +0200617 sprctl |= SP_MIRROR;
618
Ville Syrjälä78587de2017-03-09 17:44:32 +0200619 if (key->flags & I915_SET_COLORKEY_SOURCE)
620 sprctl |= SP_SOURCE_KEY;
621
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200622 return sprctl;
623}
624
625static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300626vlv_update_plane(struct intel_plane *plane,
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200627 const struct intel_crtc_state *crtc_state,
628 const struct intel_plane_state *plane_state)
629{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300630 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
631 const struct drm_framebuffer *fb = plane_state->base.fb;
632 enum pipe pipe = plane->pipe;
633 enum plane_id plane_id = plane->id;
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200634 u32 sprctl = plane_state->ctl;
Ville Syrjäläc11ada02018-09-07 18:24:04 +0300635 u32 sprsurf_offset = plane_state->color_plane[0].offset;
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200636 u32 linear_offset;
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200637 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
638 int crtc_x = plane_state->base.dst.x1;
639 int crtc_y = plane_state->base.dst.y1;
640 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
641 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
Ville Syrjäläc11ada02018-09-07 18:24:04 +0300642 uint32_t x = plane_state->color_plane[0].x;
643 uint32_t y = plane_state->color_plane[0].y;
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200644 unsigned long irqflags;
645
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700646 /* Sizes are 0 based */
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700647 crtc_w--;
648 crtc_h--;
649
Ville Syrjälä29490562016-01-20 18:02:50 +0200650 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
Ville Syrjälä6687c902015-09-15 13:16:41 +0300651
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200652 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
653
Ville Syrjälä5deae912018-02-14 21:23:23 +0200654 vlv_update_clrc(plane_state);
655
Ville Syrjälä78587de2017-03-09 17:44:32 +0200656 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
Ville Syrjälä5deae912018-02-14 21:23:23 +0200657 chv_update_csc(plane_state);
Ville Syrjälä78587de2017-03-09 17:44:32 +0200658
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200659 if (key->flags) {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200660 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
661 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
662 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200663 }
Ville Syrjälädf79cf42018-09-11 18:01:39 +0300664 I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
665 plane_state->color_plane[0].stride);
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200666 I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
Ville Syrjäläca6ad022014-01-17 20:09:03 +0200667
Ville Syrjäläbae781b2016-11-16 13:33:16 +0200668 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200669 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700670 else
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200671 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700672
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200673 I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
Ville Syrjäläc14b0482014-10-16 20:52:34 +0300674
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200675 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
676 I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
677 I915_WRITE_FW(SPSURF(pipe, plane_id),
678 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
679 POSTING_READ_FW(SPSURF(pipe, plane_id));
680
681 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700682}
683
684static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300685vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700686{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300687 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
688 enum pipe pipe = plane->pipe;
689 enum plane_id plane_id = plane->id;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200690 unsigned long irqflags;
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700691
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200692 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
Ville Syrjälä48fe4692015-03-19 17:57:13 +0200693
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200694 I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
695
696 I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
697 POSTING_READ_FW(SPSURF(pipe, plane_id));
698
699 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700700}
701
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200702static bool
Ville Syrjäläeade6c82018-01-30 22:38:03 +0200703vlv_plane_get_hw_state(struct intel_plane *plane,
704 enum pipe *pipe)
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200705{
706 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
707 enum intel_display_power_domain power_domain;
708 enum plane_id plane_id = plane->id;
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200709 bool ret;
710
Ville Syrjäläeade6c82018-01-30 22:38:03 +0200711 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200712 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
713 return false;
714
Ville Syrjäläeade6c82018-01-30 22:38:03 +0200715 ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
716
717 *pipe = plane->pipe;
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200718
719 intel_display_power_put(dev_priv, power_domain);
720
721 return ret;
722}
723
Ville Syrjälä45dea7b2017-03-17 23:17:59 +0200724static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
725 const struct intel_plane_state *plane_state)
726{
727 struct drm_i915_private *dev_priv =
728 to_i915(plane_state->base.plane->dev);
729 const struct drm_framebuffer *fb = plane_state->base.fb;
730 unsigned int rotation = plane_state->base.rotation;
731 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
732 u32 sprctl;
733
734 sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
735
736 if (IS_IVYBRIDGE(dev_priv))
737 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
738
739 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
740 sprctl |= SPRITE_PIPE_CSC_ENABLE;
741
742 switch (fb->format->format) {
743 case DRM_FORMAT_XBGR8888:
744 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
745 break;
746 case DRM_FORMAT_XRGB8888:
747 sprctl |= SPRITE_FORMAT_RGBX888;
748 break;
749 case DRM_FORMAT_YUYV:
750 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
751 break;
752 case DRM_FORMAT_YVYU:
753 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
754 break;
755 case DRM_FORMAT_UYVY:
756 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
757 break;
758 case DRM_FORMAT_VYUY:
759 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
760 break;
761 default:
762 MISSING_CASE(fb->format->format);
763 return 0;
764 }
765
Ville Syrjäläb0f5c0b2018-02-14 21:23:25 +0200766 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
767 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
768
Ville Syrjäläc8624ed2018-02-14 21:23:27 +0200769 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
770 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
771
Ville Syrjälä45dea7b2017-03-17 23:17:59 +0200772 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
773 sprctl |= SPRITE_TILED;
774
Robert Fossc2c446a2017-05-19 16:50:17 -0400775 if (rotation & DRM_MODE_ROTATE_180)
Ville Syrjälä45dea7b2017-03-17 23:17:59 +0200776 sprctl |= SPRITE_ROTATE_180;
777
778 if (key->flags & I915_SET_COLORKEY_DESTINATION)
779 sprctl |= SPRITE_DEST_KEY;
780 else if (key->flags & I915_SET_COLORKEY_SOURCE)
781 sprctl |= SPRITE_SOURCE_KEY;
782
783 return sprctl;
784}
785
Jesse Barnes7f1f38512013-04-02 11:22:20 -0700786static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300787ivb_update_plane(struct intel_plane *plane,
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100788 const struct intel_crtc_state *crtc_state,
789 const struct intel_plane_state *plane_state)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800790{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300791 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
792 const struct drm_framebuffer *fb = plane_state->base.fb;
793 enum pipe pipe = plane->pipe;
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200794 u32 sprctl = plane_state->ctl, sprscale = 0;
Ville Syrjäläc11ada02018-09-07 18:24:04 +0300795 u32 sprsurf_offset = plane_state->color_plane[0].offset;
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200796 u32 linear_offset;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100797 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300798 int crtc_x = plane_state->base.dst.x1;
799 int crtc_y = plane_state->base.dst.y1;
800 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
801 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
Ville Syrjäläc11ada02018-09-07 18:24:04 +0300802 uint32_t x = plane_state->color_plane[0].x;
803 uint32_t y = plane_state->color_plane[0].y;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300804 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
805 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200806 unsigned long irqflags;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800807
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800808 /* Sizes are 0 based */
809 src_w--;
810 src_h--;
811 crtc_w--;
812 crtc_h--;
813
Ville Syrjälä8553c182013-12-05 15:51:39 +0200814 if (crtc_w != src_w || crtc_h != src_h)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800815 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800816
Ville Syrjälä29490562016-01-20 18:02:50 +0200817 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
Ville Syrjälä6687c902015-09-15 13:16:41 +0300818
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200819 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
820
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200821 if (key->flags) {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200822 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
823 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
824 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200825 }
826
Ville Syrjälädf79cf42018-09-11 18:01:39 +0300827 I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200828 I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
Ville Syrjäläca6ad022014-01-17 20:09:03 +0200829
Damien Lespiau5a35e992012-10-26 18:20:12 +0100830 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
831 * register */
Tvrtko Ursulin86527442016-10-13 11:03:00 +0100832 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200833 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
Ville Syrjäläbae781b2016-11-16 13:33:16 +0200834 else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200835 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
Damien Lespiau5a35e992012-10-26 18:20:12 +0100836 else
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200837 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
Damien Lespiauc54173a2012-10-26 18:20:11 +0100838
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200839 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
Ville Syrjäläfd6e3c62018-09-07 18:24:08 +0300840 if (IS_IVYBRIDGE(dev_priv))
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200841 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
842 I915_WRITE_FW(SPRCTL(pipe), sprctl);
843 I915_WRITE_FW(SPRSURF(pipe),
844 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
845 POSTING_READ_FW(SPRSURF(pipe));
846
847 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800848}
849
850static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300851ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800852{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300853 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
854 enum pipe pipe = plane->pipe;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200855 unsigned long irqflags;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800856
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200857 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
858
859 I915_WRITE_FW(SPRCTL(pipe), 0);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800860 /* Can't leave the scaler enabled... */
Ville Syrjäläfd6e3c62018-09-07 18:24:08 +0300861 if (IS_IVYBRIDGE(dev_priv))
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200862 I915_WRITE_FW(SPRSCALE(pipe), 0);
Ville Syrjälä5b633d62014-04-29 13:35:47 +0300863
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200864 I915_WRITE_FW(SPRSURF(pipe), 0);
865 POSTING_READ_FW(SPRSURF(pipe));
866
867 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800868}
869
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200870static bool
Ville Syrjäläeade6c82018-01-30 22:38:03 +0200871ivb_plane_get_hw_state(struct intel_plane *plane,
872 enum pipe *pipe)
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200873{
874 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
875 enum intel_display_power_domain power_domain;
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200876 bool ret;
877
Ville Syrjäläeade6c82018-01-30 22:38:03 +0200878 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200879 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
880 return false;
881
Ville Syrjäläeade6c82018-01-30 22:38:03 +0200882 ret = I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE;
883
884 *pipe = plane->pipe;
Ville Syrjälä51f5a0962017-11-17 21:19:08 +0200885
886 intel_display_power_put(dev_priv, power_domain);
887
888 return ret;
889}
890
Ville Syrjäläddd57132018-09-07 18:24:02 +0300891static unsigned int
892g4x_sprite_max_stride(struct intel_plane *plane,
893 u32 pixel_format, u64 modifier,
894 unsigned int rotation)
895{
896 return 16384;
897}
898
Ville Syrjäläab330812017-04-21 21:14:32 +0300899static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
Ville Syrjälä0a375142017-03-17 23:18:00 +0200900 const struct intel_plane_state *plane_state)
901{
902 struct drm_i915_private *dev_priv =
903 to_i915(plane_state->base.plane->dev);
904 const struct drm_framebuffer *fb = plane_state->base.fb;
905 unsigned int rotation = plane_state->base.rotation;
906 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
907 u32 dvscntr;
908
909 dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
910
911 if (IS_GEN6(dev_priv))
912 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
913
914 switch (fb->format->format) {
915 case DRM_FORMAT_XBGR8888:
916 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
917 break;
918 case DRM_FORMAT_XRGB8888:
919 dvscntr |= DVS_FORMAT_RGBX888;
920 break;
921 case DRM_FORMAT_YUYV:
922 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
923 break;
924 case DRM_FORMAT_YVYU:
925 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
926 break;
927 case DRM_FORMAT_UYVY:
928 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
929 break;
930 case DRM_FORMAT_VYUY:
931 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
932 break;
933 default:
934 MISSING_CASE(fb->format->format);
935 return 0;
936 }
937
Ville Syrjäläb0f5c0b2018-02-14 21:23:25 +0200938 if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
939 dvscntr |= DVS_YUV_FORMAT_BT709;
940
Ville Syrjäläc8624ed2018-02-14 21:23:27 +0200941 if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
942 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
943
Ville Syrjälä0a375142017-03-17 23:18:00 +0200944 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
945 dvscntr |= DVS_TILED;
946
Robert Fossc2c446a2017-05-19 16:50:17 -0400947 if (rotation & DRM_MODE_ROTATE_180)
Ville Syrjälä0a375142017-03-17 23:18:00 +0200948 dvscntr |= DVS_ROTATE_180;
949
950 if (key->flags & I915_SET_COLORKEY_DESTINATION)
951 dvscntr |= DVS_DEST_KEY;
952 else if (key->flags & I915_SET_COLORKEY_SOURCE)
953 dvscntr |= DVS_SOURCE_KEY;
954
955 return dvscntr;
956}
957
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800958static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300959g4x_update_plane(struct intel_plane *plane,
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100960 const struct intel_crtc_state *crtc_state,
961 const struct intel_plane_state *plane_state)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800962{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300963 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
964 const struct drm_framebuffer *fb = plane_state->base.fb;
965 enum pipe pipe = plane->pipe;
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200966 u32 dvscntr = plane_state->ctl, dvsscale = 0;
Ville Syrjäläc11ada02018-09-07 18:24:04 +0300967 u32 dvssurf_offset = plane_state->color_plane[0].offset;
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200968 u32 linear_offset;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100969 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300970 int crtc_x = plane_state->base.dst.x1;
971 int crtc_y = plane_state->base.dst.y1;
972 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
973 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
Ville Syrjäläc11ada02018-09-07 18:24:04 +0300974 uint32_t x = plane_state->color_plane[0].x;
975 uint32_t y = plane_state->color_plane[0].y;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300976 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
977 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200978 unsigned long irqflags;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800979
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800980 /* Sizes are 0 based */
981 src_w--;
982 src_h--;
983 crtc_w--;
984 crtc_h--;
985
Ville Syrjälä8368f012013-12-05 15:51:31 +0200986 if (crtc_w != src_w || crtc_h != src_h)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800987 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
988
Ville Syrjälä29490562016-01-20 18:02:50 +0200989 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
Ville Syrjälä6687c902015-09-15 13:16:41 +0300990
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200991 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
992
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200993 if (key->flags) {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200994 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
995 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
996 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200997 }
998
Ville Syrjälädf79cf42018-09-11 18:01:39 +0300999 I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
Ville Syrjälädd584fc2017-03-09 17:44:33 +02001000 I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
Ville Syrjäläca6ad022014-01-17 20:09:03 +02001001
Ville Syrjäläbae781b2016-11-16 13:33:16 +02001002 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
Ville Syrjälädd584fc2017-03-09 17:44:33 +02001003 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
Damien Lespiau5a35e992012-10-26 18:20:12 +01001004 else
Ville Syrjälädd584fc2017-03-09 17:44:33 +02001005 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
Damien Lespiau5a35e992012-10-26 18:20:12 +01001006
Ville Syrjälädd584fc2017-03-09 17:44:33 +02001007 I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
1008 I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
1009 I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
1010 I915_WRITE_FW(DVSSURF(pipe),
1011 intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
1012 POSTING_READ_FW(DVSSURF(pipe));
1013
1014 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001015}
1016
1017static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +03001018g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001019{
Ville Syrjälä282dbf92017-03-27 21:55:33 +03001020 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1021 enum pipe pipe = plane->pipe;
Ville Syrjälädd584fc2017-03-09 17:44:33 +02001022 unsigned long irqflags;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001023
Ville Syrjälädd584fc2017-03-09 17:44:33 +02001024 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1025
1026 I915_WRITE_FW(DVSCNTR(pipe), 0);
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001027 /* Disable the scaler */
Ville Syrjälädd584fc2017-03-09 17:44:33 +02001028 I915_WRITE_FW(DVSSCALE(pipe), 0);
Ville Syrjälä48fe4692015-03-19 17:57:13 +02001029
Ville Syrjälädd584fc2017-03-09 17:44:33 +02001030 I915_WRITE_FW(DVSSURF(pipe), 0);
1031 POSTING_READ_FW(DVSSURF(pipe));
1032
1033 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001034}
1035
Ville Syrjälä51f5a0962017-11-17 21:19:08 +02001036static bool
Ville Syrjäläeade6c82018-01-30 22:38:03 +02001037g4x_plane_get_hw_state(struct intel_plane *plane,
1038 enum pipe *pipe)
Ville Syrjälä51f5a0962017-11-17 21:19:08 +02001039{
1040 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1041 enum intel_display_power_domain power_domain;
Ville Syrjälä51f5a0962017-11-17 21:19:08 +02001042 bool ret;
1043
Ville Syrjäläeade6c82018-01-30 22:38:03 +02001044 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
Ville Syrjälä51f5a0962017-11-17 21:19:08 +02001045 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
1046 return false;
1047
Ville Syrjäläeade6c82018-01-30 22:38:03 +02001048 ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE;
1049
1050 *pipe = plane->pipe;
Ville Syrjälä51f5a0962017-11-17 21:19:08 +02001051
1052 intel_display_power_put(dev_priv, power_domain);
1053
1054 return ret;
1055}
1056
Jesse Barnes8ea30862012-01-03 08:05:39 -08001057static int
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001058g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
1059 struct intel_plane_state *plane_state)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001060{
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001061 const struct drm_framebuffer *fb = plane_state->base.fb;
1062 const struct drm_rect *src = &plane_state->base.src;
1063 const struct drm_rect *dst = &plane_state->base.dst;
1064 int src_x, src_y, src_w, src_h, crtc_w, crtc_h;
1065 const struct drm_display_mode *adjusted_mode =
1066 &crtc_state->base.adjusted_mode;
1067 unsigned int cpp = fb->format->cpp[0];
1068 unsigned int width_bytes;
1069 int min_width, min_height;
1070
1071 crtc_w = drm_rect_width(dst);
1072 crtc_h = drm_rect_height(dst);
1073
1074 src_x = src->x1 >> 16;
1075 src_y = src->y1 >> 16;
1076 src_w = drm_rect_width(src) >> 16;
1077 src_h = drm_rect_height(src) >> 16;
1078
1079 if (src_w == crtc_w && src_h == crtc_h)
1080 return 0;
1081
1082 min_width = 3;
1083
1084 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1085 if (src_h & 1) {
1086 DRM_DEBUG_KMS("Source height must be even with interlaced modes\n");
1087 return -EINVAL;
1088 }
1089 min_height = 6;
1090 } else {
1091 min_height = 3;
1092 }
1093
1094 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1095
1096 if (src_w < min_width || src_h < min_height ||
1097 src_w > 2048 || src_h > 2048) {
1098 DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
1099 src_w, src_h, min_width, min_height, 2048, 2048);
1100 return -EINVAL;
1101 }
1102
1103 if (width_bytes > 4096) {
1104 DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n",
1105 width_bytes, 4096);
1106 return -EINVAL;
1107 }
1108
1109 if (width_bytes > 4096 || fb->pitches[0] > 4096) {
1110 DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n",
1111 fb->pitches[0], 4096);
1112 return -EINVAL;
1113 }
1114
1115 return 0;
1116}
1117
1118static int
1119g4x_sprite_check(struct intel_crtc_state *crtc_state,
1120 struct intel_plane_state *plane_state)
1121{
1122 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
Ville Syrjälä282dbf92017-03-27 21:55:33 +03001123 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
Ville Syrjälä17316932013-04-24 18:52:38 +03001124 int max_scale, min_scale;
Ville Syrjäläb63a16f2016-01-28 16:53:54 +02001125 int ret;
Matt Ropercf4c7c12014-12-04 10:27:42 -08001126
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001127 if (INTEL_GEN(dev_priv) < 7) {
1128 min_scale = 1;
1129 max_scale = 16 << 16;
1130 } else if (IS_IVYBRIDGE(dev_priv)) {
1131 min_scale = 1;
1132 max_scale = 2 << 16;
Chandra Konduru225c2282015-05-18 16:18:44 -07001133 } else {
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001134 min_scale = DRM_PLANE_HELPER_NO_SCALING;
1135 max_scale = DRM_PLANE_HELPER_NO_SCALING;
Chandra Konduru225c2282015-05-18 16:18:44 -07001136 }
1137
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001138 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
Maarten Lankhorst9c1659e2018-05-03 13:22:15 +02001139 &crtc_state->base,
1140 min_scale, max_scale,
1141 true, true);
1142 if (ret)
1143 return ret;
Damien Lespiau2d354c32012-10-22 18:19:27 +01001144
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001145 if (!plane_state->base.visible)
1146 return 0;
Ville Syrjälä17316932013-04-24 18:52:38 +03001147
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001148 ret = intel_plane_check_src_coordinates(plane_state);
1149 if (ret)
1150 return ret;
Ville Syrjälä17316932013-04-24 18:52:38 +03001151
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001152 ret = g4x_sprite_check_scaling(crtc_state, plane_state);
1153 if (ret)
1154 return ret;
Gustavo Padovan96d61a72014-09-05 17:04:47 -03001155
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001156 ret = i9xx_check_plane_surface(plane_state);
1157 if (ret)
1158 return ret;
Maarten Lankhorst9c1659e2018-05-03 13:22:15 +02001159
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001160 if (INTEL_GEN(dev_priv) >= 7)
1161 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
1162 else
1163 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
Maarten Lankhorst9c1659e2018-05-03 13:22:15 +02001164
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001165 return 0;
1166}
Maarten Lankhorst9c1659e2018-05-03 13:22:15 +02001167
Ville Syrjälä25721f82018-09-07 18:24:12 +03001168int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
1169{
1170 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1171 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1172 unsigned int rotation = plane_state->base.rotation;
1173
1174 /* CHV ignores the mirror bit when the rotate bit is set :( */
1175 if (IS_CHERRYVIEW(dev_priv) &&
1176 rotation & DRM_MODE_ROTATE_180 &&
1177 rotation & DRM_MODE_REFLECT_X) {
1178 DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n");
1179 return -EINVAL;
1180 }
1181
1182 return 0;
1183}
1184
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001185static int
1186vlv_sprite_check(struct intel_crtc_state *crtc_state,
1187 struct intel_plane_state *plane_state)
1188{
1189 int ret;
Gustavo Padovan96d61a72014-09-05 17:04:47 -03001190
Ville Syrjälä25721f82018-09-07 18:24:12 +03001191 ret = chv_plane_check_rotation(plane_state);
1192 if (ret)
1193 return ret;
1194
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001195 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1196 &crtc_state->base,
1197 DRM_PLANE_HELPER_NO_SCALING,
1198 DRM_PLANE_HELPER_NO_SCALING,
1199 true, true);
1200 if (ret)
1201 return ret;
Ville Syrjäläa0864d52017-03-23 21:27:09 +02001202
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001203 if (!plane_state->base.visible)
1204 return 0;
Ville Syrjäläf9407ae2017-03-23 21:27:12 +02001205
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001206 ret = intel_plane_check_src_coordinates(plane_state);
1207 if (ret)
1208 return ret;
Ville Syrjäläf9407ae2017-03-23 21:27:12 +02001209
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001210 ret = i9xx_check_plane_surface(plane_state);
1211 if (ret)
1212 return ret;
1213
1214 plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
1215
1216 return 0;
1217}
1218
Ville Syrjäläe21c2d32018-09-07 18:24:10 +03001219static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
1220 const struct intel_plane_state *plane_state)
1221{
1222 const struct drm_framebuffer *fb = plane_state->base.fb;
1223 unsigned int rotation = plane_state->base.rotation;
1224 struct drm_format_name_buf format_name;
1225
1226 if (!fb)
1227 return 0;
1228
1229 if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
Ville Syrjälä1ee516f2018-09-18 16:10:59 +03001230 is_ccs_modifier(fb->modifier)) {
Ville Syrjäläe21c2d32018-09-07 18:24:10 +03001231 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation (%x)\n",
1232 rotation);
1233 return -EINVAL;
1234 }
1235
1236 if (rotation & DRM_MODE_REFLECT_X &&
1237 fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1238 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
1239 return -EINVAL;
1240 }
1241
1242 if (drm_rotation_90_or_270(rotation)) {
1243 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
1244 fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
1245 DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
1246 return -EINVAL;
1247 }
1248
1249 /*
1250 * 90/270 is not allowed with RGB64 16:16:16:16,
1251 * RGB 16-bit 5:6:5, and Indexed 8-bit.
1252 * TBD: Add RGB64 case once its added in supported format list.
1253 */
1254 switch (fb->format->format) {
1255 case DRM_FORMAT_C8:
1256 case DRM_FORMAT_RGB565:
1257 DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
1258 drm_get_format_name(fb->format->format,
1259 &format_name));
1260 return -EINVAL;
1261 default:
1262 break;
1263 }
1264 }
1265
1266 /* Y-tiling is not supported in IF-ID Interlace mode */
1267 if (crtc_state->base.enable &&
1268 crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
1269 (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
1270 fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
1271 fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
1272 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
1273 DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
1274 return -EINVAL;
1275 }
1276
1277 return 0;
1278}
1279
Ville Syrjälä73266592018-09-07 18:24:11 +03001280static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
1281 const struct intel_plane_state *plane_state)
1282{
1283 struct drm_i915_private *dev_priv =
1284 to_i915(plane_state->base.plane->dev);
1285 int crtc_x = plane_state->base.dst.x1;
1286 int crtc_w = drm_rect_width(&plane_state->base.dst);
1287 int pipe_src_w = crtc_state->pipe_src_w;
1288
1289 /*
1290 * Display WA #1175: cnl,glk
1291 * Planes other than the cursor may cause FIFO underflow and display
1292 * corruption if starting less than 4 pixels from the right edge of
1293 * the screen.
1294 * Besides the above WA fix the similar problem, where planes other
1295 * than the cursor ending less than 4 pixels from the left edge of the
1296 * screen may cause FIFO underflow and display corruption.
1297 */
1298 if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
1299 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
1300 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
1301 crtc_x + crtc_w < 4 ? "end" : "start",
1302 crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
1303 4, pipe_src_w - 4);
1304 return -ERANGE;
1305 }
1306
1307 return 0;
1308}
1309
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001310int skl_plane_check(struct intel_crtc_state *crtc_state,
1311 struct intel_plane_state *plane_state)
1312{
1313 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1314 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1315 int max_scale, min_scale;
1316 int ret;
1317
Ville Syrjäläe21c2d32018-09-07 18:24:10 +03001318 ret = skl_plane_check_fb(crtc_state, plane_state);
1319 if (ret)
1320 return ret;
1321
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001322 /* use scaler when colorkey is not required */
1323 if (!plane_state->ckey.flags) {
1324 const struct drm_framebuffer *fb = plane_state->base.fb;
1325
1326 min_scale = 1;
1327 max_scale = skl_max_scale(crtc_state,
1328 fb ? fb->format->format : 0);
Ville Syrjäläa0864d52017-03-23 21:27:09 +02001329 } else {
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001330 min_scale = DRM_PLANE_HELPER_NO_SCALING;
1331 max_scale = DRM_PLANE_HELPER_NO_SCALING;
Ville Syrjäläb63a16f2016-01-28 16:53:54 +02001332 }
1333
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001334 ret = drm_atomic_helper_check_plane_state(&plane_state->base,
1335 &crtc_state->base,
1336 min_scale, max_scale,
1337 true, true);
1338 if (ret)
1339 return ret;
1340
1341 if (!plane_state->base.visible)
1342 return 0;
1343
Ville Syrjälä73266592018-09-07 18:24:11 +03001344 ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
1345 if (ret)
1346 return ret;
1347
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001348 ret = intel_plane_check_src_coordinates(plane_state);
1349 if (ret)
1350 return ret;
1351
Ville Syrjälä73266592018-09-07 18:24:11 +03001352 ret = skl_check_plane_surface(plane_state);
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001353 if (ret)
1354 return ret;
1355
1356 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
1357
James Ausmus4036c782017-11-13 10:11:28 -08001358 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001359 plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
1360 plane_state);
James Ausmus4036c782017-11-13 10:11:28 -08001361
Gustavo Padovan96d61a72014-09-05 17:04:47 -03001362 return 0;
1363}
1364
Ville Syrjälä672b3c42018-05-29 21:28:00 +03001365static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv)
1366{
1367 return INTEL_GEN(dev_priv) >= 9;
1368}
1369
1370static void intel_plane_set_ckey(struct intel_plane_state *plane_state,
1371 const struct drm_intel_sprite_colorkey *set)
1372{
1373 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
1374 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1375 struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1376
1377 *key = *set;
1378
1379 /*
1380 * We want src key enabled on the
1381 * sprite and not on the primary.
1382 */
1383 if (plane->id == PLANE_PRIMARY &&
1384 set->flags & I915_SET_COLORKEY_SOURCE)
1385 key->flags = 0;
1386
1387 /*
1388 * On SKL+ we want dst key enabled on
1389 * the primary and not on the sprite.
1390 */
1391 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY &&
1392 set->flags & I915_SET_COLORKEY_DESTINATION)
1393 key->flags = 0;
1394}
1395
Ville Syrjälä6a20fe72018-02-07 18:48:41 +02001396int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
1397 struct drm_file *file_priv)
Jesse Barnes8ea30862012-01-03 08:05:39 -08001398{
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +01001399 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes8ea30862012-01-03 08:05:39 -08001400 struct drm_intel_sprite_colorkey *set = data;
Jesse Barnes8ea30862012-01-03 08:05:39 -08001401 struct drm_plane *plane;
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001402 struct drm_plane_state *plane_state;
1403 struct drm_atomic_state *state;
1404 struct drm_modeset_acquire_ctx ctx;
Jesse Barnes8ea30862012-01-03 08:05:39 -08001405 int ret = 0;
1406
Ville Syrjälä6ec5bd32018-02-02 22:42:31 +02001407 /* ignore the pointless "none" flag */
1408 set->flags &= ~I915_SET_COLORKEY_NONE;
1409
Ville Syrjälä89746e72018-02-06 22:43:33 +02001410 if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1411 return -EINVAL;
1412
Jesse Barnes8ea30862012-01-03 08:05:39 -08001413 /* Make sure we don't try to enable both src & dest simultaneously */
1414 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1415 return -EINVAL;
1416
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +01001417 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
Ville Syrjälä47ecbb22015-03-19 21:18:57 +02001418 set->flags & I915_SET_COLORKEY_DESTINATION)
1419 return -EINVAL;
1420
Keith Packard418da172017-03-14 23:25:07 -07001421 plane = drm_plane_find(dev, file_priv, set->plane_id);
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001422 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1423 return -ENOENT;
1424
Ville Syrjälä672b3c42018-05-29 21:28:00 +03001425 /*
1426 * SKL+ only plane 2 can do destination keying against plane 1.
1427 * Also multiple planes can't do destination keying on the same
1428 * pipe simultaneously.
1429 */
1430 if (INTEL_GEN(dev_priv) >= 9 &&
1431 to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
1432 set->flags & I915_SET_COLORKEY_DESTINATION)
1433 return -EINVAL;
1434
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001435 drm_modeset_acquire_init(&ctx, 0);
1436
1437 state = drm_atomic_state_alloc(plane->dev);
1438 if (!state) {
1439 ret = -ENOMEM;
1440 goto out;
Jesse Barnes8ea30862012-01-03 08:05:39 -08001441 }
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001442 state->acquire_ctx = &ctx;
Jesse Barnes8ea30862012-01-03 08:05:39 -08001443
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001444 while (1) {
1445 plane_state = drm_atomic_get_plane_state(state, plane);
1446 ret = PTR_ERR_OR_ZERO(plane_state);
Ville Syrjälä672b3c42018-05-29 21:28:00 +03001447 if (!ret)
1448 intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
1449
1450 /*
1451 * On some platforms we have to configure
1452 * the dst colorkey on the primary plane.
1453 */
1454 if (!ret && has_dst_key_in_primary_plane(dev_priv)) {
1455 struct intel_crtc *crtc =
1456 intel_get_crtc_for_pipe(dev_priv,
1457 to_intel_plane(plane)->pipe);
1458
1459 plane_state = drm_atomic_get_plane_state(state,
1460 crtc->base.primary);
1461 ret = PTR_ERR_OR_ZERO(plane_state);
1462 if (!ret)
1463 intel_plane_set_ckey(to_intel_plane_state(plane_state), set);
Chandra Konduru6156a452015-04-27 13:48:39 -07001464 }
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001465
Ville Syrjälä672b3c42018-05-29 21:28:00 +03001466 if (!ret)
1467 ret = drm_atomic_commit(state);
1468
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001469 if (ret != -EDEADLK)
1470 break;
1471
1472 drm_atomic_state_clear(state);
1473 drm_modeset_backoff(&ctx);
Chandra Konduru6156a452015-04-27 13:48:39 -07001474 }
1475
Chris Wilson08536952016-10-14 13:18:18 +01001476 drm_atomic_state_put(state);
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001477out:
1478 drm_modeset_drop_locks(&ctx);
1479 drm_modeset_acquire_fini(&ctx);
Jesse Barnes8ea30862012-01-03 08:05:39 -08001480 return ret;
1481}
1482
Ville Syrjäläab330812017-04-21 21:14:32 +03001483static const uint32_t g4x_plane_formats[] = {
Chris Wilsond1686ae2012-04-10 11:41:49 +01001484 DRM_FORMAT_XRGB8888,
1485 DRM_FORMAT_YUYV,
1486 DRM_FORMAT_YVYU,
1487 DRM_FORMAT_UYVY,
1488 DRM_FORMAT_VYUY,
1489};
1490
Ben Widawsky714244e2017-08-01 09:58:16 -07001491static const uint64_t i9xx_plane_format_modifiers[] = {
1492 I915_FORMAT_MOD_X_TILED,
1493 DRM_FORMAT_MOD_LINEAR,
1494 DRM_FORMAT_MOD_INVALID
1495};
1496
Damien Lespiaudada2d52015-05-12 16:13:22 +01001497static const uint32_t snb_plane_formats[] = {
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001498 DRM_FORMAT_XBGR8888,
1499 DRM_FORMAT_XRGB8888,
1500 DRM_FORMAT_YUYV,
1501 DRM_FORMAT_YVYU,
1502 DRM_FORMAT_UYVY,
1503 DRM_FORMAT_VYUY,
1504};
1505
Damien Lespiaudada2d52015-05-12 16:13:22 +01001506static const uint32_t vlv_plane_formats[] = {
Jesse Barnes7f1f38512013-04-02 11:22:20 -07001507 DRM_FORMAT_RGB565,
1508 DRM_FORMAT_ABGR8888,
1509 DRM_FORMAT_ARGB8888,
1510 DRM_FORMAT_XBGR8888,
1511 DRM_FORMAT_XRGB8888,
1512 DRM_FORMAT_XBGR2101010,
1513 DRM_FORMAT_ABGR2101010,
1514 DRM_FORMAT_YUYV,
1515 DRM_FORMAT_YVYU,
1516 DRM_FORMAT_UYVY,
1517 DRM_FORMAT_VYUY,
1518};
1519
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00001520static uint32_t skl_plane_formats[] = {
1521 DRM_FORMAT_RGB565,
1522 DRM_FORMAT_ABGR8888,
1523 DRM_FORMAT_ARGB8888,
1524 DRM_FORMAT_XBGR8888,
1525 DRM_FORMAT_XRGB8888,
1526 DRM_FORMAT_YUYV,
1527 DRM_FORMAT_YVYU,
1528 DRM_FORMAT_UYVY,
1529 DRM_FORMAT_VYUY,
1530};
1531
Chandra Konduru429204f2018-05-12 03:03:17 +05301532static uint32_t skl_planar_formats[] = {
1533 DRM_FORMAT_RGB565,
1534 DRM_FORMAT_ABGR8888,
1535 DRM_FORMAT_ARGB8888,
1536 DRM_FORMAT_XBGR8888,
1537 DRM_FORMAT_XRGB8888,
1538 DRM_FORMAT_YUYV,
1539 DRM_FORMAT_YVYU,
1540 DRM_FORMAT_UYVY,
1541 DRM_FORMAT_VYUY,
1542 DRM_FORMAT_NV12,
1543};
1544
Ville Syrjälä77064e22017-12-22 21:22:28 +02001545static const uint64_t skl_plane_format_modifiers_noccs[] = {
1546 I915_FORMAT_MOD_Yf_TILED,
1547 I915_FORMAT_MOD_Y_TILED,
1548 I915_FORMAT_MOD_X_TILED,
1549 DRM_FORMAT_MOD_LINEAR,
1550 DRM_FORMAT_MOD_INVALID
1551};
1552
1553static const uint64_t skl_plane_format_modifiers_ccs[] = {
1554 I915_FORMAT_MOD_Yf_TILED_CCS,
1555 I915_FORMAT_MOD_Y_TILED_CCS,
Ville Syrjälä74ac1602017-12-22 21:22:26 +02001556 I915_FORMAT_MOD_Yf_TILED,
1557 I915_FORMAT_MOD_Y_TILED,
Ben Widawsky714244e2017-08-01 09:58:16 -07001558 I915_FORMAT_MOD_X_TILED,
1559 DRM_FORMAT_MOD_LINEAR,
1560 DRM_FORMAT_MOD_INVALID
1561};
1562
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001563static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
1564 u32 format, u64 modifier)
Ben Widawsky714244e2017-08-01 09:58:16 -07001565{
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001566 switch (modifier) {
1567 case DRM_FORMAT_MOD_LINEAR:
1568 case I915_FORMAT_MOD_X_TILED:
1569 break;
1570 default:
1571 return false;
1572 }
1573
Ben Widawsky714244e2017-08-01 09:58:16 -07001574 switch (format) {
Ben Widawsky714244e2017-08-01 09:58:16 -07001575 case DRM_FORMAT_XRGB8888:
1576 case DRM_FORMAT_YUYV:
1577 case DRM_FORMAT_YVYU:
1578 case DRM_FORMAT_UYVY:
1579 case DRM_FORMAT_VYUY:
1580 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1581 modifier == I915_FORMAT_MOD_X_TILED)
1582 return true;
1583 /* fall through */
1584 default:
1585 return false;
1586 }
1587}
1588
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001589static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
1590 u32 format, u64 modifier)
Ben Widawsky714244e2017-08-01 09:58:16 -07001591{
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001592 switch (modifier) {
1593 case DRM_FORMAT_MOD_LINEAR:
1594 case I915_FORMAT_MOD_X_TILED:
1595 break;
1596 default:
1597 return false;
1598 }
1599
Ben Widawsky714244e2017-08-01 09:58:16 -07001600 switch (format) {
Ville Syrjäläc21f7902017-12-22 21:22:27 +02001601 case DRM_FORMAT_XRGB8888:
1602 case DRM_FORMAT_XBGR8888:
Ben Widawsky714244e2017-08-01 09:58:16 -07001603 case DRM_FORMAT_YUYV:
1604 case DRM_FORMAT_YVYU:
1605 case DRM_FORMAT_UYVY:
1606 case DRM_FORMAT_VYUY:
Ville Syrjäläc21f7902017-12-22 21:22:27 +02001607 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1608 modifier == I915_FORMAT_MOD_X_TILED)
1609 return true;
1610 /* fall through */
1611 default:
1612 return false;
1613 }
1614}
1615
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001616static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
1617 u32 format, u64 modifier)
Ville Syrjäläc21f7902017-12-22 21:22:27 +02001618{
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001619 switch (modifier) {
1620 case DRM_FORMAT_MOD_LINEAR:
1621 case I915_FORMAT_MOD_X_TILED:
1622 break;
1623 default:
1624 return false;
1625 }
1626
Ville Syrjäläc21f7902017-12-22 21:22:27 +02001627 switch (format) {
Ben Widawsky714244e2017-08-01 09:58:16 -07001628 case DRM_FORMAT_RGB565:
Ville Syrjäläc21f7902017-12-22 21:22:27 +02001629 case DRM_FORMAT_ABGR8888:
Ben Widawsky714244e2017-08-01 09:58:16 -07001630 case DRM_FORMAT_ARGB8888:
Ville Syrjäläc21f7902017-12-22 21:22:27 +02001631 case DRM_FORMAT_XBGR8888:
1632 case DRM_FORMAT_XRGB8888:
Ben Widawsky714244e2017-08-01 09:58:16 -07001633 case DRM_FORMAT_XBGR2101010:
1634 case DRM_FORMAT_ABGR2101010:
Ville Syrjäläc21f7902017-12-22 21:22:27 +02001635 case DRM_FORMAT_YUYV:
1636 case DRM_FORMAT_YVYU:
1637 case DRM_FORMAT_UYVY:
1638 case DRM_FORMAT_VYUY:
Ben Widawsky714244e2017-08-01 09:58:16 -07001639 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1640 modifier == I915_FORMAT_MOD_X_TILED)
1641 return true;
1642 /* fall through */
1643 default:
1644 return false;
1645 }
1646}
1647
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001648static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
1649 u32 format, u64 modifier)
Ben Widawsky714244e2017-08-01 09:58:16 -07001650{
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001651 struct intel_plane *plane = to_intel_plane(_plane);
1652
1653 switch (modifier) {
1654 case DRM_FORMAT_MOD_LINEAR:
1655 case I915_FORMAT_MOD_X_TILED:
1656 case I915_FORMAT_MOD_Y_TILED:
1657 case I915_FORMAT_MOD_Yf_TILED:
1658 break;
1659 case I915_FORMAT_MOD_Y_TILED_CCS:
1660 case I915_FORMAT_MOD_Yf_TILED_CCS:
1661 if (!plane->has_ccs)
1662 return false;
1663 break;
1664 default:
1665 return false;
1666 }
1667
Ben Widawsky714244e2017-08-01 09:58:16 -07001668 switch (format) {
1669 case DRM_FORMAT_XRGB8888:
1670 case DRM_FORMAT_XBGR8888:
1671 case DRM_FORMAT_ARGB8888:
1672 case DRM_FORMAT_ABGR8888:
Dhinakaran Pandiyan63eaf9a2018-08-22 12:38:27 -07001673 if (is_ccs_modifier(modifier))
Ville Syrjälä77064e22017-12-22 21:22:28 +02001674 return true;
1675 /* fall through */
Ben Widawsky714244e2017-08-01 09:58:16 -07001676 case DRM_FORMAT_RGB565:
1677 case DRM_FORMAT_XRGB2101010:
1678 case DRM_FORMAT_XBGR2101010:
1679 case DRM_FORMAT_YUYV:
1680 case DRM_FORMAT_YVYU:
1681 case DRM_FORMAT_UYVY:
1682 case DRM_FORMAT_VYUY:
Chandra Konduru429204f2018-05-12 03:03:17 +05301683 case DRM_FORMAT_NV12:
Ben Widawsky714244e2017-08-01 09:58:16 -07001684 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1685 return true;
1686 /* fall through */
1687 case DRM_FORMAT_C8:
1688 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1689 modifier == I915_FORMAT_MOD_X_TILED ||
1690 modifier == I915_FORMAT_MOD_Y_TILED)
1691 return true;
1692 /* fall through */
1693 default:
1694 return false;
1695 }
1696}
1697
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001698static const struct drm_plane_funcs g4x_sprite_funcs = {
Ville Syrjäläb4686c42018-05-30 19:59:22 +03001699 .update_plane = drm_atomic_helper_update_plane,
1700 .disable_plane = drm_atomic_helper_disable_plane,
1701 .destroy = intel_plane_destroy,
1702 .atomic_get_property = intel_plane_atomic_get_property,
1703 .atomic_set_property = intel_plane_atomic_set_property,
1704 .atomic_duplicate_state = intel_plane_duplicate_state,
1705 .atomic_destroy_state = intel_plane_destroy_state,
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001706 .format_mod_supported = g4x_sprite_format_mod_supported,
1707};
Ben Widawsky714244e2017-08-01 09:58:16 -07001708
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001709static const struct drm_plane_funcs snb_sprite_funcs = {
1710 .update_plane = drm_atomic_helper_update_plane,
1711 .disable_plane = drm_atomic_helper_disable_plane,
1712 .destroy = intel_plane_destroy,
1713 .atomic_get_property = intel_plane_atomic_get_property,
1714 .atomic_set_property = intel_plane_atomic_set_property,
1715 .atomic_duplicate_state = intel_plane_duplicate_state,
1716 .atomic_destroy_state = intel_plane_destroy_state,
1717 .format_mod_supported = snb_sprite_format_mod_supported,
1718};
Ben Widawsky714244e2017-08-01 09:58:16 -07001719
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001720static const struct drm_plane_funcs vlv_sprite_funcs = {
1721 .update_plane = drm_atomic_helper_update_plane,
1722 .disable_plane = drm_atomic_helper_disable_plane,
1723 .destroy = intel_plane_destroy,
1724 .atomic_get_property = intel_plane_atomic_get_property,
1725 .atomic_set_property = intel_plane_atomic_set_property,
1726 .atomic_duplicate_state = intel_plane_duplicate_state,
1727 .atomic_destroy_state = intel_plane_destroy_state,
1728 .format_mod_supported = vlv_sprite_format_mod_supported,
1729};
Ben Widawsky714244e2017-08-01 09:58:16 -07001730
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001731static const struct drm_plane_funcs skl_plane_funcs = {
1732 .update_plane = drm_atomic_helper_update_plane,
1733 .disable_plane = drm_atomic_helper_disable_plane,
1734 .destroy = intel_plane_destroy,
1735 .atomic_get_property = intel_plane_atomic_get_property,
1736 .atomic_set_property = intel_plane_atomic_set_property,
1737 .atomic_duplicate_state = intel_plane_duplicate_state,
1738 .atomic_destroy_state = intel_plane_destroy_state,
1739 .format_mod_supported = skl_plane_format_mod_supported,
Ben Widawsky714244e2017-08-01 09:58:16 -07001740};
1741
Ville Syrjälä77064e22017-12-22 21:22:28 +02001742bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
1743 enum pipe pipe, enum plane_id plane_id)
1744{
1745 if (plane_id == PLANE_CURSOR)
1746 return false;
1747
1748 if (INTEL_GEN(dev_priv) >= 10)
1749 return true;
1750
1751 if (IS_GEMINILAKE(dev_priv))
1752 return pipe != PIPE_C;
1753
1754 return pipe != PIPE_C &&
1755 (plane_id == PLANE_PRIMARY ||
1756 plane_id == PLANE_SPRITE0);
1757}
1758
Ville Syrjäläb079bd172016-10-25 18:58:02 +03001759struct intel_plane *
Ville Syrjälä580503c2016-10-31 22:37:00 +02001760intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1761 enum pipe pipe, int plane)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001762{
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001763 struct intel_plane *intel_plane = NULL;
1764 struct intel_plane_state *state = NULL;
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001765 const struct drm_plane_funcs *plane_funcs;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001766 unsigned long possible_crtcs;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001767 const uint32_t *plane_formats;
Ben Widawsky714244e2017-08-01 09:58:16 -07001768 const uint64_t *modifiers;
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001769 unsigned int supported_rotations;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001770 int num_plane_formats;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001771 int ret;
1772
Daniel Vetterb14c5672013-09-19 12:18:32 +02001773 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001774 if (!intel_plane) {
1775 ret = -ENOMEM;
1776 goto fail;
1777 }
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001778
Matt Roper8e7d6882015-01-21 16:35:41 -08001779 state = intel_create_plane_state(&intel_plane->base);
1780 if (!state) {
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001781 ret = -ENOMEM;
1782 goto fail;
Matt Roperea2c67b2014-12-23 10:41:52 -08001783 }
Matt Roper8e7d6882015-01-21 16:35:41 -08001784 intel_plane->base.state = &state->base;
Matt Roperea2c67b2014-12-23 10:41:52 -08001785
Ville Syrjälä77064e22017-12-22 21:22:28 +02001786 if (INTEL_GEN(dev_priv) >= 9) {
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001787 state->scaler_id = -1;
1788
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001789 intel_plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
1790 PLANE_SPRITE0 + plane);
1791
Ville Syrjäläddd57132018-09-07 18:24:02 +03001792 intel_plane->max_stride = skl_plane_max_stride;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001793 intel_plane->update_plane = skl_update_plane;
1794 intel_plane->disable_plane = skl_disable_plane;
Ville Syrjälä51f5a0962017-11-17 21:19:08 +02001795 intel_plane->get_hw_state = skl_plane_get_hw_state;
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001796 intel_plane->check_plane = skl_plane_check;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001797
Chandra Konduru429204f2018-05-12 03:03:17 +05301798 if (skl_plane_has_planar(dev_priv, pipe,
1799 PLANE_SPRITE0 + plane)) {
1800 plane_formats = skl_planar_formats;
1801 num_plane_formats = ARRAY_SIZE(skl_planar_formats);
1802 } else {
1803 plane_formats = skl_plane_formats;
1804 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1805 }
Ben Widawsky714244e2017-08-01 09:58:16 -07001806
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001807 if (intel_plane->has_ccs)
Ville Syrjälä77064e22017-12-22 21:22:28 +02001808 modifiers = skl_plane_format_modifiers_ccs;
1809 else
1810 modifiers = skl_plane_format_modifiers_noccs;
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001811
1812 plane_funcs = &skl_plane_funcs;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001813 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Ville Syrjäläddd57132018-09-07 18:24:02 +03001814 intel_plane->max_stride = i9xx_plane_max_stride;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001815 intel_plane->update_plane = vlv_update_plane;
1816 intel_plane->disable_plane = vlv_disable_plane;
Ville Syrjälä51f5a0962017-11-17 21:19:08 +02001817 intel_plane->get_hw_state = vlv_plane_get_hw_state;
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001818 intel_plane->check_plane = vlv_sprite_check;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001819
1820 plane_formats = vlv_plane_formats;
1821 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
Ben Widawsky714244e2017-08-01 09:58:16 -07001822 modifiers = i9xx_plane_format_modifiers;
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001823
1824 plane_funcs = &vlv_sprite_funcs;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001825 } else if (INTEL_GEN(dev_priv) >= 7) {
Ville Syrjäläddd57132018-09-07 18:24:02 +03001826 intel_plane->max_stride = g4x_sprite_max_stride;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001827 intel_plane->update_plane = ivb_update_plane;
1828 intel_plane->disable_plane = ivb_disable_plane;
Ville Syrjälä51f5a0962017-11-17 21:19:08 +02001829 intel_plane->get_hw_state = ivb_plane_get_hw_state;
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001830 intel_plane->check_plane = g4x_sprite_check;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001831
1832 plane_formats = snb_plane_formats;
1833 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
Ben Widawsky714244e2017-08-01 09:58:16 -07001834 modifiers = i9xx_plane_format_modifiers;
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001835
1836 plane_funcs = &snb_sprite_funcs;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001837 } else {
Ville Syrjäläddd57132018-09-07 18:24:02 +03001838 intel_plane->max_stride = g4x_sprite_max_stride;
Ville Syrjäläab330812017-04-21 21:14:32 +03001839 intel_plane->update_plane = g4x_update_plane;
1840 intel_plane->disable_plane = g4x_disable_plane;
Ville Syrjälä51f5a0962017-11-17 21:19:08 +02001841 intel_plane->get_hw_state = g4x_plane_get_hw_state;
Ville Syrjälä4e0b83a2018-09-07 18:24:09 +03001842 intel_plane->check_plane = g4x_sprite_check;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001843
Ben Widawsky714244e2017-08-01 09:58:16 -07001844 modifiers = i9xx_plane_format_modifiers;
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01001845 if (IS_GEN6(dev_priv)) {
Chris Wilsond1686ae2012-04-10 11:41:49 +01001846 plane_formats = snb_plane_formats;
1847 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001848
1849 plane_funcs = &snb_sprite_funcs;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001850 } else {
Ville Syrjäläab330812017-04-21 21:14:32 +03001851 plane_formats = g4x_plane_formats;
1852 num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001853
1854 plane_funcs = &g4x_sprite_funcs;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001855 }
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001856 }
1857
Dave Airlie5481e272016-10-25 16:36:13 +10001858 if (INTEL_GEN(dev_priv) >= 9) {
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001859 supported_rotations =
Robert Fossc2c446a2017-05-19 16:50:17 -04001860 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1861 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
Ville Syrjälä4ea7be22016-11-14 18:54:00 +02001862 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1863 supported_rotations =
Robert Fossc2c446a2017-05-19 16:50:17 -04001864 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1865 DRM_MODE_REFLECT_X;
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001866 } else {
1867 supported_rotations =
Robert Fossc2c446a2017-05-19 16:50:17 -04001868 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001869 }
1870
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001871 intel_plane->pipe = pipe;
Ville Syrjäläed150302017-11-17 21:19:10 +02001872 intel_plane->i9xx_plane = plane;
Ville Syrjäläb14e5842016-11-22 18:01:56 +02001873 intel_plane->id = PLANE_SPRITE0 + plane;
Ville Syrjäläc19e1122018-01-23 20:33:43 +02001874 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, intel_plane->id);
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001875
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001876 possible_crtcs = (1 << pipe);
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001877
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001878 if (INTEL_GEN(dev_priv) >= 9)
Ville Syrjälä580503c2016-10-31 22:37:00 +02001879 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001880 possible_crtcs, plane_funcs,
Ville Syrjälä38573dc2016-05-27 20:59:23 +03001881 plane_formats, num_plane_formats,
Ben Widawsky714244e2017-08-01 09:58:16 -07001882 modifiers,
1883 DRM_PLANE_TYPE_OVERLAY,
Ville Syrjälä38573dc2016-05-27 20:59:23 +03001884 "plane %d%c", plane + 2, pipe_name(pipe));
1885 else
Ville Syrjälä580503c2016-10-31 22:37:00 +02001886 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
Ville Syrjäläa38189c2018-05-18 19:21:59 +03001887 possible_crtcs, plane_funcs,
Ville Syrjälä38573dc2016-05-27 20:59:23 +03001888 plane_formats, num_plane_formats,
Ben Widawsky714244e2017-08-01 09:58:16 -07001889 modifiers,
1890 DRM_PLANE_TYPE_OVERLAY,
Ville Syrjälä38573dc2016-05-27 20:59:23 +03001891 "sprite %c", sprite_name(pipe, plane));
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001892 if (ret)
1893 goto fail;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001894
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001895 drm_plane_create_rotation_property(&intel_plane->base,
Robert Fossc2c446a2017-05-19 16:50:17 -04001896 DRM_MODE_ROTATE_0,
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001897 supported_rotations);
Ville Syrjälä7ed6eee2014-08-05 11:26:55 +05301898
Ville Syrjäläb0f5c0b2018-02-14 21:23:25 +02001899 drm_plane_create_color_properties(&intel_plane->base,
1900 BIT(DRM_COLOR_YCBCR_BT601) |
1901 BIT(DRM_COLOR_YCBCR_BT709),
Ville Syrjäläc8624ed2018-02-14 21:23:27 +02001902 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1903 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
Ville Syrjälä23b28082018-02-14 21:23:26 +02001904 DRM_COLOR_YCBCR_BT709,
Ville Syrjäläb0f5c0b2018-02-14 21:23:25 +02001905 DRM_COLOR_YCBCR_LIMITED_RANGE);
1906
Matt Roperea2c67b2014-12-23 10:41:52 -08001907 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1908
Ville Syrjäläb079bd172016-10-25 18:58:02 +03001909 return intel_plane;
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001910
1911fail:
1912 kfree(state);
1913 kfree(intel_plane);
1914
Ville Syrjäläb079bd172016-10-25 18:58:02 +03001915 return ERR_PTR(ret);
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001916}