Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Driver for the Conexant CX25821 PCIe bridge |
| 3 | * |
| 4 | * Copyright (C) 2009 Conexant Systems Inc. |
| 5 | * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21 | */ |
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 22 | |
| 23 | #ifndef __CX25821_REGISTERS__ |
| 24 | #define __CX25821_REGISTERS__ |
| 25 | |
| 26 | /* Risc Instructions */ |
| 27 | #define RISC_CNT_INC 0x00010000 |
| 28 | #define RISC_CNT_RESET 0x00030000 |
| 29 | #define RISC_IRQ1 0x01000000 |
| 30 | #define RISC_IRQ2 0x02000000 |
| 31 | #define RISC_EOL 0x04000000 |
| 32 | #define RISC_SOL 0x08000000 |
| 33 | #define RISC_WRITE 0x10000000 |
| 34 | #define RISC_SKIP 0x20000000 |
| 35 | #define RISC_JUMP 0x70000000 |
| 36 | #define RISC_SYNC 0x80000000 |
| 37 | #define RISC_RESYNC 0x80008000 |
| 38 | #define RISC_READ 0x90000000 |
| 39 | #define RISC_WRITERM 0xB0000000 |
| 40 | #define RISC_WRITECM 0xC0000000 |
| 41 | #define RISC_WRITECR 0xD0000000 |
| 42 | #define RISC_WRITEC 0x50000000 |
| 43 | #define RISC_READC 0xA0000000 |
| 44 | |
| 45 | #define RISC_SYNC_ODD 0x00000000 |
| 46 | #define RISC_SYNC_EVEN 0x00000200 |
| 47 | #define RISC_SYNC_ODD_VBI 0x00000006 |
| 48 | #define RISC_SYNC_EVEN_VBI 0x00000207 |
| 49 | #define RISC_NOOP 0xF0000000 |
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 50 | |
Palash Bandyopadhyay | 6d8c2ba | 2010-07-04 14:15:38 -0300 | [diff] [blame] | 51 | /***************************************************************************** |
| 52 | * ASB SRAM |
| 53 | *****************************************************************************/ |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 54 | #define TX_SRAM 0x000000 /* Transmit SRAM */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 55 | |
Palash Bandyopadhyay | 6d8c2ba | 2010-07-04 14:15:38 -0300 | [diff] [blame] | 56 | /*****************************************************************************/ |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 57 | #define RX_RAM 0x010000 /* Receive SRAM */ |
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 58 | |
Palash Bandyopadhyay | 6d8c2ba | 2010-07-04 14:15:38 -0300 | [diff] [blame] | 59 | /***************************************************************************** |
| 60 | * Application Layer (AL) |
| 61 | *****************************************************************************/ |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 62 | #define DEV_CNTRL2 0x040000 /* Device control */ |
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 63 | #define FLD_RUN_RISC 0x00000020 |
| 64 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 65 | /* ***************************************************************************** */ |
| 66 | #define PCI_INT_MSK 0x040010 /* PCI interrupt mask */ |
| 67 | #define PCI_INT_STAT 0x040014 /* PCI interrupt status */ |
| 68 | #define PCI_INT_MSTAT 0x040018 /* PCI interrupt masked status */ |
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 69 | #define FLD_HAMMERHEAD_INT (1 << 27) |
| 70 | #define FLD_UART_INT (1 << 26) |
| 71 | #define FLD_IRQN_INT (1 << 25) |
| 72 | #define FLD_TM_INT (1 << 28) |
| 73 | #define FLD_I2C_3_RACK (1 << 27) |
| 74 | #define FLD_I2C_3_INT (1 << 26) |
| 75 | #define FLD_I2C_2_RACK (1 << 25) |
| 76 | #define FLD_I2C_2_INT (1 << 24) |
| 77 | #define FLD_I2C_1_RACK (1 << 23) |
| 78 | #define FLD_I2C_1_INT (1 << 22) |
| 79 | |
| 80 | #define FLD_APB_DMA_BERR_INT (1 << 21) |
| 81 | #define FLD_AL_WR_BERR_INT (1 << 20) |
| 82 | #define FLD_AL_RD_BERR_INT (1 << 19) |
| 83 | #define FLD_RISC_WR_BERR_INT (1 << 18) |
| 84 | #define FLD_RISC_RD_BERR_INT (1 << 17) |
| 85 | |
| 86 | #define FLD_VID_I_INT (1 << 8) |
| 87 | #define FLD_VID_H_INT (1 << 7) |
| 88 | #define FLD_VID_G_INT (1 << 6) |
| 89 | #define FLD_VID_F_INT (1 << 5) |
| 90 | #define FLD_VID_E_INT (1 << 4) |
| 91 | #define FLD_VID_D_INT (1 << 3) |
| 92 | #define FLD_VID_C_INT (1 << 2) |
| 93 | #define FLD_VID_B_INT (1 << 1) |
| 94 | #define FLD_VID_A_INT (1 << 0) |
| 95 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 96 | /* ***************************************************************************** */ |
| 97 | #define VID_A_INT_MSK 0x040020 /* Video A interrupt mask */ |
| 98 | #define VID_A_INT_STAT 0x040024 /* Video A interrupt status */ |
| 99 | #define VID_A_INT_MSTAT 0x040028 /* Video A interrupt masked status */ |
| 100 | #define VID_A_INT_SSTAT 0x04002C /* Video A interrupt set status */ |
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 101 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 102 | /* ***************************************************************************** */ |
| 103 | #define VID_B_INT_MSK 0x040030 /* Video B interrupt mask */ |
| 104 | #define VID_B_INT_STAT 0x040034 /* Video B interrupt status */ |
| 105 | #define VID_B_INT_MSTAT 0x040038 /* Video B interrupt masked status */ |
| 106 | #define VID_B_INT_SSTAT 0x04003C /* Video B interrupt set status */ |
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 107 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 108 | /* ***************************************************************************** */ |
| 109 | #define VID_C_INT_MSK 0x040040 /* Video C interrupt mask */ |
| 110 | #define VID_C_INT_STAT 0x040044 /* Video C interrupt status */ |
| 111 | #define VID_C_INT_MSTAT 0x040048 /* Video C interrupt masked status */ |
| 112 | #define VID_C_INT_SSTAT 0x04004C /* Video C interrupt set status */ |
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 113 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 114 | /* ***************************************************************************** */ |
| 115 | #define VID_D_INT_MSK 0x040050 /* Video D interrupt mask */ |
| 116 | #define VID_D_INT_STAT 0x040054 /* Video D interrupt status */ |
| 117 | #define VID_D_INT_MSTAT 0x040058 /* Video D interrupt masked status */ |
| 118 | #define VID_D_INT_SSTAT 0x04005C /* Video D interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 119 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 120 | /* ***************************************************************************** */ |
| 121 | #define VID_E_INT_MSK 0x040060 /* Video E interrupt mask */ |
| 122 | #define VID_E_INT_STAT 0x040064 /* Video E interrupt status */ |
| 123 | #define VID_E_INT_MSTAT 0x040068 /* Video E interrupt masked status */ |
| 124 | #define VID_E_INT_SSTAT 0x04006C /* Video E interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 125 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 126 | /* ***************************************************************************** */ |
| 127 | #define VID_F_INT_MSK 0x040070 /* Video F interrupt mask */ |
| 128 | #define VID_F_INT_STAT 0x040074 /* Video F interrupt status */ |
| 129 | #define VID_F_INT_MSTAT 0x040078 /* Video F interrupt masked status */ |
| 130 | #define VID_F_INT_SSTAT 0x04007C /* Video F interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 131 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 132 | /* ***************************************************************************** */ |
| 133 | #define VID_G_INT_MSK 0x040080 /* Video G interrupt mask */ |
| 134 | #define VID_G_INT_STAT 0x040084 /* Video G interrupt status */ |
| 135 | #define VID_G_INT_MSTAT 0x040088 /* Video G interrupt masked status */ |
| 136 | #define VID_G_INT_SSTAT 0x04008C /* Video G interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 137 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 138 | /* ***************************************************************************** */ |
| 139 | #define VID_H_INT_MSK 0x040090 /* Video H interrupt mask */ |
| 140 | #define VID_H_INT_STAT 0x040094 /* Video H interrupt status */ |
| 141 | #define VID_H_INT_MSTAT 0x040098 /* Video H interrupt masked status */ |
| 142 | #define VID_H_INT_SSTAT 0x04009C /* Video H interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 143 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 144 | /* ***************************************************************************** */ |
| 145 | #define VID_I_INT_MSK 0x0400A0 /* Video I interrupt mask */ |
| 146 | #define VID_I_INT_STAT 0x0400A4 /* Video I interrupt status */ |
| 147 | #define VID_I_INT_MSTAT 0x0400A8 /* Video I interrupt masked status */ |
| 148 | #define VID_I_INT_SSTAT 0x0400AC /* Video I interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 149 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 150 | /* ***************************************************************************** */ |
| 151 | #define VID_J_INT_MSK 0x0400B0 /* Video J interrupt mask */ |
| 152 | #define VID_J_INT_STAT 0x0400B4 /* Video J interrupt status */ |
| 153 | #define VID_J_INT_MSTAT 0x0400B8 /* Video J interrupt masked status */ |
| 154 | #define VID_J_INT_SSTAT 0x0400BC /* Video J interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 155 | |
| 156 | #define FLD_VID_SRC_OPC_ERR 0x00020000 |
| 157 | #define FLD_VID_DST_OPC_ERR 0x00010000 |
| 158 | #define FLD_VID_SRC_SYNC 0x00002000 |
| 159 | #define FLD_VID_DST_SYNC 0x00001000 |
| 160 | #define FLD_VID_SRC_UF 0x00000200 |
| 161 | #define FLD_VID_DST_OF 0x00000100 |
| 162 | #define FLD_VID_SRC_RISC2 0x00000020 |
| 163 | #define FLD_VID_DST_RISC2 0x00000010 |
| 164 | #define FLD_VID_SRC_RISC1 0x00000002 |
| 165 | #define FLD_VID_DST_RISC1 0x00000001 |
Ruslan Pisarev | e4115bb | 2010-09-27 10:01:36 -0300 | [diff] [blame] | 166 | #define FLD_VID_SRC_ERRORS (FLD_VID_SRC_OPC_ERR | FLD_VID_SRC_SYNC | FLD_VID_SRC_UF) |
| 167 | #define FLD_VID_DST_ERRORS (FLD_VID_DST_OPC_ERR | FLD_VID_DST_SYNC | FLD_VID_DST_OF) |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 168 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 169 | /* ***************************************************************************** */ |
| 170 | #define AUD_A_INT_MSK 0x0400C0 /* Audio Int interrupt mask */ |
| 171 | #define AUD_A_INT_STAT 0x0400C4 /* Audio Int interrupt status */ |
| 172 | #define AUD_A_INT_MSTAT 0x0400C8 /* Audio Int interrupt masked status */ |
| 173 | #define AUD_A_INT_SSTAT 0x0400CC /* Audio Int interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 174 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 175 | /* ***************************************************************************** */ |
| 176 | #define AUD_B_INT_MSK 0x0400D0 /* Audio Int interrupt mask */ |
| 177 | #define AUD_B_INT_STAT 0x0400D4 /* Audio Int interrupt status */ |
| 178 | #define AUD_B_INT_MSTAT 0x0400D8 /* Audio Int interrupt masked status */ |
| 179 | #define AUD_B_INT_SSTAT 0x0400DC /* Audio Int interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 180 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 181 | /* ***************************************************************************** */ |
| 182 | #define AUD_C_INT_MSK 0x0400E0 /* Audio Int interrupt mask */ |
| 183 | #define AUD_C_INT_STAT 0x0400E4 /* Audio Int interrupt status */ |
| 184 | #define AUD_C_INT_MSTAT 0x0400E8 /* Audio Int interrupt masked status */ |
| 185 | #define AUD_C_INT_SSTAT 0x0400EC /* Audio Int interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 186 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 187 | /* ***************************************************************************** */ |
| 188 | #define AUD_D_INT_MSK 0x0400F0 /* Audio Int interrupt mask */ |
| 189 | #define AUD_D_INT_STAT 0x0400F4 /* Audio Int interrupt status */ |
| 190 | #define AUD_D_INT_MSTAT 0x0400F8 /* Audio Int interrupt masked status */ |
| 191 | #define AUD_D_INT_SSTAT 0x0400FC /* Audio Int interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 192 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 193 | /* ***************************************************************************** */ |
| 194 | #define AUD_E_INT_MSK 0x040100 /* Audio Int interrupt mask */ |
| 195 | #define AUD_E_INT_STAT 0x040104 /* Audio Int interrupt status */ |
| 196 | #define AUD_E_INT_MSTAT 0x040108 /* Audio Int interrupt masked status */ |
| 197 | #define AUD_E_INT_SSTAT 0x04010C /* Audio Int interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 198 | |
| 199 | #define FLD_AUD_SRC_OPC_ERR 0x00020000 |
| 200 | #define FLD_AUD_DST_OPC_ERR 0x00010000 |
| 201 | #define FLD_AUD_SRC_SYNC 0x00002000 |
| 202 | #define FLD_AUD_DST_SYNC 0x00001000 |
| 203 | #define FLD_AUD_SRC_OF 0x00000200 |
| 204 | #define FLD_AUD_DST_OF 0x00000100 |
| 205 | #define FLD_AUD_SRC_RISCI2 0x00000020 |
| 206 | #define FLD_AUD_DST_RISCI2 0x00000010 |
| 207 | #define FLD_AUD_SRC_RISCI1 0x00000002 |
| 208 | #define FLD_AUD_DST_RISCI1 0x00000001 |
| 209 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 210 | /* ***************************************************************************** */ |
| 211 | #define MBIF_A_INT_MSK 0x040110 /* MBIF Int interrupt mask */ |
| 212 | #define MBIF_A_INT_STAT 0x040114 /* MBIF Int interrupt status */ |
| 213 | #define MBIF_A_INT_MSTAT 0x040118 /* MBIF Int interrupt masked status */ |
| 214 | #define MBIF_A_INT_SSTAT 0x04011C /* MBIF Int interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 215 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 216 | /* ***************************************************************************** */ |
| 217 | #define MBIF_B_INT_MSK 0x040120 /* MBIF Int interrupt mask */ |
| 218 | #define MBIF_B_INT_STAT 0x040124 /* MBIF Int interrupt status */ |
| 219 | #define MBIF_B_INT_MSTAT 0x040128 /* MBIF Int interrupt masked status */ |
| 220 | #define MBIF_B_INT_SSTAT 0x04012C /* MBIF Int interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 221 | |
| 222 | #define FLD_MBIF_DST_OPC_ERR 0x00010000 |
| 223 | #define FLD_MBIF_DST_SYNC 0x00001000 |
| 224 | #define FLD_MBIF_DST_OF 0x00000100 |
| 225 | #define FLD_MBIF_DST_RISCI2 0x00000010 |
| 226 | #define FLD_MBIF_DST_RISCI1 0x00000001 |
| 227 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 228 | /* ***************************************************************************** */ |
| 229 | #define AUD_EXT_INT_MSK 0x040060 /* Audio Ext interrupt mask */ |
| 230 | #define AUD_EXT_INT_STAT 0x040064 /* Audio Ext interrupt status */ |
| 231 | #define AUD_EXT_INT_MSTAT 0x040068 /* Audio Ext interrupt masked status */ |
| 232 | #define AUD_EXT_INT_SSTAT 0x04006C /* Audio Ext interrupt set status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 233 | #define FLD_AUD_EXT_OPC_ERR 0x00010000 |
| 234 | #define FLD_AUD_EXT_SYNC 0x00001000 |
| 235 | #define FLD_AUD_EXT_OF 0x00000100 |
| 236 | #define FLD_AUD_EXT_RISCI2 0x00000010 |
| 237 | #define FLD_AUD_EXT_RISCI1 0x00000001 |
| 238 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 239 | /* ***************************************************************************** */ |
| 240 | #define GPIO_LO 0x110010 /* Lower of GPIO pins [31:0] */ |
| 241 | #define GPIO_HI 0x110014 /* Upper WORD of GPIO pins [47:31] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 242 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 243 | #define GPIO_LO_OE 0x110018 /* Lower of GPIO output enable [31:0] */ |
| 244 | #define GPIO_HI_OE 0x11001C /* Upper word of GPIO output enable [47:32] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 245 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 246 | #define GPIO_LO_INT_MSK 0x11003C /* GPIO interrupt mask */ |
| 247 | #define GPIO_LO_INT_STAT 0x110044 /* GPIO interrupt status */ |
| 248 | #define GPIO_LO_INT_MSTAT 0x11004C /* GPIO interrupt masked status */ |
| 249 | #define GPIO_LO_ISM_SNS 0x110054 /* GPIO interrupt sensitivity */ |
| 250 | #define GPIO_LO_ISM_POL 0x11005C /* GPIO interrupt polarity */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 251 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 252 | #define GPIO_HI_INT_MSK 0x110040 /* GPIO interrupt mask */ |
| 253 | #define GPIO_HI_INT_STAT 0x110048 /* GPIO interrupt status */ |
| 254 | #define GPIO_HI_INT_MSTAT 0x110050 /* GPIO interrupt masked status */ |
| 255 | #define GPIO_HI_ISM_SNS 0x110058 /* GPIO interrupt sensitivity */ |
| 256 | #define GPIO_HI_ISM_POL 0x110060 /* GPIO interrupt polarity */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 257 | |
| 258 | #define FLD_GPIO43_INT (1 << 11) |
| 259 | #define FLD_GPIO42_INT (1 << 10) |
| 260 | #define FLD_GPIO41_INT (1 << 9) |
| 261 | #define FLD_GPIO40_INT (1 << 8) |
| 262 | |
| 263 | #define FLD_GPIO9_INT (1 << 9) |
| 264 | #define FLD_GPIO8_INT (1 << 8) |
| 265 | #define FLD_GPIO7_INT (1 << 7) |
| 266 | #define FLD_GPIO6_INT (1 << 6) |
| 267 | #define FLD_GPIO5_INT (1 << 5) |
| 268 | #define FLD_GPIO4_INT (1 << 4) |
| 269 | #define FLD_GPIO3_INT (1 << 3) |
| 270 | #define FLD_GPIO2_INT (1 << 2) |
| 271 | #define FLD_GPIO1_INT (1 << 1) |
| 272 | #define FLD_GPIO0_INT (1 << 0) |
| 273 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 274 | /* ***************************************************************************** */ |
| 275 | #define TC_REQ 0x040090 /* Rider PCI Express traFFic class request */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 276 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 277 | /* ***************************************************************************** */ |
| 278 | #define TC_REQ_SET 0x040094 /* Rider PCI Express traFFic class request set */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 279 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 280 | /* ***************************************************************************** */ |
| 281 | /* Rider */ |
| 282 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 283 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 284 | /* PCI Compatible Header */ |
| 285 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 286 | #define RDR_CFG0 0x050000 |
| 287 | #define RDR_VENDOR_DEVICE_ID_CFG 0x050000 |
| 288 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 289 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 290 | #define RDR_CFG1 0x050004 |
| 291 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 292 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 293 | #define RDR_CFG2 0x050008 |
| 294 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 295 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 296 | #define RDR_CFG3 0x05000C |
| 297 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 298 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 299 | #define RDR_CFG4 0x050010 |
| 300 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 301 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 302 | #define RDR_CFG5 0x050014 |
| 303 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 304 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 305 | #define RDR_CFG6 0x050018 |
| 306 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 307 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 308 | #define RDR_CFG7 0x05001C |
| 309 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 310 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 311 | #define RDR_CFG8 0x050020 |
| 312 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 313 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 314 | #define RDR_CFG9 0x050024 |
| 315 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 316 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 317 | #define RDR_CFGA 0x050028 |
| 318 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 319 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 320 | #define RDR_CFGB 0x05002C |
| 321 | #define RDR_SUSSYSTEM_ID_CFG 0x05002C |
| 322 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 323 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 324 | #define RDR_CFGC 0x050030 |
| 325 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 326 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 327 | #define RDR_CFGD 0x050034 |
| 328 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 329 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 330 | #define RDR_CFGE 0x050038 |
| 331 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 332 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 333 | #define RDR_CFGF 0x05003C |
| 334 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 335 | /* ***************************************************************************** */ |
| 336 | /* PCI-Express Capabilities */ |
| 337 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 338 | #define RDR_PECAP 0x050040 |
| 339 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 340 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 341 | #define RDR_PEDEVCAP 0x050044 |
| 342 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 343 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 344 | #define RDR_PEDEVSC 0x050048 |
| 345 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 346 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 347 | #define RDR_PELINKCAP 0x05004C |
| 348 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 349 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 350 | #define RDR_PELINKSC 0x050050 |
| 351 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 352 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 353 | #define RDR_PMICAP 0x050080 |
| 354 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 355 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 356 | #define RDR_PMCSR 0x050084 |
| 357 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 358 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 359 | #define RDR_VPDCAP 0x050090 |
| 360 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 361 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 362 | #define RDR_VPDDATA 0x050094 |
| 363 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 364 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 365 | #define RDR_MSICAP 0x0500A0 |
| 366 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 367 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 368 | #define RDR_MSIARL 0x0500A4 |
| 369 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 370 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 371 | #define RDR_MSIARU 0x0500A8 |
| 372 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 373 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 374 | #define RDR_MSIDATA 0x0500AC |
| 375 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 376 | /* ***************************************************************************** */ |
| 377 | /* PCI Express Extended Capabilities */ |
| 378 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 379 | #define RDR_AERXCAP 0x050100 |
| 380 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 381 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 382 | #define RDR_AERUESTA 0x050104 |
| 383 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 384 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 385 | #define RDR_AERUEMSK 0x050108 |
| 386 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 387 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 388 | #define RDR_AERUESEV 0x05010C |
| 389 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 390 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 391 | #define RDR_AERCESTA 0x050110 |
| 392 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 393 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 394 | #define RDR_AERCEMSK 0x050114 |
| 395 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 396 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 397 | #define RDR_AERCC 0x050118 |
| 398 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 399 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 400 | #define RDR_AERHL0 0x05011C |
| 401 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 402 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 403 | #define RDR_AERHL1 0x050120 |
| 404 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 405 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 406 | #define RDR_AERHL2 0x050124 |
| 407 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 408 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 409 | #define RDR_AERHL3 0x050128 |
| 410 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 411 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 412 | #define RDR_VCXCAP 0x050200 |
| 413 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 414 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 415 | #define RDR_VCCAP1 0x050204 |
| 416 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 417 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 418 | #define RDR_VCCAP2 0x050208 |
| 419 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 420 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 421 | #define RDR_VCSC 0x05020C |
| 422 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 423 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 424 | #define RDR_VCR0_CAP 0x050210 |
| 425 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 426 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 427 | #define RDR_VCR0_CTRL 0x050214 |
| 428 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 429 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 430 | #define RDR_VCR0_STAT 0x050218 |
| 431 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 432 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 433 | #define RDR_VCR1_CAP 0x05021C |
| 434 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 435 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 436 | #define RDR_VCR1_CTRL 0x050220 |
| 437 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 438 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 439 | #define RDR_VCR1_STAT 0x050224 |
| 440 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 441 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 442 | #define RDR_VCR2_CAP 0x050228 |
| 443 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 444 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 445 | #define RDR_VCR2_CTRL 0x05022C |
| 446 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 447 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 448 | #define RDR_VCR2_STAT 0x050230 |
| 449 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 450 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 451 | #define RDR_VCR3_CAP 0x050234 |
| 452 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 453 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 454 | #define RDR_VCR3_CTRL 0x050238 |
| 455 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 456 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 457 | #define RDR_VCR3_STAT 0x05023C |
| 458 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 459 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 460 | #define RDR_VCARB0 0x050240 |
| 461 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 462 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 463 | #define RDR_VCARB1 0x050244 |
| 464 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 465 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 466 | #define RDR_VCARB2 0x050248 |
| 467 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 468 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 469 | #define RDR_VCARB3 0x05024C |
| 470 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 471 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 472 | #define RDR_VCARB4 0x050250 |
| 473 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 474 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 475 | #define RDR_VCARB5 0x050254 |
| 476 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 477 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 478 | #define RDR_VCARB6 0x050258 |
| 479 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 480 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 481 | #define RDR_VCARB7 0x05025C |
| 482 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 483 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 484 | #define RDR_RDRSTAT0 0x050300 |
| 485 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 486 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 487 | #define RDR_RDRSTAT1 0x050304 |
| 488 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 489 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 490 | #define RDR_RDRCTL0 0x050308 |
| 491 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 492 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 493 | #define RDR_RDRCTL1 0x05030C |
| 494 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 495 | /* ***************************************************************************** */ |
| 496 | /* Transaction Layer Registers */ |
| 497 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 498 | #define RDR_TLSTAT0 0x050310 |
| 499 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 500 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 501 | #define RDR_TLSTAT1 0x050314 |
| 502 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 503 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 504 | #define RDR_TLCTL0 0x050318 |
| 505 | #define FLD_CFG_UR_CPL_MODE 0x00000040 |
| 506 | #define FLD_CFG_CORR_ERR_QUITE 0x00000020 |
| 507 | #define FLD_CFG_RCB_CK_EN 0x00000010 |
| 508 | #define FLD_CFG_BNDRY_CK_EN 0x00000008 |
| 509 | #define FLD_CFG_BYTE_EN_CK_EN 0x00000004 |
| 510 | #define FLD_CFG_RELAX_ORDER_MSK 0x00000002 |
| 511 | #define FLD_CFG_TAG_ORDER_EN 0x00000001 |
| 512 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 513 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 514 | #define RDR_TLCTL1 0x05031C |
| 515 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 516 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 517 | #define RDR_REQRCAL 0x050320 |
| 518 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 519 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 520 | #define RDR_REQRCAU 0x050324 |
| 521 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 522 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 523 | #define RDR_REQEPA 0x050328 |
| 524 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 525 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 526 | #define RDR_REQCTRL 0x05032C |
| 527 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 528 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 529 | #define RDR_REQSTAT 0x050330 |
| 530 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 531 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 532 | #define RDR_TL_TEST 0x050334 |
| 533 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 534 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 535 | #define RDR_VCR01_CTL 0x050348 |
| 536 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 537 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 538 | #define RDR_VCR23_CTL 0x05034C |
| 539 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 540 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 541 | #define RDR_RX_VCR0_FC 0x050350 |
| 542 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 543 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 544 | #define RDR_RX_VCR1_FC 0x050354 |
| 545 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 546 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 547 | #define RDR_RX_VCR2_FC 0x050358 |
| 548 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 549 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 550 | #define RDR_RX_VCR3_FC 0x05035C |
| 551 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 552 | /* ***************************************************************************** */ |
| 553 | /* Data Link Layer Registers */ |
| 554 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 555 | #define RDR_DLLSTAT 0x050360 |
| 556 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 557 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 558 | #define RDR_DLLCTRL 0x050364 |
| 559 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 560 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 561 | #define RDR_REPLAYTO 0x050368 |
| 562 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 563 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 564 | #define RDR_ACKLATTO 0x05036C |
| 565 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 566 | /* ***************************************************************************** */ |
| 567 | /* MAC Layer Registers */ |
| 568 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 569 | #define RDR_MACSTAT0 0x050380 |
| 570 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 571 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 572 | #define RDR_MACSTAT1 0x050384 |
| 573 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 574 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 575 | #define RDR_MACCTRL0 0x050388 |
| 576 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 577 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 578 | #define RDR_MACCTRL1 0x05038C |
| 579 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 580 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 581 | #define RDR_MACCTRL2 0x050390 |
| 582 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 583 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 584 | #define RDR_MAC_LB_DATA 0x050394 |
| 585 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 586 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 587 | #define RDR_L0S_EXIT_LAT 0x050398 |
| 588 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 589 | /* ***************************************************************************** */ |
| 590 | /* DMAC */ |
| 591 | /* ***************************************************************************** */ |
| 592 | #define DMA1_PTR1 0x100000 /* DMA Current Ptr : Ch#1 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 593 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 594 | /* ***************************************************************************** */ |
| 595 | #define DMA2_PTR1 0x100004 /* DMA Current Ptr : Ch#2 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 596 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 597 | /* ***************************************************************************** */ |
| 598 | #define DMA3_PTR1 0x100008 /* DMA Current Ptr : Ch#3 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 599 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 600 | /* ***************************************************************************** */ |
| 601 | #define DMA4_PTR1 0x10000C /* DMA Current Ptr : Ch#4 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 602 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 603 | /* ***************************************************************************** */ |
| 604 | #define DMA5_PTR1 0x100010 /* DMA Current Ptr : Ch#5 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 605 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 606 | /* ***************************************************************************** */ |
| 607 | #define DMA6_PTR1 0x100014 /* DMA Current Ptr : Ch#6 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 608 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 609 | /* ***************************************************************************** */ |
| 610 | #define DMA7_PTR1 0x100018 /* DMA Current Ptr : Ch#7 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 611 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 612 | /* ***************************************************************************** */ |
| 613 | #define DMA8_PTR1 0x10001C /* DMA Current Ptr : Ch#8 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 614 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 615 | /* ***************************************************************************** */ |
| 616 | #define DMA9_PTR1 0x100020 /* DMA Current Ptr : Ch#9 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 617 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 618 | /* ***************************************************************************** */ |
| 619 | #define DMA10_PTR1 0x100024 /* DMA Current Ptr : Ch#10 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 620 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 621 | /* ***************************************************************************** */ |
| 622 | #define DMA11_PTR1 0x100028 /* DMA Current Ptr : Ch#11 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 623 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 624 | /* ***************************************************************************** */ |
| 625 | #define DMA12_PTR1 0x10002C /* DMA Current Ptr : Ch#12 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 626 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 627 | /* ***************************************************************************** */ |
| 628 | #define DMA13_PTR1 0x100030 /* DMA Current Ptr : Ch#13 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 629 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 630 | /* ***************************************************************************** */ |
| 631 | #define DMA14_PTR1 0x100034 /* DMA Current Ptr : Ch#14 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 632 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 633 | /* ***************************************************************************** */ |
| 634 | #define DMA15_PTR1 0x100038 /* DMA Current Ptr : Ch#15 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 635 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 636 | /* ***************************************************************************** */ |
| 637 | #define DMA16_PTR1 0x10003C /* DMA Current Ptr : Ch#16 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 638 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 639 | /* ***************************************************************************** */ |
| 640 | #define DMA17_PTR1 0x100040 /* DMA Current Ptr : Ch#17 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 641 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 642 | /* ***************************************************************************** */ |
| 643 | #define DMA18_PTR1 0x100044 /* DMA Current Ptr : Ch#18 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 644 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 645 | /* ***************************************************************************** */ |
| 646 | #define DMA19_PTR1 0x100048 /* DMA Current Ptr : Ch#19 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 647 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 648 | /* ***************************************************************************** */ |
| 649 | #define DMA20_PTR1 0x10004C /* DMA Current Ptr : Ch#20 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 650 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 651 | /* ***************************************************************************** */ |
| 652 | #define DMA21_PTR1 0x100050 /* DMA Current Ptr : Ch#21 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 653 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 654 | /* ***************************************************************************** */ |
| 655 | #define DMA22_PTR1 0x100054 /* DMA Current Ptr : Ch#22 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 656 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 657 | /* ***************************************************************************** */ |
| 658 | #define DMA23_PTR1 0x100058 /* DMA Current Ptr : Ch#23 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 659 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 660 | /* ***************************************************************************** */ |
| 661 | #define DMA24_PTR1 0x10005C /* DMA Current Ptr : Ch#24 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 662 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 663 | /* ***************************************************************************** */ |
| 664 | #define DMA25_PTR1 0x100060 /* DMA Current Ptr : Ch#25 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 665 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 666 | /* ***************************************************************************** */ |
| 667 | #define DMA26_PTR1 0x100064 /* DMA Current Ptr : Ch#26 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 668 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 669 | /* ***************************************************************************** */ |
| 670 | #define DMA1_PTR2 0x100080 /* DMA Tab Ptr : Ch#1 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 671 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 672 | /* ***************************************************************************** */ |
| 673 | #define DMA2_PTR2 0x100084 /* DMA Tab Ptr : Ch#2 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 674 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 675 | /* ***************************************************************************** */ |
| 676 | #define DMA3_PTR2 0x100088 /* DMA Tab Ptr : Ch#3 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 677 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 678 | /* ***************************************************************************** */ |
| 679 | #define DMA4_PTR2 0x10008C /* DMA Tab Ptr : Ch#4 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 680 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 681 | /* ***************************************************************************** */ |
| 682 | #define DMA5_PTR2 0x100090 /* DMA Tab Ptr : Ch#5 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 683 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 684 | /* ***************************************************************************** */ |
| 685 | #define DMA6_PTR2 0x100094 /* DMA Tab Ptr : Ch#6 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 686 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 687 | /* ***************************************************************************** */ |
| 688 | #define DMA7_PTR2 0x100098 /* DMA Tab Ptr : Ch#7 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 689 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 690 | /* ***************************************************************************** */ |
| 691 | #define DMA8_PTR2 0x10009C /* DMA Tab Ptr : Ch#8 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 692 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 693 | /* ***************************************************************************** */ |
| 694 | #define DMA9_PTR2 0x1000A0 /* DMA Tab Ptr : Ch#9 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 695 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 696 | /* ***************************************************************************** */ |
| 697 | #define DMA10_PTR2 0x1000A4 /* DMA Tab Ptr : Ch#10 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 698 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 699 | /* ***************************************************************************** */ |
| 700 | #define DMA11_PTR2 0x1000A8 /* DMA Tab Ptr : Ch#11 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 701 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 702 | /* ***************************************************************************** */ |
| 703 | #define DMA12_PTR2 0x1000AC /* DMA Tab Ptr : Ch#12 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 704 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 705 | /* ***************************************************************************** */ |
| 706 | #define DMA13_PTR2 0x1000B0 /* DMA Tab Ptr : Ch#13 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 707 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 708 | /* ***************************************************************************** */ |
| 709 | #define DMA14_PTR2 0x1000B4 /* DMA Tab Ptr : Ch#14 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 710 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 711 | /* ***************************************************************************** */ |
| 712 | #define DMA15_PTR2 0x1000B8 /* DMA Tab Ptr : Ch#15 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 713 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 714 | /* ***************************************************************************** */ |
| 715 | #define DMA16_PTR2 0x1000BC /* DMA Tab Ptr : Ch#16 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 716 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 717 | /* ***************************************************************************** */ |
| 718 | #define DMA17_PTR2 0x1000C0 /* DMA Tab Ptr : Ch#17 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 719 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 720 | /* ***************************************************************************** */ |
| 721 | #define DMA18_PTR2 0x1000C4 /* DMA Tab Ptr : Ch#18 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 722 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 723 | /* ***************************************************************************** */ |
| 724 | #define DMA19_PTR2 0x1000C8 /* DMA Tab Ptr : Ch#19 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 725 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 726 | /* ***************************************************************************** */ |
| 727 | #define DMA20_PTR2 0x1000CC /* DMA Tab Ptr : Ch#20 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 728 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 729 | /* ***************************************************************************** */ |
| 730 | #define DMA21_PTR2 0x1000D0 /* DMA Tab Ptr : Ch#21 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 731 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 732 | /* ***************************************************************************** */ |
| 733 | #define DMA22_PTR2 0x1000D4 /* DMA Tab Ptr : Ch#22 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 734 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 735 | /* ***************************************************************************** */ |
| 736 | #define DMA23_PTR2 0x1000D8 /* DMA Tab Ptr : Ch#23 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 737 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 738 | /* ***************************************************************************** */ |
| 739 | #define DMA24_PTR2 0x1000DC /* DMA Tab Ptr : Ch#24 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 740 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 741 | /* ***************************************************************************** */ |
| 742 | #define DMA25_PTR2 0x1000E0 /* DMA Tab Ptr : Ch#25 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 743 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 744 | /* ***************************************************************************** */ |
| 745 | #define DMA26_PTR2 0x1000E4 /* DMA Tab Ptr : Ch#26 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 746 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 747 | /* ***************************************************************************** */ |
| 748 | #define DMA1_CNT1 0x100100 /* DMA BuFFer Size : Ch#1 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 749 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 750 | /* ***************************************************************************** */ |
| 751 | #define DMA2_CNT1 0x100104 /* DMA BuFFer Size : Ch#2 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 752 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 753 | /* ***************************************************************************** */ |
| 754 | #define DMA3_CNT1 0x100108 /* DMA BuFFer Size : Ch#3 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 755 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 756 | /* ***************************************************************************** */ |
| 757 | #define DMA4_CNT1 0x10010C /* DMA BuFFer Size : Ch#4 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 758 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 759 | /* ***************************************************************************** */ |
| 760 | #define DMA5_CNT1 0x100110 /* DMA BuFFer Size : Ch#5 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 761 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 762 | /* ***************************************************************************** */ |
| 763 | #define DMA6_CNT1 0x100114 /* DMA BuFFer Size : Ch#6 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 764 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 765 | /* ***************************************************************************** */ |
| 766 | #define DMA7_CNT1 0x100118 /* DMA BuFFer Size : Ch#7 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 767 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 768 | /* ***************************************************************************** */ |
| 769 | #define DMA8_CNT1 0x10011C /* DMA BuFFer Size : Ch#8 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 770 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 771 | /* ***************************************************************************** */ |
| 772 | #define DMA9_CNT1 0x100120 /* DMA BuFFer Size : Ch#9 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 773 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 774 | /* ***************************************************************************** */ |
| 775 | #define DMA10_CNT1 0x100124 /* DMA BuFFer Size : Ch#10 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 776 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 777 | /* ***************************************************************************** */ |
| 778 | #define DMA11_CNT1 0x100128 /* DMA BuFFer Size : Ch#11 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 779 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 780 | /* ***************************************************************************** */ |
| 781 | #define DMA12_CNT1 0x10012C /* DMA BuFFer Size : Ch#12 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 782 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 783 | /* ***************************************************************************** */ |
| 784 | #define DMA13_CNT1 0x100130 /* DMA BuFFer Size : Ch#13 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 785 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 786 | /* ***************************************************************************** */ |
| 787 | #define DMA14_CNT1 0x100134 /* DMA BuFFer Size : Ch#14 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 788 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 789 | /* ***************************************************************************** */ |
| 790 | #define DMA15_CNT1 0x100138 /* DMA BuFFer Size : Ch#15 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 791 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 792 | /* ***************************************************************************** */ |
| 793 | #define DMA16_CNT1 0x10013C /* DMA BuFFer Size : Ch#16 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 794 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 795 | /* ***************************************************************************** */ |
| 796 | #define DMA17_CNT1 0x100140 /* DMA BuFFer Size : Ch#17 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 797 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 798 | /* ***************************************************************************** */ |
| 799 | #define DMA18_CNT1 0x100144 /* DMA BuFFer Size : Ch#18 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 800 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 801 | /* ***************************************************************************** */ |
| 802 | #define DMA19_CNT1 0x100148 /* DMA BuFFer Size : Ch#19 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 803 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 804 | /* ***************************************************************************** */ |
| 805 | #define DMA20_CNT1 0x10014C /* DMA BuFFer Size : Ch#20 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 806 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 807 | /* ***************************************************************************** */ |
| 808 | #define DMA21_CNT1 0x100150 /* DMA BuFFer Size : Ch#21 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 809 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 810 | /* ***************************************************************************** */ |
| 811 | #define DMA22_CNT1 0x100154 /* DMA BuFFer Size : Ch#22 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 812 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 813 | /* ***************************************************************************** */ |
| 814 | #define DMA23_CNT1 0x100158 /* DMA BuFFer Size : Ch#23 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 815 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 816 | /* ***************************************************************************** */ |
| 817 | #define DMA24_CNT1 0x10015C /* DMA BuFFer Size : Ch#24 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 818 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 819 | /* ***************************************************************************** */ |
| 820 | #define DMA25_CNT1 0x100160 /* DMA BuFFer Size : Ch#25 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 821 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 822 | /* ***************************************************************************** */ |
| 823 | #define DMA26_CNT1 0x100164 /* DMA BuFFer Size : Ch#26 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 824 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 825 | /* ***************************************************************************** */ |
| 826 | #define DMA1_CNT2 0x100180 /* DMA Table Size : Ch#1 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 827 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 828 | /* ***************************************************************************** */ |
| 829 | #define DMA2_CNT2 0x100184 /* DMA Table Size : Ch#2 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 830 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 831 | /* ***************************************************************************** */ |
| 832 | #define DMA3_CNT2 0x100188 /* DMA Table Size : Ch#3 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 833 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 834 | /* ***************************************************************************** */ |
| 835 | #define DMA4_CNT2 0x10018C /* DMA Table Size : Ch#4 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 836 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 837 | /* ***************************************************************************** */ |
| 838 | #define DMA5_CNT2 0x100190 /* DMA Table Size : Ch#5 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 839 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 840 | /* ***************************************************************************** */ |
| 841 | #define DMA6_CNT2 0x100194 /* DMA Table Size : Ch#6 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 842 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 843 | /* ***************************************************************************** */ |
| 844 | #define DMA7_CNT2 0x100198 /* DMA Table Size : Ch#7 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 845 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 846 | /* ***************************************************************************** */ |
| 847 | #define DMA8_CNT2 0x10019C /* DMA Table Size : Ch#8 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 848 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 849 | /* ***************************************************************************** */ |
| 850 | #define DMA9_CNT2 0x1001A0 /* DMA Table Size : Ch#9 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 851 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 852 | /* ***************************************************************************** */ |
| 853 | #define DMA10_CNT2 0x1001A4 /* DMA Table Size : Ch#10 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 854 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 855 | /* ***************************************************************************** */ |
| 856 | #define DMA11_CNT2 0x1001A8 /* DMA Table Size : Ch#11 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 857 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 858 | /* ***************************************************************************** */ |
| 859 | #define DMA12_CNT2 0x1001AC /* DMA Table Size : Ch#12 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 860 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 861 | /* ***************************************************************************** */ |
| 862 | #define DMA13_CNT2 0x1001B0 /* DMA Table Size : Ch#13 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 863 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 864 | /* ***************************************************************************** */ |
| 865 | #define DMA14_CNT2 0x1001B4 /* DMA Table Size : Ch#14 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 866 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 867 | /* ***************************************************************************** */ |
| 868 | #define DMA15_CNT2 0x1001B8 /* DMA Table Size : Ch#15 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 869 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 870 | /* ***************************************************************************** */ |
| 871 | #define DMA16_CNT2 0x1001BC /* DMA Table Size : Ch#16 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 872 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 873 | /* ***************************************************************************** */ |
| 874 | #define DMA17_CNT2 0x1001C0 /* DMA Table Size : Ch#17 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 875 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 876 | /* ***************************************************************************** */ |
| 877 | #define DMA18_CNT2 0x1001C4 /* DMA Table Size : Ch#18 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 878 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 879 | /* ***************************************************************************** */ |
| 880 | #define DMA19_CNT2 0x1001C8 /* DMA Table Size : Ch#19 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 881 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 882 | /* ***************************************************************************** */ |
| 883 | #define DMA20_CNT2 0x1001CC /* DMA Table Size : Ch#20 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 884 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 885 | /* ***************************************************************************** */ |
| 886 | #define DMA21_CNT2 0x1001D0 /* DMA Table Size : Ch#21 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 887 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 888 | /* ***************************************************************************** */ |
| 889 | #define DMA22_CNT2 0x1001D4 /* DMA Table Size : Ch#22 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 890 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 891 | /* ***************************************************************************** */ |
| 892 | #define DMA23_CNT2 0x1001D8 /* DMA Table Size : Ch#23 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 893 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 894 | /* ***************************************************************************** */ |
| 895 | #define DMA24_CNT2 0x1001DC /* DMA Table Size : Ch#24 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 896 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 897 | /* ***************************************************************************** */ |
| 898 | #define DMA25_CNT2 0x1001E0 /* DMA Table Size : Ch#25 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 899 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 900 | /* ***************************************************************************** */ |
| 901 | #define DMA26_CNT2 0x1001E4 /* DMA Table Size : Ch#26 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 902 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 903 | /* ***************************************************************************** */ |
| 904 | /* ITG */ |
| 905 | /* ***************************************************************************** */ |
| 906 | #define TM_CNT_LDW 0x110000 /* Timer : Counter low */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 907 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 908 | /* ***************************************************************************** */ |
| 909 | #define TM_CNT_UW 0x110004 /* Timer : Counter high word */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 910 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 911 | /* ***************************************************************************** */ |
| 912 | #define TM_LMT_LDW 0x110008 /* Timer : Limit low */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 913 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 914 | /* ***************************************************************************** */ |
| 915 | #define TM_LMT_UW 0x11000C /* Timer : Limit high word */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 916 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 917 | /* ***************************************************************************** */ |
| 918 | #define GP0_IO 0x110010 /* GPIO output enables data I/O */ |
| 919 | #define FLD_GP_OE 0x00FF0000 /* GPIO: GP_OE output enable */ |
| 920 | #define FLD_GP_IN 0x0000FF00 /* GPIO: GP_IN status */ |
| 921 | #define FLD_GP_OUT 0x000000FF /* GPIO: GP_OUT control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 922 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 923 | /* ***************************************************************************** */ |
| 924 | #define GPIO_ISM 0x110014 /* GPIO interrupt sensitivity mode */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 925 | #define FLD_GP_ISM_SNS 0x00000070 |
| 926 | #define FLD_GP_ISM_POL 0x00000007 |
| 927 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 928 | /* ***************************************************************************** */ |
| 929 | #define SOFT_RESET 0x11001C /* Output system reset reg */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 930 | #define FLD_PECOS_SOFT_RESET 0x00000001 |
| 931 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 932 | /* ***************************************************************************** */ |
| 933 | #define MC416_RWD 0x110020 /* MC416 GPIO[18:3] pin */ |
| 934 | #define MC416_OEN 0x110024 /* Output enable of GPIO[18:3] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 935 | #define MC416_CTL 0x110028 |
| 936 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 937 | /* ***************************************************************************** */ |
| 938 | #define ALT_PIN_OUT_SEL 0x11002C /* Alternate GPIO output select */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 939 | |
| 940 | #define FLD_ALT_GPIO_OUT_SEL 0xF0000000 |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 941 | /* 0 Disabled <-- default */ |
| 942 | /* 1 GPIO[0] */ |
| 943 | /* 2 GPIO[10] */ |
| 944 | /* 3 VIP_656_DATA_VAL */ |
| 945 | /* 4 VIP_656_DATA[0] */ |
| 946 | /* 5 VIP_656_CLK */ |
| 947 | /* 6 VIP_656_DATA_EXT[1] */ |
| 948 | /* 7 VIP_656_DATA_EXT[0] */ |
| 949 | /* 8 ATT_IF */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 950 | |
| 951 | #define FLD_AUX_PLL_CLK_ALT_SEL 0x0F000000 |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 952 | /* 0 AUX_PLL_CLK<-- default */ |
| 953 | /* 1 GPIO[2] */ |
| 954 | /* 2 GPIO[10] */ |
| 955 | /* 3 VIP_656_DATA_VAL */ |
| 956 | /* 4 VIP_656_DATA[0] */ |
| 957 | /* 5 VIP_656_CLK */ |
| 958 | /* 6 VIP_656_DATA_EXT[1] */ |
| 959 | /* 7 VIP_656_DATA_EXT[0] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 960 | |
| 961 | #define FLD_IR_TX_ALT_SEL 0x00F00000 |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 962 | /* 0 IR_TX <-- default */ |
| 963 | /* 1 GPIO[1] */ |
| 964 | /* 2 GPIO[10] */ |
| 965 | /* 3 VIP_656_DATA_VAL */ |
| 966 | /* 4 VIP_656_DATA[0] */ |
| 967 | /* 5 VIP_656_CLK */ |
| 968 | /* 6 VIP_656_DATA_EXT[1] */ |
| 969 | /* 7 VIP_656_DATA_EXT[0] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 970 | |
| 971 | #define FLD_IR_RX_ALT_SEL 0x000F0000 |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 972 | /* 0 IR_RX <-- default */ |
| 973 | /* 1 GPIO[0] */ |
| 974 | /* 2 GPIO[10] */ |
| 975 | /* 3 VIP_656_DATA_VAL */ |
| 976 | /* 4 VIP_656_DATA[0] */ |
| 977 | /* 5 VIP_656_CLK */ |
| 978 | /* 6 VIP_656_DATA_EXT[1] */ |
| 979 | /* 7 VIP_656_DATA_EXT[0] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 980 | |
| 981 | #define FLD_GPIO10_ALT_SEL 0x0000F000 |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 982 | /* 0 GPIO[10] <-- default */ |
| 983 | /* 1 GPIO[0] */ |
| 984 | /* 2 GPIO[10] */ |
| 985 | /* 3 VIP_656_DATA_VAL */ |
| 986 | /* 4 VIP_656_DATA[0] */ |
| 987 | /* 5 VIP_656_CLK */ |
| 988 | /* 6 VIP_656_DATA_EXT[1] */ |
| 989 | /* 7 VIP_656_DATA_EXT[0] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 990 | |
| 991 | #define FLD_GPIO2_ALT_SEL 0x00000F00 |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 992 | /* 0 GPIO[2] <-- default */ |
| 993 | /* 1 GPIO[1] */ |
| 994 | /* 2 GPIO[10] */ |
| 995 | /* 3 VIP_656_DATA_VAL */ |
| 996 | /* 4 VIP_656_DATA[0] */ |
| 997 | /* 5 VIP_656_CLK */ |
| 998 | /* 6 VIP_656_DATA_EXT[1] */ |
| 999 | /* 7 VIP_656_DATA_EXT[0] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1000 | |
| 1001 | #define FLD_GPIO1_ALT_SEL 0x000000F0 |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1002 | /* 0 GPIO[1] <-- default */ |
| 1003 | /* 1 GPIO[0] */ |
| 1004 | /* 2 GPIO[10] */ |
| 1005 | /* 3 VIP_656_DATA_VAL */ |
| 1006 | /* 4 VIP_656_DATA[0] */ |
| 1007 | /* 5 VIP_656_CLK */ |
| 1008 | /* 6 VIP_656_DATA_EXT[1] */ |
| 1009 | /* 7 VIP_656_DATA_EXT[0] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1010 | |
| 1011 | #define FLD_GPIO0_ALT_SEL 0x0000000F |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1012 | /* 0 GPIO[0] <-- default */ |
| 1013 | /* 1 GPIO[1] */ |
| 1014 | /* 2 GPIO[10] */ |
| 1015 | /* 3 VIP_656_DATA_VAL */ |
| 1016 | /* 4 VIP_656_DATA[0] */ |
| 1017 | /* 5 VIP_656_CLK */ |
| 1018 | /* 6 VIP_656_DATA_EXT[1] */ |
| 1019 | /* 7 VIP_656_DATA_EXT[0] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1020 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1021 | #define ALT_PIN_IN_SEL 0x110030 /* Alternate GPIO input select */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1022 | |
| 1023 | #define FLD_GPIO10_ALT_IN_SEL 0x0000F000 |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1024 | /* 0 GPIO[10] <-- default */ |
| 1025 | /* 1 IR_RX */ |
| 1026 | /* 2 IR_TX */ |
| 1027 | /* 3 AUX_PLL_CLK */ |
| 1028 | /* 4 IF_ATT_SEL */ |
| 1029 | /* 5 GPIO[0] */ |
| 1030 | /* 6 GPIO[1] */ |
| 1031 | /* 7 GPIO[2] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1032 | |
| 1033 | #define FLD_GPIO2_ALT_IN_SEL 0x00000F00 |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1034 | /* 0 GPIO[2] <-- default */ |
| 1035 | /* 1 IR_RX */ |
| 1036 | /* 2 IR_TX */ |
| 1037 | /* 3 AUX_PLL_CLK */ |
| 1038 | /* 4 IF_ATT_SEL */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1039 | |
| 1040 | #define FLD_GPIO1_ALT_IN_SEL 0x000000F0 |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1041 | /* 0 GPIO[1] <-- default */ |
| 1042 | /* 1 IR_RX */ |
| 1043 | /* 2 IR_TX */ |
| 1044 | /* 3 AUX_PLL_CLK */ |
| 1045 | /* 4 IF_ATT_SEL */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1046 | |
| 1047 | #define FLD_GPIO0_ALT_IN_SEL 0x0000000F |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1048 | /* 0 GPIO[0] <-- default */ |
| 1049 | /* 1 IR_RX */ |
| 1050 | /* 2 IR_TX */ |
| 1051 | /* 3 AUX_PLL_CLK */ |
| 1052 | /* 4 IF_ATT_SEL */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1053 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1054 | /* ***************************************************************************** */ |
| 1055 | #define TEST_BUS_CTL1 0x110040 /* Test bus control register #1 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1056 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1057 | /* ***************************************************************************** */ |
| 1058 | #define TEST_BUS_CTL2 0x110044 /* Test bus control register #2 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1059 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1060 | /* ***************************************************************************** */ |
| 1061 | #define CLK_DELAY 0x110048 /* Clock delay */ |
| 1062 | #define FLD_MOE_CLK_DIS 0x80000000 /* Disable MoE clock */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1063 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1064 | /* ***************************************************************************** */ |
| 1065 | #define PAD_CTRL 0x110068 /* Pad drive strength control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1066 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1067 | /* ***************************************************************************** */ |
| 1068 | #define MBIST_CTRL 0x110050 /* SRAM memory built-in self test control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1069 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1070 | /* ***************************************************************************** */ |
| 1071 | #define MBIST_STAT 0x110054 /* SRAM memory built-in self test status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1072 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1073 | /* ***************************************************************************** */ |
| 1074 | /* PLL registers */ |
| 1075 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1076 | #define PLL_A_INT_FRAC 0x110088 |
| 1077 | #define PLL_A_POST_STAT_BIST 0x11008C |
| 1078 | #define PLL_B_INT_FRAC 0x110090 |
| 1079 | #define PLL_B_POST_STAT_BIST 0x110094 |
| 1080 | #define PLL_C_INT_FRAC 0x110098 |
| 1081 | #define PLL_C_POST_STAT_BIST 0x11009C |
| 1082 | #define PLL_D_INT_FRAC 0x1100A0 |
| 1083 | #define PLL_D_POST_STAT_BIST 0x1100A4 |
| 1084 | |
| 1085 | #define CLK_RST 0x11002C |
| 1086 | #define FLD_VID_I_CLK_NOE 0x00001000 |
| 1087 | #define FLD_VID_J_CLK_NOE 0x00002000 |
| 1088 | #define FLD_USE_ALT_PLL_REF 0x00004000 |
| 1089 | |
| 1090 | #define VID_CH_MODE_SEL 0x110078 |
| 1091 | #define VID_CH_CLK_SEL 0x11007C |
| 1092 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1093 | /* ***************************************************************************** */ |
| 1094 | #define VBI_A_DMA 0x130008 /* VBI A DMA data port */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1095 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1096 | /* ***************************************************************************** */ |
| 1097 | #define VID_A_VIP_CTL 0x130080 /* Video A VIP format control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1098 | #define FLD_VIP_MODE 0x00000001 |
| 1099 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1100 | /* ***************************************************************************** */ |
| 1101 | #define VID_A_PIXEL_FRMT 0x130084 /* Video A pixel format */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1102 | #define FLD_VID_A_GAMMA_DIS 0x00000008 |
| 1103 | #define FLD_VID_A_FORMAT 0x00000007 |
| 1104 | #define FLD_VID_A_GAMMA_FACTOR 0x00000010 |
| 1105 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1106 | /* ***************************************************************************** */ |
| 1107 | #define VID_A_VBI_CTL 0x130088 /* Video A VBI miscellaneous control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1108 | #define FLD_VID_A_VIP_EXT 0x00000003 |
| 1109 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1110 | /* ***************************************************************************** */ |
| 1111 | #define VID_B_DMA 0x130100 /* Video B DMA data port */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1112 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1113 | /* ***************************************************************************** */ |
| 1114 | #define VBI_B_DMA 0x130108 /* VBI B DMA data port */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1115 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1116 | /* ***************************************************************************** */ |
| 1117 | #define VID_B_SRC_SEL 0x130144 /* Video B source select */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1118 | #define FLD_VID_B_SRC_SEL 0x00000000 |
| 1119 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1120 | /* ***************************************************************************** */ |
| 1121 | #define VID_B_LNGTH 0x130150 /* Video B line length */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1122 | #define FLD_VID_B_LN_LNGTH 0x00000FFF |
| 1123 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1124 | /* ***************************************************************************** */ |
| 1125 | #define VID_B_VIP_CTL 0x130180 /* Video B VIP format control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1126 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1127 | /* ***************************************************************************** */ |
| 1128 | #define VID_B_PIXEL_FRMT 0x130184 /* Video B pixel format */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1129 | #define FLD_VID_B_GAMMA_DIS 0x00000008 |
| 1130 | #define FLD_VID_B_FORMAT 0x00000007 |
| 1131 | #define FLD_VID_B_GAMMA_FACTOR 0x00000010 |
| 1132 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1133 | /* ***************************************************************************** */ |
| 1134 | #define VID_C_DMA 0x130200 /* Video C DMA data port */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1135 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1136 | /* ***************************************************************************** */ |
| 1137 | #define VID_C_LNGTH 0x130250 /* Video C line length */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1138 | #define FLD_VID_C_LN_LNGTH 0x00000FFF |
| 1139 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1140 | /* ***************************************************************************** */ |
| 1141 | /* Video Destination Channels */ |
| 1142 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1143 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1144 | #define VID_DST_A_GPCNT 0x130020 /* Video A general purpose counter */ |
| 1145 | #define VID_DST_B_GPCNT 0x130120 /* Video B general purpose counter */ |
| 1146 | #define VID_DST_C_GPCNT 0x130220 /* Video C general purpose counter */ |
| 1147 | #define VID_DST_D_GPCNT 0x130320 /* Video D general purpose counter */ |
| 1148 | #define VID_DST_E_GPCNT 0x130420 /* Video E general purpose counter */ |
| 1149 | #define VID_DST_F_GPCNT 0x130520 /* Video F general purpose counter */ |
| 1150 | #define VID_DST_G_GPCNT 0x130620 /* Video G general purpose counter */ |
| 1151 | #define VID_DST_H_GPCNT 0x130720 /* Video H general purpose counter */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1152 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1153 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1154 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1155 | #define VID_DST_A_GPCNT_CTL 0x130030 /* Video A general purpose control */ |
| 1156 | #define VID_DST_B_GPCNT_CTL 0x130130 /* Video B general purpose control */ |
| 1157 | #define VID_DST_C_GPCNT_CTL 0x130230 /* Video C general purpose control */ |
| 1158 | #define VID_DST_D_GPCNT_CTL 0x130330 /* Video D general purpose control */ |
| 1159 | #define VID_DST_E_GPCNT_CTL 0x130430 /* Video E general purpose control */ |
| 1160 | #define VID_DST_F_GPCNT_CTL 0x130530 /* Video F general purpose control */ |
| 1161 | #define VID_DST_G_GPCNT_CTL 0x130630 /* Video G general purpose control */ |
| 1162 | #define VID_DST_H_GPCNT_CTL 0x130730 /* Video H general purpose control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1163 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1164 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1165 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1166 | #define VID_DST_A_DMA_CTL 0x130040 /* Video A DMA control */ |
| 1167 | #define VID_DST_B_DMA_CTL 0x130140 /* Video B DMA control */ |
| 1168 | #define VID_DST_C_DMA_CTL 0x130240 /* Video C DMA control */ |
| 1169 | #define VID_DST_D_DMA_CTL 0x130340 /* Video D DMA control */ |
| 1170 | #define VID_DST_E_DMA_CTL 0x130440 /* Video E DMA control */ |
| 1171 | #define VID_DST_F_DMA_CTL 0x130540 /* Video F DMA control */ |
| 1172 | #define VID_DST_G_DMA_CTL 0x130640 /* Video G DMA control */ |
| 1173 | #define VID_DST_H_DMA_CTL 0x130740 /* Video H DMA control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1174 | |
| 1175 | #define FLD_VID_RISC_EN 0x00000010 |
| 1176 | #define FLD_VID_FIFO_EN 0x00000001 |
| 1177 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1178 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1179 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1180 | #define VID_DST_A_VIP_CTL 0x130080 /* Video A VIP control */ |
| 1181 | #define VID_DST_B_VIP_CTL 0x130180 /* Video B VIP control */ |
| 1182 | #define VID_DST_C_VIP_CTL 0x130280 /* Video C VIP control */ |
| 1183 | #define VID_DST_D_VIP_CTL 0x130380 /* Video D VIP control */ |
| 1184 | #define VID_DST_E_VIP_CTL 0x130480 /* Video E VIP control */ |
| 1185 | #define VID_DST_F_VIP_CTL 0x130580 /* Video F VIP control */ |
| 1186 | #define VID_DST_G_VIP_CTL 0x130680 /* Video G VIP control */ |
| 1187 | #define VID_DST_H_VIP_CTL 0x130780 /* Video H VIP control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1188 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1189 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1190 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1191 | #define VID_DST_A_PIX_FRMT 0x130084 /* Video A Pixel format */ |
| 1192 | #define VID_DST_B_PIX_FRMT 0x130184 /* Video B Pixel format */ |
| 1193 | #define VID_DST_C_PIX_FRMT 0x130284 /* Video C Pixel format */ |
| 1194 | #define VID_DST_D_PIX_FRMT 0x130384 /* Video D Pixel format */ |
| 1195 | #define VID_DST_E_PIX_FRMT 0x130484 /* Video E Pixel format */ |
| 1196 | #define VID_DST_F_PIX_FRMT 0x130584 /* Video F Pixel format */ |
| 1197 | #define VID_DST_G_PIX_FRMT 0x130684 /* Video G Pixel format */ |
| 1198 | #define VID_DST_H_PIX_FRMT 0x130784 /* Video H Pixel format */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1199 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1200 | /* ***************************************************************************** */ |
| 1201 | /* Video Source Channels */ |
| 1202 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1203 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1204 | #define VID_SRC_A_GPCNT_CTL 0x130804 /* Video A general purpose control */ |
| 1205 | #define VID_SRC_B_GPCNT_CTL 0x130904 /* Video B general purpose control */ |
| 1206 | #define VID_SRC_C_GPCNT_CTL 0x130A04 /* Video C general purpose control */ |
| 1207 | #define VID_SRC_D_GPCNT_CTL 0x130B04 /* Video D general purpose control */ |
| 1208 | #define VID_SRC_E_GPCNT_CTL 0x130C04 /* Video E general purpose control */ |
| 1209 | #define VID_SRC_F_GPCNT_CTL 0x130D04 /* Video F general purpose control */ |
| 1210 | #define VID_SRC_I_GPCNT_CTL 0x130E04 /* Video I general purpose control */ |
| 1211 | #define VID_SRC_J_GPCNT_CTL 0x130F04 /* Video J general purpose control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1212 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1213 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1214 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1215 | #define VID_SRC_A_GPCNT 0x130808 /* Video A general purpose counter */ |
| 1216 | #define VID_SRC_B_GPCNT 0x130908 /* Video B general purpose counter */ |
| 1217 | #define VID_SRC_C_GPCNT 0x130A08 /* Video C general purpose counter */ |
| 1218 | #define VID_SRC_D_GPCNT 0x130B08 /* Video D general purpose counter */ |
| 1219 | #define VID_SRC_E_GPCNT 0x130C08 /* Video E general purpose counter */ |
| 1220 | #define VID_SRC_F_GPCNT 0x130D08 /* Video F general purpose counter */ |
| 1221 | #define VID_SRC_I_GPCNT 0x130E08 /* Video I general purpose counter */ |
| 1222 | #define VID_SRC_J_GPCNT 0x130F08 /* Video J general purpose counter */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1223 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1224 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1225 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1226 | #define VID_SRC_A_DMA_CTL 0x13080C /* Video A DMA control */ |
| 1227 | #define VID_SRC_B_DMA_CTL 0x13090C /* Video B DMA control */ |
| 1228 | #define VID_SRC_C_DMA_CTL 0x130A0C /* Video C DMA control */ |
| 1229 | #define VID_SRC_D_DMA_CTL 0x130B0C /* Video D DMA control */ |
| 1230 | #define VID_SRC_E_DMA_CTL 0x130C0C /* Video E DMA control */ |
| 1231 | #define VID_SRC_F_DMA_CTL 0x130D0C /* Video F DMA control */ |
| 1232 | #define VID_SRC_I_DMA_CTL 0x130E0C /* Video I DMA control */ |
| 1233 | #define VID_SRC_J_DMA_CTL 0x130F0C /* Video J DMA control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1234 | |
| 1235 | #define FLD_APB_RISC_EN 0x00000010 |
| 1236 | #define FLD_APB_FIFO_EN 0x00000001 |
| 1237 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1238 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1239 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1240 | #define VID_SRC_A_FMT_CTL 0x130810 /* Video A format control */ |
| 1241 | #define VID_SRC_B_FMT_CTL 0x130910 /* Video B format control */ |
| 1242 | #define VID_SRC_C_FMT_CTL 0x130A10 /* Video C format control */ |
| 1243 | #define VID_SRC_D_FMT_CTL 0x130B10 /* Video D format control */ |
| 1244 | #define VID_SRC_E_FMT_CTL 0x130C10 /* Video E format control */ |
| 1245 | #define VID_SRC_F_FMT_CTL 0x130D10 /* Video F format control */ |
| 1246 | #define VID_SRC_I_FMT_CTL 0x130E10 /* Video I format control */ |
| 1247 | #define VID_SRC_J_FMT_CTL 0x130F10 /* Video J format control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1248 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1249 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1250 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1251 | #define VID_SRC_A_ACTIVE_CTL1 0x130814 /* Video A active control 1 */ |
| 1252 | #define VID_SRC_B_ACTIVE_CTL1 0x130914 /* Video B active control 1 */ |
| 1253 | #define VID_SRC_C_ACTIVE_CTL1 0x130A14 /* Video C active control 1 */ |
| 1254 | #define VID_SRC_D_ACTIVE_CTL1 0x130B14 /* Video D active control 1 */ |
| 1255 | #define VID_SRC_E_ACTIVE_CTL1 0x130C14 /* Video E active control 1 */ |
| 1256 | #define VID_SRC_F_ACTIVE_CTL1 0x130D14 /* Video F active control 1 */ |
| 1257 | #define VID_SRC_I_ACTIVE_CTL1 0x130E14 /* Video I active control 1 */ |
| 1258 | #define VID_SRC_J_ACTIVE_CTL1 0x130F14 /* Video J active control 1 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1259 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1260 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1261 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1262 | #define VID_SRC_A_ACTIVE_CTL2 0x130818 /* Video A active control 2 */ |
| 1263 | #define VID_SRC_B_ACTIVE_CTL2 0x130918 /* Video B active control 2 */ |
| 1264 | #define VID_SRC_C_ACTIVE_CTL2 0x130A18 /* Video C active control 2 */ |
| 1265 | #define VID_SRC_D_ACTIVE_CTL2 0x130B18 /* Video D active control 2 */ |
| 1266 | #define VID_SRC_E_ACTIVE_CTL2 0x130C18 /* Video E active control 2 */ |
| 1267 | #define VID_SRC_F_ACTIVE_CTL2 0x130D18 /* Video F active control 2 */ |
| 1268 | #define VID_SRC_I_ACTIVE_CTL2 0x130E18 /* Video I active control 2 */ |
| 1269 | #define VID_SRC_J_ACTIVE_CTL2 0x130F18 /* Video J active control 2 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1270 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1271 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1272 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1273 | #define VID_SRC_A_CDT_SZ 0x13081C /* Video A CDT size */ |
| 1274 | #define VID_SRC_B_CDT_SZ 0x13091C /* Video B CDT size */ |
| 1275 | #define VID_SRC_C_CDT_SZ 0x130A1C /* Video C CDT size */ |
| 1276 | #define VID_SRC_D_CDT_SZ 0x130B1C /* Video D CDT size */ |
| 1277 | #define VID_SRC_E_CDT_SZ 0x130C1C /* Video E CDT size */ |
| 1278 | #define VID_SRC_F_CDT_SZ 0x130D1C /* Video F CDT size */ |
| 1279 | #define VID_SRC_I_CDT_SZ 0x130E1C /* Video I CDT size */ |
| 1280 | #define VID_SRC_J_CDT_SZ 0x130F1C /* Video J CDT size */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1281 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1282 | /* ***************************************************************************** */ |
| 1283 | /* Audio I/F */ |
| 1284 | /* ***************************************************************************** */ |
| 1285 | #define AUD_DST_A_DMA 0x140000 /* Audio Int A DMA data port */ |
| 1286 | #define AUD_SRC_A_DMA 0x140008 /* Audio Int A DMA data port */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1287 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1288 | #define AUD_A_GPCNT 0x140010 /* Audio Int A gp counter */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1289 | #define FLD_AUD_A_GP_CNT 0x0000FFFF |
| 1290 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1291 | #define AUD_A_GPCNT_CTL 0x140014 /* Audio Int A gp control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1292 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1293 | #define AUD_A_LNGTH 0x140018 /* Audio Int A line length */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1294 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1295 | #define AUD_A_CFG 0x14001C /* Audio Int A configuration */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1296 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1297 | /* ***************************************************************************** */ |
| 1298 | #define AUD_DST_B_DMA 0x140100 /* Audio Int B DMA data port */ |
| 1299 | #define AUD_SRC_B_DMA 0x140108 /* Audio Int B DMA data port */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1300 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1301 | #define AUD_B_GPCNT 0x140110 /* Audio Int B gp counter */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1302 | #define FLD_AUD_B_GP_CNT 0x0000FFFF |
| 1303 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1304 | #define AUD_B_GPCNT_CTL 0x140114 /* Audio Int B gp control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1305 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1306 | #define AUD_B_LNGTH 0x140118 /* Audio Int B line length */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1307 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1308 | #define AUD_B_CFG 0x14011C /* Audio Int B configuration */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1309 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1310 | /* ***************************************************************************** */ |
| 1311 | #define AUD_DST_C_DMA 0x140200 /* Audio Int C DMA data port */ |
| 1312 | #define AUD_SRC_C_DMA 0x140208 /* Audio Int C DMA data port */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1313 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1314 | #define AUD_C_GPCNT 0x140210 /* Audio Int C gp counter */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1315 | #define FLD_AUD_C_GP_CNT 0x0000FFFF |
| 1316 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1317 | #define AUD_C_GPCNT_CTL 0x140214 /* Audio Int C gp control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1318 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1319 | #define AUD_C_LNGTH 0x140218 /* Audio Int C line length */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1320 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1321 | #define AUD_C_CFG 0x14021C /* Audio Int C configuration */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1322 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1323 | /* ***************************************************************************** */ |
| 1324 | #define AUD_DST_D_DMA 0x140300 /* Audio Int D DMA data port */ |
| 1325 | #define AUD_SRC_D_DMA 0x140308 /* Audio Int D DMA data port */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1326 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1327 | #define AUD_D_GPCNT 0x140310 /* Audio Int D gp counter */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1328 | #define FLD_AUD_D_GP_CNT 0x0000FFFF |
| 1329 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1330 | #define AUD_D_GPCNT_CTL 0x140314 /* Audio Int D gp control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1331 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1332 | #define AUD_D_LNGTH 0x140318 /* Audio Int D line length */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1333 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1334 | #define AUD_D_CFG 0x14031C /* Audio Int D configuration */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1335 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1336 | /* ***************************************************************************** */ |
| 1337 | #define AUD_SRC_E_DMA 0x140400 /* Audio Int E DMA data port */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1338 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1339 | #define AUD_E_GPCNT 0x140410 /* Audio Int E gp counter */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1340 | #define FLD_AUD_E_GP_CNT 0x0000FFFF |
| 1341 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1342 | #define AUD_E_GPCNT_CTL 0x140414 /* Audio Int E gp control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1343 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1344 | #define AUD_E_CFG 0x14041C /* Audio Int E configuration */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1345 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1346 | /* ***************************************************************************** */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1347 | |
| 1348 | #define FLD_AUD_DST_LN_LNGTH 0x00000FFF |
| 1349 | |
| 1350 | #define FLD_AUD_DST_PK_MODE 0x00004000 |
| 1351 | |
| 1352 | #define FLD_AUD_CLK_ENABLE 0x00000200 |
| 1353 | |
| 1354 | #define FLD_AUD_MASTER_MODE 0x00000002 |
| 1355 | |
| 1356 | #define FLD_AUD_SONY_MODE 0x00000001 |
| 1357 | |
| 1358 | #define FLD_AUD_CLK_SELECT_PLL_D 0x00001800 |
| 1359 | |
| 1360 | #define FLD_AUD_DST_ENABLE 0x00020000 |
| 1361 | |
| 1362 | #define FLD_AUD_SRC_ENABLE 0x00010000 |
| 1363 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1364 | /* ***************************************************************************** */ |
| 1365 | #define AUD_INT_DMA_CTL 0x140500 /* Audio Int DMA control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1366 | |
| 1367 | #define FLD_AUD_SRC_E_RISC_EN 0x00008000 |
| 1368 | #define FLD_AUD_SRC_C_RISC_EN 0x00004000 |
| 1369 | #define FLD_AUD_SRC_B_RISC_EN 0x00002000 |
| 1370 | #define FLD_AUD_SRC_A_RISC_EN 0x00001000 |
| 1371 | |
| 1372 | #define FLD_AUD_DST_D_RISC_EN 0x00000800 |
| 1373 | #define FLD_AUD_DST_C_RISC_EN 0x00000400 |
| 1374 | #define FLD_AUD_DST_B_RISC_EN 0x00000200 |
| 1375 | #define FLD_AUD_DST_A_RISC_EN 0x00000100 |
| 1376 | |
| 1377 | #define FLD_AUD_SRC_E_FIFO_EN 0x00000080 |
| 1378 | #define FLD_AUD_SRC_C_FIFO_EN 0x00000040 |
| 1379 | #define FLD_AUD_SRC_B_FIFO_EN 0x00000020 |
| 1380 | #define FLD_AUD_SRC_A_FIFO_EN 0x00000010 |
| 1381 | |
| 1382 | #define FLD_AUD_DST_D_FIFO_EN 0x00000008 |
| 1383 | #define FLD_AUD_DST_C_FIFO_EN 0x00000004 |
| 1384 | #define FLD_AUD_DST_B_FIFO_EN 0x00000002 |
| 1385 | #define FLD_AUD_DST_A_FIFO_EN 0x00000001 |
| 1386 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1387 | /* ***************************************************************************** */ |
| 1388 | /* */ |
| 1389 | /* Mobilygen Interface Registers */ |
| 1390 | /* */ |
| 1391 | /* ***************************************************************************** */ |
| 1392 | /* Mobilygen Interface A */ |
| 1393 | /* ***************************************************************************** */ |
| 1394 | #define MB_IF_A_DMA 0x150000 /* MBIF A DMA data port */ |
| 1395 | #define MB_IF_A_GPCN 0x150008 /* MBIF A GP counter */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1396 | #define MB_IF_A_GPCN_CTRL 0x15000C |
| 1397 | #define MB_IF_A_DMA_CTRL 0x150010 |
| 1398 | #define MB_IF_A_LENGTH 0x150014 |
| 1399 | #define MB_IF_A_HDMA_XFER_SZ 0x150018 |
| 1400 | #define MB_IF_A_HCMD 0x15001C |
| 1401 | #define MB_IF_A_HCONFIG 0x150020 |
| 1402 | #define MB_IF_A_DATA_STRUCT_0 0x150024 |
| 1403 | #define MB_IF_A_DATA_STRUCT_1 0x150028 |
| 1404 | #define MB_IF_A_DATA_STRUCT_2 0x15002C |
| 1405 | #define MB_IF_A_DATA_STRUCT_3 0x150030 |
| 1406 | #define MB_IF_A_DATA_STRUCT_4 0x150034 |
| 1407 | #define MB_IF_A_DATA_STRUCT_5 0x150038 |
| 1408 | #define MB_IF_A_DATA_STRUCT_6 0x15003C |
| 1409 | #define MB_IF_A_DATA_STRUCT_7 0x150040 |
| 1410 | #define MB_IF_A_DATA_STRUCT_8 0x150044 |
| 1411 | #define MB_IF_A_DATA_STRUCT_9 0x150048 |
| 1412 | #define MB_IF_A_DATA_STRUCT_A 0x15004C |
| 1413 | #define MB_IF_A_DATA_STRUCT_B 0x150050 |
| 1414 | #define MB_IF_A_DATA_STRUCT_C 0x150054 |
| 1415 | #define MB_IF_A_DATA_STRUCT_D 0x150058 |
| 1416 | #define MB_IF_A_DATA_STRUCT_E 0x15005C |
| 1417 | #define MB_IF_A_DATA_STRUCT_F 0x150060 |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1418 | /* ***************************************************************************** */ |
| 1419 | /* Mobilygen Interface B */ |
| 1420 | /* ***************************************************************************** */ |
| 1421 | #define MB_IF_B_DMA 0x160000 /* MBIF A DMA data port */ |
| 1422 | #define MB_IF_B_GPCN 0x160008 /* MBIF A GP counter */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1423 | #define MB_IF_B_GPCN_CTRL 0x16000C |
| 1424 | #define MB_IF_B_DMA_CTRL 0x160010 |
| 1425 | #define MB_IF_B_LENGTH 0x160014 |
| 1426 | #define MB_IF_B_HDMA_XFER_SZ 0x160018 |
| 1427 | #define MB_IF_B_HCMD 0x16001C |
| 1428 | #define MB_IF_B_HCONFIG 0x160020 |
| 1429 | #define MB_IF_B_DATA_STRUCT_0 0x160024 |
| 1430 | #define MB_IF_B_DATA_STRUCT_1 0x160028 |
| 1431 | #define MB_IF_B_DATA_STRUCT_2 0x16002C |
| 1432 | #define MB_IF_B_DATA_STRUCT_3 0x160030 |
| 1433 | #define MB_IF_B_DATA_STRUCT_4 0x160034 |
| 1434 | #define MB_IF_B_DATA_STRUCT_5 0x160038 |
| 1435 | #define MB_IF_B_DATA_STRUCT_6 0x16003C |
| 1436 | #define MB_IF_B_DATA_STRUCT_7 0x160040 |
| 1437 | #define MB_IF_B_DATA_STRUCT_8 0x160044 |
| 1438 | #define MB_IF_B_DATA_STRUCT_9 0x160048 |
| 1439 | #define MB_IF_B_DATA_STRUCT_A 0x16004C |
| 1440 | #define MB_IF_B_DATA_STRUCT_B 0x160050 |
| 1441 | #define MB_IF_B_DATA_STRUCT_C 0x160054 |
| 1442 | #define MB_IF_B_DATA_STRUCT_D 0x160058 |
| 1443 | #define MB_IF_B_DATA_STRUCT_E 0x16005C |
| 1444 | #define MB_IF_B_DATA_STRUCT_F 0x160060 |
| 1445 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1446 | /* MB_DMA_CTRL */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1447 | #define FLD_MB_IF_RISC_EN 0x00000010 |
| 1448 | #define FLD_MB_IF_FIFO_EN 0x00000001 |
| 1449 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1450 | /* MB_LENGTH */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1451 | #define FLD_MB_IF_LN_LNGTH 0x00000FFF |
| 1452 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1453 | /* MB_HCMD register */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1454 | #define FLD_MB_HCMD_H_GO 0x80000000 |
| 1455 | #define FLD_MB_HCMD_H_BUSY 0x40000000 |
| 1456 | #define FLD_MB_HCMD_H_DMA_HOLD 0x10000000 |
| 1457 | #define FLD_MB_HCMD_H_DMA_BUSY 0x08000000 |
| 1458 | #define FLD_MB_HCMD_H_DMA_TYPE 0x04000000 |
| 1459 | #define FLD_MB_HCMD_H_DMA_XACT 0x02000000 |
| 1460 | #define FLD_MB_HCMD_H_RW_N 0x01000000 |
| 1461 | #define FLD_MB_HCMD_H_ADDR 0x00FF0000 |
| 1462 | #define FLD_MB_HCMD_H_DATA 0x0000FFFF |
| 1463 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1464 | /* ***************************************************************************** */ |
| 1465 | /* I2C #1 */ |
| 1466 | /* ***************************************************************************** */ |
| 1467 | #define I2C1_ADDR 0x180000 /* I2C #1 address */ |
| 1468 | #define FLD_I2C_DADDR 0xfe000000 /* RW [31:25] I2C Device Address */ |
| 1469 | /* RO [24] reserved */ |
| 1470 | /* ***************************************************************************** */ |
| 1471 | #define FLD_I2C_SADDR 0x00FFFFFF /* RW [23:0] I2C Sub-address */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1472 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1473 | /* ***************************************************************************** */ |
| 1474 | #define I2C1_WDATA 0x180004 /* I2C #1 write data */ |
| 1475 | #define FLD_I2C_WDATA 0xFFFFFFFF /* RW [31:0] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1476 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1477 | /* ***************************************************************************** */ |
| 1478 | #define I2C1_CTRL 0x180008 /* I2C #1 control */ |
| 1479 | #define FLD_I2C_PERIOD 0xFF000000 /* RW [31:24] */ |
| 1480 | #define FLD_I2C_SCL_IN 0x00200000 /* RW [21] */ |
| 1481 | #define FLD_I2C_SDA_IN 0x00100000 /* RW [20] */ |
| 1482 | /* RO [19:18] reserved */ |
| 1483 | #define FLD_I2C_SCL_OUT 0x00020000 /* RW [17] */ |
| 1484 | #define FLD_I2C_SDA_OUT 0x00010000 /* RW [16] */ |
| 1485 | /* RO [15] reserved */ |
| 1486 | #define FLD_I2C_DATA_LEN 0x00007000 /* RW [14:12] */ |
| 1487 | #define FLD_I2C_SADDR_INC 0x00000800 /* RW [11] */ |
| 1488 | /* RO [10:9] reserved */ |
| 1489 | #define FLD_I2C_SADDR_LEN 0x00000300 /* RW [9:8] */ |
| 1490 | /* RO [7:6] reserved */ |
| 1491 | #define FLD_I2C_SOFT 0x00000020 /* RW [5] */ |
| 1492 | #define FLD_I2C_NOSTOP 0x00000010 /* RW [4] */ |
| 1493 | #define FLD_I2C_EXTEND 0x00000008 /* RW [3] */ |
| 1494 | #define FLD_I2C_SYNC 0x00000004 /* RW [2] */ |
| 1495 | #define FLD_I2C_READ_SA 0x00000002 /* RW [1] */ |
| 1496 | #define FLD_I2C_READ_WRN 0x00000001 /* RW [0] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1497 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1498 | /* ***************************************************************************** */ |
| 1499 | #define I2C1_RDATA 0x18000C /* I2C #1 read data */ |
| 1500 | #define FLD_I2C_RDATA 0xFFFFFFFF /* RO [31:0] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1501 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1502 | /* ***************************************************************************** */ |
| 1503 | #define I2C1_STAT 0x180010 /* I2C #1 status */ |
| 1504 | #define FLD_I2C_XFER_IN_PROG 0x00000002 /* RO [1] */ |
| 1505 | #define FLD_I2C_RACK 0x00000001 /* RO [0] */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1506 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1507 | /* ***************************************************************************** */ |
| 1508 | /* I2C #2 */ |
| 1509 | /* ***************************************************************************** */ |
| 1510 | #define I2C2_ADDR 0x190000 /* I2C #2 address */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1511 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1512 | /* ***************************************************************************** */ |
| 1513 | #define I2C2_WDATA 0x190004 /* I2C #2 write data */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1514 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1515 | /* ***************************************************************************** */ |
| 1516 | #define I2C2_CTRL 0x190008 /* I2C #2 control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1517 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1518 | /* ***************************************************************************** */ |
| 1519 | #define I2C2_RDATA 0x19000C /* I2C #2 read data */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1520 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1521 | /* ***************************************************************************** */ |
| 1522 | #define I2C2_STAT 0x190010 /* I2C #2 status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1523 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1524 | /* ***************************************************************************** */ |
| 1525 | /* I2C #3 */ |
| 1526 | /* ***************************************************************************** */ |
| 1527 | #define I2C3_ADDR 0x1A0000 /* I2C #3 address */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1528 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1529 | /* ***************************************************************************** */ |
| 1530 | #define I2C3_WDATA 0x1A0004 /* I2C #3 write data */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1531 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1532 | /* ***************************************************************************** */ |
| 1533 | #define I2C3_CTRL 0x1A0008 /* I2C #3 control */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1534 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1535 | /* ***************************************************************************** */ |
| 1536 | #define I2C3_RDATA 0x1A000C /* I2C #3 read data */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1537 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1538 | /* ***************************************************************************** */ |
| 1539 | #define I2C3_STAT 0x1A0010 /* I2C #3 status */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1540 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1541 | /* ***************************************************************************** */ |
| 1542 | /* UART */ |
| 1543 | /* ***************************************************************************** */ |
| 1544 | #define UART_CTL 0x1B0000 /* UART Control Register */ |
| 1545 | #define FLD_LOOP_BACK_EN (1 << 7) /* RW field - default 0 */ |
| 1546 | #define FLD_RX_TRG_SZ (3 << 2) /* RW field - default 0 */ |
| 1547 | #define FLD_RX_EN (1 << 1) /* RW field - default 0 */ |
| 1548 | #define FLD_TX_EN (1 << 0) /* RW field - default 0 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1549 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1550 | /* ***************************************************************************** */ |
| 1551 | #define UART_BRD 0x1B0004 /* UART Baud Rate Divisor */ |
| 1552 | #define FLD_BRD 0x0000FFFF /* RW field - default 0x197 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1553 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1554 | /* ***************************************************************************** */ |
| 1555 | #define UART_DBUF 0x1B0008 /* UART Tx/Rx Data BuFFer */ |
| 1556 | #define FLD_DB 0xFFFFFFFF /* RW field - default 0 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1557 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1558 | /* ***************************************************************************** */ |
| 1559 | #define UART_ISR 0x1B000C /* UART Interrupt Status */ |
| 1560 | #define FLD_RXD_TIMEOUT_EN (1 << 7) /* RW field - default 0 */ |
| 1561 | #define FLD_FRM_ERR_EN (1 << 6) /* RW field - default 0 */ |
| 1562 | #define FLD_RXD_RDY_EN (1 << 5) /* RW field - default 0 */ |
| 1563 | #define FLD_TXD_EMPTY_EN (1 << 4) /* RW field - default 0 */ |
| 1564 | #define FLD_RXD_OVERFLOW (1 << 3) /* RW field - default 0 */ |
| 1565 | #define FLD_FRM_ERR (1 << 2) /* RW field - default 0 */ |
| 1566 | #define FLD_RXD_RDY (1 << 1) /* RW field - default 0 */ |
| 1567 | #define FLD_TXD_EMPTY (1 << 0) /* RW field - default 0 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1568 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1569 | /* ***************************************************************************** */ |
| 1570 | #define UART_CNT 0x1B0010 /* UART Tx/Rx FIFO Byte Count */ |
| 1571 | #define FLD_TXD_CNT (0x1F << 8) /* RW field - default 0 */ |
| 1572 | #define FLD_RXD_CNT (0x1F << 0) /* RW field - default 0 */ |
Mauro Carvalho Chehab | 1a9fc85 | 2009-09-13 11:30:11 -0300 | [diff] [blame] | 1573 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1574 | /* ***************************************************************************** */ |
| 1575 | /* Motion Detection */ |
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame] | 1576 | #define MD_CH0_GRID_BLOCK_YCNT 0x170014 |
| 1577 | #define MD_CH1_GRID_BLOCK_YCNT 0x170094 |
| 1578 | #define MD_CH2_GRID_BLOCK_YCNT 0x170114 |
| 1579 | #define MD_CH3_GRID_BLOCK_YCNT 0x170194 |
| 1580 | #define MD_CH4_GRID_BLOCK_YCNT 0x170214 |
| 1581 | #define MD_CH5_GRID_BLOCK_YCNT 0x170294 |
| 1582 | #define MD_CH6_GRID_BLOCK_YCNT 0x170314 |
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 1583 | #define MD_CH7_GRID_BLOCK_YCNT 0x170394 |
| 1584 | |
| 1585 | #define PIXEL_FRMT_422 4 |
| 1586 | #define PIXEL_FRMT_411 5 |
| 1587 | #define PIXEL_FRMT_Y8 6 |
| 1588 | |
| 1589 | #define PIXEL_ENGINE_VIP1 0 |
| 1590 | #define PIXEL_ENGINE_VIP2 1 |
| 1591 | |
Mauro Carvalho Chehab | 1852a1b | 2010-07-04 15:21:40 -0300 | [diff] [blame] | 1592 | #endif /* Athena_REGISTERS */ |