Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 1 | /* |
| 2 | * SPU core / file system interface and HW structures |
| 3 | * |
| 4 | * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 |
| 5 | * |
| 6 | * Author: Arnd Bergmann <arndb@de.ibm.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2, or (at your option) |
| 11 | * any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21 | */ |
| 22 | |
| 23 | #ifndef _SPU_H |
| 24 | #define _SPU_H |
Arnd Bergmann | 88ced03 | 2005-12-16 22:43:46 +0100 | [diff] [blame] | 25 | #ifdef __KERNEL__ |
| 26 | |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 27 | #include <linux/workqueue.h> |
Jeremy Kerr | 1d64093 | 2006-06-19 20:33:19 +0200 | [diff] [blame] | 28 | #include <linux/sysdev.h> |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 29 | |
Arnd Bergmann | aeb0137 | 2006-01-04 20:31:32 +0100 | [diff] [blame] | 30 | #define LS_SIZE (256 * 1024) |
Mark Nutter | 5473af0 | 2005-11-15 15:53:49 -0500 | [diff] [blame] | 31 | #define LS_ADDR_MASK (LS_SIZE - 1) |
| 32 | |
| 33 | #define MFC_PUT_CMD 0x20 |
| 34 | #define MFC_PUTS_CMD 0x28 |
| 35 | #define MFC_PUTR_CMD 0x30 |
| 36 | #define MFC_PUTF_CMD 0x22 |
| 37 | #define MFC_PUTB_CMD 0x21 |
| 38 | #define MFC_PUTFS_CMD 0x2A |
| 39 | #define MFC_PUTBS_CMD 0x29 |
| 40 | #define MFC_PUTRF_CMD 0x32 |
| 41 | #define MFC_PUTRB_CMD 0x31 |
| 42 | #define MFC_PUTL_CMD 0x24 |
| 43 | #define MFC_PUTRL_CMD 0x34 |
| 44 | #define MFC_PUTLF_CMD 0x26 |
| 45 | #define MFC_PUTLB_CMD 0x25 |
| 46 | #define MFC_PUTRLF_CMD 0x36 |
| 47 | #define MFC_PUTRLB_CMD 0x35 |
| 48 | |
| 49 | #define MFC_GET_CMD 0x40 |
| 50 | #define MFC_GETS_CMD 0x48 |
| 51 | #define MFC_GETF_CMD 0x42 |
| 52 | #define MFC_GETB_CMD 0x41 |
| 53 | #define MFC_GETFS_CMD 0x4A |
| 54 | #define MFC_GETBS_CMD 0x49 |
| 55 | #define MFC_GETL_CMD 0x44 |
| 56 | #define MFC_GETLF_CMD 0x46 |
| 57 | #define MFC_GETLB_CMD 0x45 |
| 58 | |
| 59 | #define MFC_SDCRT_CMD 0x80 |
| 60 | #define MFC_SDCRTST_CMD 0x81 |
| 61 | #define MFC_SDCRZ_CMD 0x89 |
| 62 | #define MFC_SDCRS_CMD 0x8D |
| 63 | #define MFC_SDCRF_CMD 0x8F |
| 64 | |
| 65 | #define MFC_GETLLAR_CMD 0xD0 |
| 66 | #define MFC_PUTLLC_CMD 0xB4 |
| 67 | #define MFC_PUTLLUC_CMD 0xB0 |
| 68 | #define MFC_PUTQLLUC_CMD 0xB8 |
| 69 | #define MFC_SNDSIG_CMD 0xA0 |
| 70 | #define MFC_SNDSIGB_CMD 0xA1 |
| 71 | #define MFC_SNDSIGF_CMD 0xA2 |
| 72 | #define MFC_BARRIER_CMD 0xC0 |
| 73 | #define MFC_EIEIO_CMD 0xC8 |
| 74 | #define MFC_SYNC_CMD 0xCC |
| 75 | |
| 76 | #define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */ |
| 77 | #define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */ |
| 78 | #define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT) |
| 79 | #define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT) |
| 80 | #define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1) |
| 81 | #define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1) |
| 82 | #define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */ |
| 83 | #define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */ |
| 84 | |
| 85 | #define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F)) |
| 86 | |
| 87 | /* Events for Channels 0-2 */ |
| 88 | #define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001 |
| 89 | #define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002 |
| 90 | #define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008 |
| 91 | #define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010 |
| 92 | #define MFC_DECREMENTER_EVENT 0x00000020 |
| 93 | #define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040 |
| 94 | #define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080 |
| 95 | #define MFC_SIGNAL_2_EVENT 0x00000100 |
| 96 | #define MFC_SIGNAL_1_EVENT 0x00000200 |
| 97 | #define MFC_LLR_LOST_EVENT 0x00000400 |
| 98 | #define MFC_PRIV_ATTN_EVENT 0x00000800 |
| 99 | #define MFC_MULTI_SRC_EVENT 0x00001000 |
| 100 | |
| 101 | /* Flags indicating progress during context switch. */ |
Arnd Bergmann | 8837d92 | 2006-01-04 20:31:28 +0100 | [diff] [blame] | 102 | #define SPU_CONTEXT_SWITCH_PENDING 0UL |
| 103 | #define SPU_CONTEXT_SWITCH_ACTIVE 1UL |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 104 | |
Arnd Bergmann | 8b3d666 | 2005-11-15 15:53:52 -0500 | [diff] [blame] | 105 | struct spu_context; |
| 106 | struct spu_runqueue; |
Ishizaki Kou | c9868fe | 2007-02-02 16:45:33 +0900 | [diff] [blame] | 107 | struct device_node; |
Arnd Bergmann | 8b3d666 | 2005-11-15 15:53:52 -0500 | [diff] [blame] | 108 | |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 109 | struct spu { |
Jeremy Kerr | c61c27d | 2006-07-12 15:39:54 +1000 | [diff] [blame] | 110 | const char *name; |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 111 | unsigned long local_store_phys; |
| 112 | u8 *local_store; |
Mark Nutter | 6df10a8 | 2006-03-23 00:00:12 +0100 | [diff] [blame] | 113 | unsigned long problem_phys; |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 114 | struct spu_problem __iomem *problem; |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 115 | struct spu_priv2 __iomem *priv2; |
| 116 | struct list_head list; |
Arnd Bergmann | 8b3d666 | 2005-11-15 15:53:52 -0500 | [diff] [blame] | 117 | struct list_head sched_list; |
Christian Krafft | e570beb | 2006-10-24 18:31:23 +0200 | [diff] [blame] | 118 | struct list_head full_list; |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 119 | int number; |
Benjamin Herrenschmidt | 0ebfff1 | 2006-07-03 21:36:01 +1000 | [diff] [blame] | 120 | unsigned int irqs[3]; |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 121 | u32 node; |
Mark Nutter | 5473af0 | 2005-11-15 15:53:49 -0500 | [diff] [blame] | 122 | u64 flags; |
Arnd Bergmann | 8b3d666 | 2005-11-15 15:53:52 -0500 | [diff] [blame] | 123 | u64 dar; |
| 124 | u64 dsisr; |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 125 | size_t ls_size; |
| 126 | unsigned int slb_replace; |
| 127 | struct mm_struct *mm; |
Arnd Bergmann | 8b3d666 | 2005-11-15 15:53:52 -0500 | [diff] [blame] | 128 | struct spu_context *ctx; |
| 129 | struct spu_runqueue *rq; |
Arnd Bergmann | 2a911f0 | 2005-12-05 22:52:26 -0500 | [diff] [blame] | 130 | unsigned long long timestamp; |
Arnd Bergmann | 8b3d666 | 2005-11-15 15:53:52 -0500 | [diff] [blame] | 131 | pid_t pid; |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 132 | int class_0_pending; |
| 133 | spinlock_t register_lock; |
| 134 | |
Arnd Bergmann | 8b3d666 | 2005-11-15 15:53:52 -0500 | [diff] [blame] | 135 | void (* wbox_callback)(struct spu *spu); |
| 136 | void (* ibox_callback)(struct spu *spu); |
Arnd Bergmann | 5110459 | 2005-12-05 22:52:25 -0500 | [diff] [blame] | 137 | void (* stop_callback)(struct spu *spu); |
Arnd Bergmann | a33a7d7 | 2006-03-23 00:00:11 +0100 | [diff] [blame] | 138 | void (* mfc_callback)(struct spu *spu); |
Arnd Bergmann | 9add11d | 2006-10-04 17:26:14 +0200 | [diff] [blame] | 139 | void (* dma_callback)(struct spu *spu, int type); |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 140 | |
| 141 | char irq_c0[8]; |
| 142 | char irq_c1[8]; |
| 143 | char irq_c2[8]; |
Jeremy Kerr | 1d64093 | 2006-06-19 20:33:19 +0200 | [diff] [blame] | 144 | |
Ishizaki Kou | c9868fe | 2007-02-02 16:45:33 +0900 | [diff] [blame] | 145 | u64 spe_id; |
| 146 | |
Geoff Levand | e28b003 | 2006-11-23 00:46:49 +0100 | [diff] [blame] | 147 | void* pdata; /* platform private data */ |
Ishizaki Kou | c9868fe | 2007-02-02 16:45:33 +0900 | [diff] [blame] | 148 | |
| 149 | /* of based platforms only */ |
| 150 | struct device_node *devnode; |
| 151 | |
| 152 | /* native only */ |
| 153 | struct spu_priv1 __iomem *priv1; |
| 154 | |
| 155 | /* beat only */ |
| 156 | u64 shadow_int_mask_RW[3]; |
| 157 | |
Jeremy Kerr | 1d64093 | 2006-06-19 20:33:19 +0200 | [diff] [blame] | 158 | struct sys_device sysdev; |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 159 | }; |
| 160 | |
| 161 | struct spu *spu_alloc(void); |
Mark Nutter | a68cf98 | 2006-10-04 17:26:12 +0200 | [diff] [blame] | 162 | struct spu *spu_alloc_node(int node); |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 163 | void spu_free(struct spu *spu); |
Arnd Bergmann | 5110459 | 2005-12-05 22:52:25 -0500 | [diff] [blame] | 164 | int spu_irq_class_0_bottom(struct spu *spu); |
| 165 | int spu_irq_class_1_bottom(struct spu *spu); |
Arnd Bergmann | 2fb9d20 | 2006-01-05 14:05:29 +0000 | [diff] [blame] | 166 | void spu_irq_setaffinity(struct spu *spu, int cpu); |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 167 | |
Arnd Bergmann | 2dd1493 | 2006-03-23 00:00:09 +0100 | [diff] [blame] | 168 | /* system callbacks from the SPU */ |
| 169 | struct spu_syscall_block { |
| 170 | u64 nr_ret; |
| 171 | u64 parm[6]; |
| 172 | }; |
| 173 | extern long spu_sys_callback(struct spu_syscall_block *s); |
| 174 | |
| 175 | /* syscalls implemented in spufs */ |
Arnd Bergmann | f1fa16e | 2006-12-19 15:32:42 +0100 | [diff] [blame] | 176 | struct file; |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 177 | extern struct spufs_calls { |
| 178 | asmlinkage long (*create_thread)(const char __user *name, |
| 179 | unsigned int flags, mode_t mode); |
| 180 | asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc, |
| 181 | __u32 __user *ustatus); |
| 182 | struct module *owner; |
| 183 | } spufs_calls; |
| 184 | |
Dwayne Grant McConnell | bf1ab97 | 2006-11-23 00:46:37 +0100 | [diff] [blame] | 185 | /* coredump calls implemented in spufs */ |
| 186 | struct spu_coredump_calls { |
| 187 | asmlinkage int (*arch_notes_size)(void); |
| 188 | asmlinkage void (*arch_write_notes)(struct file *file); |
| 189 | struct module *owner; |
| 190 | }; |
| 191 | |
Arnd Bergmann | 9add11d | 2006-10-04 17:26:14 +0200 | [diff] [blame] | 192 | /* return status from spu_run, same as in libspe */ |
| 193 | #define SPE_EVENT_DMA_ALIGNMENT 0x0008 /*A DMA alignment error */ |
| 194 | #define SPE_EVENT_SPE_ERROR 0x0010 /*An illegal instruction error*/ |
| 195 | #define SPE_EVENT_SPE_DATA_SEGMENT 0x0020 /*A DMA segmentation error */ |
| 196 | #define SPE_EVENT_SPE_DATA_STORAGE 0x0040 /*A DMA storage error */ |
| 197 | #define SPE_EVENT_INVALID_DMA 0x0800 /* Invalid MFC DMA */ |
| 198 | |
| 199 | /* |
| 200 | * Flags for sys_spu_create. |
| 201 | */ |
| 202 | #define SPU_CREATE_EVENTS_ENABLED 0x0001 |
Arnd Bergmann | 6263203 | 2006-10-04 17:26:15 +0200 | [diff] [blame] | 203 | #define SPU_CREATE_GANG 0x0002 |
Mark Nutter | 5737edd | 2006-10-24 18:31:16 +0200 | [diff] [blame] | 204 | #define SPU_CREATE_NOSCHED 0x0004 |
| 205 | #define SPU_CREATE_ISOLATE 0x0008 |
Arnd Bergmann | 6263203 | 2006-10-04 17:26:15 +0200 | [diff] [blame] | 206 | |
Mark Nutter | 5737edd | 2006-10-24 18:31:16 +0200 | [diff] [blame] | 207 | #define SPU_CREATE_FLAG_ALL 0x000f /* mask of all valid flags */ |
Arnd Bergmann | 6263203 | 2006-10-04 17:26:15 +0200 | [diff] [blame] | 208 | |
Arnd Bergmann | 9add11d | 2006-10-04 17:26:14 +0200 | [diff] [blame] | 209 | |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 210 | #ifdef CONFIG_SPU_FS_MODULE |
| 211 | int register_spu_syscalls(struct spufs_calls *calls); |
| 212 | void unregister_spu_syscalls(struct spufs_calls *calls); |
| 213 | #else |
| 214 | static inline int register_spu_syscalls(struct spufs_calls *calls) |
| 215 | { |
| 216 | return 0; |
| 217 | } |
| 218 | static inline void unregister_spu_syscalls(struct spufs_calls *calls) |
| 219 | { |
| 220 | } |
| 221 | #endif /* MODULE */ |
| 222 | |
Dwayne Grant McConnell | bf1ab97 | 2006-11-23 00:46:37 +0100 | [diff] [blame] | 223 | int register_arch_coredump_calls(struct spu_coredump_calls *calls); |
| 224 | void unregister_arch_coredump_calls(struct spu_coredump_calls *calls); |
| 225 | |
Christian Krafft | e570beb | 2006-10-24 18:31:23 +0200 | [diff] [blame] | 226 | int spu_add_sysdev_attr(struct sysdev_attribute *attr); |
| 227 | void spu_remove_sysdev_attr(struct sysdev_attribute *attr); |
| 228 | |
| 229 | int spu_add_sysdev_attr_group(struct attribute_group *attrs); |
| 230 | void spu_remove_sysdev_attr_group(struct attribute_group *attrs); |
| 231 | |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 232 | |
| 233 | /* |
Arnd Bergmann | 8676727 | 2006-10-04 17:26:21 +0200 | [diff] [blame] | 234 | * Notifier blocks: |
| 235 | * |
| 236 | * oprofile can get notified when a context switch is performed |
| 237 | * on an spe. The notifer function that gets called is passed |
| 238 | * a pointer to the SPU structure as well as the object-id that |
| 239 | * identifies the binary running on that SPU now. |
| 240 | * |
| 241 | * For a context save, the object-id that is passed is zero, |
| 242 | * identifying that the kernel will run from that moment on. |
| 243 | * |
| 244 | * For a context restore, the object-id is the value written |
| 245 | * to object-id spufs file from user space and the notifer |
| 246 | * function can assume that spu->ctx is valid. |
| 247 | */ |
Arnd Bergmann | f1fa16e | 2006-12-19 15:32:42 +0100 | [diff] [blame] | 248 | struct notifier_block; |
Arnd Bergmann | 8676727 | 2006-10-04 17:26:21 +0200 | [diff] [blame] | 249 | int spu_switch_event_register(struct notifier_block * n); |
| 250 | int spu_switch_event_unregister(struct notifier_block * n); |
| 251 | |
| 252 | /* |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 253 | * This defines the Local Store, Problem Area and Privlege Area of an SPU. |
| 254 | */ |
| 255 | |
| 256 | union mfc_tag_size_class_cmd { |
| 257 | struct { |
| 258 | u16 mfc_size; |
| 259 | u16 mfc_tag; |
| 260 | u8 pad; |
| 261 | u8 mfc_rclassid; |
| 262 | u16 mfc_cmd; |
| 263 | } u; |
| 264 | struct { |
| 265 | u32 mfc_size_tag32; |
| 266 | u32 mfc_class_cmd32; |
| 267 | } by32; |
| 268 | u64 all64; |
| 269 | }; |
| 270 | |
| 271 | struct mfc_cq_sr { |
| 272 | u64 mfc_cq_data0_RW; |
| 273 | u64 mfc_cq_data1_RW; |
| 274 | u64 mfc_cq_data2_RW; |
| 275 | u64 mfc_cq_data3_RW; |
| 276 | }; |
| 277 | |
| 278 | struct spu_problem { |
| 279 | #define MS_SYNC_PENDING 1L |
| 280 | u64 spc_mssync_RW; /* 0x0000 */ |
| 281 | u8 pad_0x0008_0x3000[0x3000 - 0x0008]; |
| 282 | |
| 283 | /* DMA Area */ |
| 284 | u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */ |
| 285 | u32 mfc_lsa_W; /* 0x3004 */ |
| 286 | u64 mfc_ea_W; /* 0x3008 */ |
| 287 | union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */ |
| 288 | u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */ |
| 289 | u32 dma_qstatus_R; /* 0x3104 */ |
| 290 | u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */ |
| 291 | u32 dma_querytype_RW; /* 0x3204 */ |
| 292 | u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */ |
| 293 | u32 dma_querymask_RW; /* 0x321c */ |
| 294 | u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */ |
| 295 | u32 dma_tagstatus_R; /* 0x322c */ |
| 296 | #define DMA_TAGSTATUS_INTR_ANY 1u |
| 297 | #define DMA_TAGSTATUS_INTR_ALL 2u |
| 298 | u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */ |
| 299 | |
| 300 | /* SPU Control Area */ |
| 301 | u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */ |
| 302 | u32 pu_mb_R; /* 0x4004 */ |
| 303 | u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */ |
| 304 | u32 spu_mb_W; /* 0x400c */ |
| 305 | u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */ |
| 306 | u32 mb_stat_R; /* 0x4014 */ |
| 307 | u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */ |
| 308 | u32 spu_runcntl_RW; /* 0x401c */ |
| 309 | #define SPU_RUNCNTL_STOP 0L |
| 310 | #define SPU_RUNCNTL_RUNNABLE 1L |
Mark Nutter | 5737edd | 2006-10-24 18:31:16 +0200 | [diff] [blame] | 311 | #define SPU_RUNCNTL_ISOLATE 2L |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 312 | u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */ |
| 313 | u32 spu_status_R; /* 0x4024 */ |
| 314 | #define SPU_STOP_STATUS_SHIFT 16 |
| 315 | #define SPU_STATUS_STOPPED 0x0 |
| 316 | #define SPU_STATUS_RUNNING 0x1 |
| 317 | #define SPU_STATUS_STOPPED_BY_STOP 0x2 |
| 318 | #define SPU_STATUS_STOPPED_BY_HALT 0x4 |
| 319 | #define SPU_STATUS_WAITING_FOR_CHANNEL 0x8 |
| 320 | #define SPU_STATUS_SINGLE_STEP 0x10 |
| 321 | #define SPU_STATUS_INVALID_INSTR 0x20 |
| 322 | #define SPU_STATUS_INVALID_CH 0x40 |
| 323 | #define SPU_STATUS_ISOLATED_STATE 0x80 |
arnd@arndb.de | eb758ce | 2006-10-24 18:31:17 +0200 | [diff] [blame] | 324 | #define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200 |
| 325 | #define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400 |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 326 | u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */ |
| 327 | u32 spu_spe_R; /* 0x402c */ |
| 328 | u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */ |
| 329 | u32 spu_npc_RW; /* 0x4034 */ |
| 330 | u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */ |
| 331 | |
| 332 | /* Signal Notification Area */ |
| 333 | u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */ |
| 334 | u32 signal_notify1; /* 0x1400c */ |
| 335 | u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */ |
| 336 | u32 signal_notify2; /* 0x1c00c */ |
| 337 | } __attribute__ ((aligned(0x20000))); |
| 338 | |
| 339 | /* SPU Privilege 2 State Area */ |
| 340 | struct spu_priv2 { |
| 341 | /* MFC Registers */ |
| 342 | u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */ |
| 343 | |
| 344 | /* SLB Management Registers */ |
| 345 | u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */ |
| 346 | u64 slb_index_W; /* 0x1108 */ |
| 347 | #define SLB_INDEX_MASK 0x7L |
| 348 | u64 slb_esid_RW; /* 0x1110 */ |
| 349 | u64 slb_vsid_RW; /* 0x1118 */ |
| 350 | #define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11) |
| 351 | #define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11) |
| 352 | #define SLB_VSID_PROBLEM_STATE (0x1ull << 10) |
| 353 | #define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10) |
| 354 | #define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9) |
| 355 | #define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9) |
| 356 | #define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9) |
| 357 | #define SLB_VSID_4K_PAGE (0x0 << 8) |
| 358 | #define SLB_VSID_LARGE_PAGE (0x1ull << 8) |
| 359 | #define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8) |
| 360 | #define SLB_VSID_CLASS_MASK (0x1ull << 7) |
| 361 | #define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6) |
| 362 | u64 slb_invalidate_entry_W; /* 0x1120 */ |
| 363 | u64 slb_invalidate_all_W; /* 0x1128 */ |
| 364 | u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */ |
| 365 | |
| 366 | /* Context Save / Restore Area */ |
| 367 | struct mfc_cq_sr spuq[16]; /* 0x2000 */ |
| 368 | struct mfc_cq_sr puq[8]; /* 0x2200 */ |
| 369 | u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */ |
| 370 | |
| 371 | /* MFC Control */ |
| 372 | u64 mfc_control_RW; /* 0x3000 */ |
| 373 | #define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0) |
| 374 | #define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0) |
| 375 | #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0) |
| 376 | #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8) |
| 377 | #define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8) |
| 378 | #define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8) |
| 379 | #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8) |
| 380 | #define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14) |
| 381 | #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14) |
| 382 | #define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15) |
| 383 | #define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24) |
| 384 | #define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24) |
| 385 | #define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24) |
| 386 | #define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32) |
| 387 | #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32) |
| 388 | #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32) |
| 389 | #define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33) |
| 390 | #define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33) |
| 391 | #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33) |
| 392 | #define MFC_CNTL_DECREMENTER_HALTED (1ull << 35) |
| 393 | #define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40) |
| 394 | #define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40) |
| 395 | u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */ |
| 396 | |
| 397 | /* Interrupt Mailbox */ |
| 398 | u64 puint_mb_R; /* 0x4000 */ |
| 399 | u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */ |
| 400 | |
| 401 | /* SPU Control */ |
| 402 | u64 spu_privcntl_RW; /* 0x4040 */ |
| 403 | #define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0) |
| 404 | #define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0) |
| 405 | #define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0) |
| 406 | #define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1) |
| 407 | #define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1) |
| 408 | #define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1) |
| 409 | #define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2) |
| 410 | #define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2) |
| 411 | u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */ |
| 412 | u64 spu_lslr_RW; /* 0x4058 */ |
| 413 | u64 spu_chnlcntptr_RW; /* 0x4060 */ |
| 414 | u64 spu_chnlcnt_RW; /* 0x4068 */ |
| 415 | u64 spu_chnldata_RW; /* 0x4070 */ |
| 416 | u64 spu_cfg_RW; /* 0x4078 */ |
| 417 | u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */ |
| 418 | |
| 419 | /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */ |
| 420 | u64 spu_pm_trace_tag_status_RW; /* 0x5000 */ |
| 421 | u64 spu_tag_status_query_RW; /* 0x5008 */ |
| 422 | #define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32) |
| 423 | #define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull) |
| 424 | u64 spu_cmd_buf1_RW; /* 0x5010 */ |
| 425 | #define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32) |
| 426 | #define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull) |
| 427 | u64 spu_cmd_buf2_RW; /* 0x5018 */ |
| 428 | #define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32) |
| 429 | #define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16) |
| 430 | #define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full) |
| 431 | u64 spu_atomic_status_RW; /* 0x5020 */ |
| 432 | } __attribute__ ((aligned(0x20000))); |
| 433 | |
| 434 | /* SPU Privilege 1 State Area */ |
| 435 | struct spu_priv1 { |
| 436 | /* Control and Configuration Area */ |
| 437 | u64 mfc_sr1_RW; /* 0x000 */ |
| 438 | #define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull |
| 439 | #define MFC_STATE1_BUS_TLBIE_MASK 0x02ull |
| 440 | #define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull |
| 441 | #define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull |
| 442 | #define MFC_STATE1_RELOCATE_MASK 0x10ull |
| 443 | #define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull |
| 444 | u64 mfc_lpid_RW; /* 0x008 */ |
| 445 | u64 spu_idr_RW; /* 0x010 */ |
| 446 | u64 mfc_vr_RO; /* 0x018 */ |
| 447 | #define MFC_VERSION_BITS (0xffff << 16) |
| 448 | #define MFC_REVISION_BITS (0xffff) |
| 449 | #define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16) |
| 450 | #define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS) |
| 451 | u64 spu_vr_RO; /* 0x020 */ |
| 452 | #define SPU_VERSION_BITS (0xffff << 16) |
| 453 | #define SPU_REVISION_BITS (0xffff) |
| 454 | #define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16 |
| 455 | #define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS) |
| 456 | u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */ |
| 457 | |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 458 | /* Interrupt Area */ |
Arnd Bergmann | f0831ac | 2006-01-04 20:31:30 +0100 | [diff] [blame] | 459 | u64 int_mask_RW[3]; /* 0x100 */ |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 460 | #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L |
| 461 | #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L |
| 462 | #define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L |
| 463 | #define CLASS0_ENABLE_MFC_FIR_INTR 0x8L |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 464 | #define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L |
| 465 | #define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L |
| 466 | #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L |
| 467 | #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 468 | #define CLASS2_ENABLE_MAILBOX_INTR 0x1L |
| 469 | #define CLASS2_ENABLE_SPU_STOP_INTR 0x2L |
| 470 | #define CLASS2_ENABLE_SPU_HALT_INTR 0x4L |
| 471 | #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L |
| 472 | u8 pad_0x118_0x140[0x28]; /* 0x118 */ |
Arnd Bergmann | f0831ac | 2006-01-04 20:31:30 +0100 | [diff] [blame] | 473 | u64 int_stat_RW[3]; /* 0x140 */ |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 474 | u8 pad_0x158_0x180[0x28]; /* 0x158 */ |
| 475 | u64 int_route_RW; /* 0x180 */ |
| 476 | |
| 477 | /* Interrupt Routing */ |
| 478 | u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */ |
| 479 | |
| 480 | /* Atomic Unit Control Area */ |
| 481 | u64 mfc_atomic_flush_RW; /* 0x200 */ |
| 482 | #define mfc_atomic_flush_enable 0x1L |
| 483 | u8 pad_0x208_0x280[0x78]; /* 0x208 */ |
| 484 | u64 resource_allocation_groupID_RW; /* 0x280 */ |
| 485 | u64 resource_allocation_enable_RW; /* 0x288 */ |
| 486 | u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */ |
| 487 | |
| 488 | /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */ |
| 489 | |
| 490 | u64 smf_sbi_signal_sel; /* 0x3c8 */ |
| 491 | #define smf_sbi_mask_lsb 56 |
| 492 | #define smf_sbi_shift (63 - smf_sbi_mask_lsb) |
| 493 | #define smf_sbi_mask (0x301LL << smf_sbi_shift) |
| 494 | #define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift) |
| 495 | #define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift) |
| 496 | #define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift) |
| 497 | #define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift) |
| 498 | u64 smf_ato_signal_sel; /* 0x3d0 */ |
| 499 | #define smf_ato_mask_lsb 35 |
| 500 | #define smf_ato_shift (63 - smf_ato_mask_lsb) |
| 501 | #define smf_ato_mask (0x3LL << smf_ato_shift) |
| 502 | #define smf_ato_bus0_bits (0x2LL << smf_ato_shift) |
| 503 | #define smf_ato_bus2_bits (0x1LL << smf_ato_shift) |
| 504 | u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */ |
| 505 | |
| 506 | /* TLB Management Registers */ |
| 507 | u64 mfc_sdr_RW; /* 0x400 */ |
| 508 | u8 pad_0x408_0x500[0xf8]; /* 0x408 */ |
| 509 | u64 tlb_index_hint_RO; /* 0x500 */ |
| 510 | u64 tlb_index_W; /* 0x508 */ |
| 511 | u64 tlb_vpn_RW; /* 0x510 */ |
| 512 | u64 tlb_rpn_RW; /* 0x518 */ |
| 513 | u8 pad_0x520_0x540[0x20]; /* 0x520 */ |
| 514 | u64 tlb_invalidate_entry_W; /* 0x540 */ |
| 515 | u64 tlb_invalidate_all_W; /* 0x548 */ |
| 516 | u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */ |
| 517 | |
| 518 | /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */ |
| 519 | u64 smm_hid; /* 0x580 */ |
| 520 | #define PAGE_SIZE_MASK 0xf000000000000000ull |
| 521 | #define PAGE_SIZE_16MB_64KB 0x2000000000000000ull |
| 522 | u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */ |
| 523 | |
| 524 | /* MFC Status/Control Area */ |
| 525 | u64 mfc_accr_RW; /* 0x600 */ |
| 526 | #define MFC_ACCR_EA_ACCESS_GET (1 << 0) |
| 527 | #define MFC_ACCR_EA_ACCESS_PUT (1 << 1) |
| 528 | #define MFC_ACCR_LS_ACCESS_GET (1 << 3) |
| 529 | #define MFC_ACCR_LS_ACCESS_PUT (1 << 4) |
| 530 | u8 pad_0x608_0x610[0x8]; /* 0x608 */ |
| 531 | u64 mfc_dsisr_RW; /* 0x610 */ |
| 532 | #define MFC_DSISR_PTE_NOT_FOUND (1 << 30) |
| 533 | #define MFC_DSISR_ACCESS_DENIED (1 << 27) |
| 534 | #define MFC_DSISR_ATOMIC (1 << 26) |
| 535 | #define MFC_DSISR_ACCESS_PUT (1 << 25) |
| 536 | #define MFC_DSISR_ADDR_MATCH (1 << 22) |
| 537 | #define MFC_DSISR_LS (1 << 17) |
| 538 | #define MFC_DSISR_L (1 << 16) |
| 539 | #define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0) |
| 540 | u8 pad_0x618_0x620[0x8]; /* 0x618 */ |
| 541 | u64 mfc_dar_RW; /* 0x620 */ |
| 542 | u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */ |
| 543 | |
| 544 | /* Replacement Management Table (RMT) Area */ |
| 545 | u64 rmt_index_RW; /* 0x700 */ |
| 546 | u8 pad_0x708_0x710[0x8]; /* 0x708 */ |
| 547 | u64 rmt_data1_RW; /* 0x710 */ |
| 548 | u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */ |
| 549 | |
| 550 | /* Control/Configuration Registers */ |
| 551 | u64 mfc_dsir_R; /* 0x800 */ |
| 552 | #define MFC_DSIR_Q (1 << 31) |
| 553 | #define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q |
| 554 | u64 mfc_lsacr_RW; /* 0x808 */ |
| 555 | #define MFC_LSACR_COMPARE_MASK ((~0ull) << 32) |
| 556 | #define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32) |
| 557 | u64 mfc_lscrr_R; /* 0x810 */ |
| 558 | #define MFC_LSCRR_Q (1 << 31) |
| 559 | #define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q |
| 560 | #define MFC_LSCRR_QI_SHIFT 32 |
| 561 | #define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT) |
| 562 | u8 pad_0x818_0x820[0x8]; /* 0x818 */ |
| 563 | u64 mfc_tclass_id_RW; /* 0x820 */ |
| 564 | #define MFC_TCLASS_ID_ENABLE (1L << 0L) |
| 565 | #define MFC_TCLASS_SLOT2_ENABLE (1L << 5L) |
| 566 | #define MFC_TCLASS_SLOT1_ENABLE (1L << 6L) |
| 567 | #define MFC_TCLASS_SLOT0_ENABLE (1L << 7L) |
| 568 | #define MFC_TCLASS_QUOTA_2_SHIFT 8L |
| 569 | #define MFC_TCLASS_QUOTA_1_SHIFT 16L |
| 570 | #define MFC_TCLASS_QUOTA_0_SHIFT 24L |
| 571 | #define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT) |
| 572 | #define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT) |
| 573 | #define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT) |
| 574 | u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */ |
| 575 | |
| 576 | /* Real Mode Support Registers */ |
| 577 | u64 mfc_rm_boundary; /* 0x900 */ |
| 578 | u8 pad_0x908_0x938[0x30]; /* 0x908 */ |
| 579 | u64 smf_dma_signal_sel; /* 0x938 */ |
| 580 | #define mfc_dma1_mask_lsb 41 |
| 581 | #define mfc_dma1_shift (63 - mfc_dma1_mask_lsb) |
| 582 | #define mfc_dma1_mask (0x3LL << mfc_dma1_shift) |
| 583 | #define mfc_dma1_bits (0x1LL << mfc_dma1_shift) |
| 584 | #define mfc_dma2_mask_lsb 43 |
| 585 | #define mfc_dma2_shift (63 - mfc_dma2_mask_lsb) |
| 586 | #define mfc_dma2_mask (0x3LL << mfc_dma2_shift) |
| 587 | #define mfc_dma2_bits (0x1LL << mfc_dma2_shift) |
| 588 | u8 pad_0x940_0xa38[0xf8]; /* 0x940 */ |
| 589 | u64 smm_signal_sel; /* 0xa38 */ |
| 590 | #define smm_sig_mask_lsb 12 |
| 591 | #define smm_sig_shift (63 - smm_sig_mask_lsb) |
| 592 | #define smm_sig_mask (0x3LL << smm_sig_shift) |
| 593 | #define smm_sig_bus0_bits (0x2LL << smm_sig_shift) |
| 594 | #define smm_sig_bus2_bits (0x1LL << smm_sig_shift) |
| 595 | u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */ |
| 596 | |
| 597 | /* DMA Command Error Area */ |
| 598 | u64 mfc_cer_R; /* 0xc00 */ |
| 599 | #define MFC_CER_Q (1 << 31) |
| 600 | #define MFC_CER_SPU_QUEUE MFC_CER_Q |
| 601 | u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */ |
| 602 | |
| 603 | /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */ |
| 604 | /* DMA Command Error Area */ |
| 605 | u64 spu_ecc_cntl_RW; /* 0x1000 */ |
| 606 | #define SPU_ECC_CNTL_E (1ull << 0ull) |
| 607 | #define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E |
| 608 | #define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L) |
| 609 | #define SPU_ECC_CNTL_S (1ull << 1ull) |
| 610 | #define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S |
| 611 | #define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L) |
| 612 | #define SPU_ECC_CNTL_B (1ull << 2ull) |
| 613 | #define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B |
| 614 | #define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L) |
| 615 | #define SPU_ECC_CNTL_I_SHIFT 3ull |
| 616 | #define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT) |
| 617 | #define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L) |
| 618 | #define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT) |
| 619 | #define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT) |
| 620 | #define SPU_ECC_CNTL_D (1ull << 5ull) |
| 621 | #define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D |
| 622 | #define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L) |
| 623 | u64 spu_ecc_stat_RW; /* 0x1008 */ |
| 624 | #define SPU_ECC_CORRECTED_ERROR (1ull << 0ul) |
| 625 | #define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul) |
| 626 | #define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul) |
| 627 | #define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul) |
| 628 | #define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul) |
| 629 | #define SPU_ECC_DATA_ERROR (1ull << 5ul) |
| 630 | #define SPU_ECC_DMA_ERROR (1ull << 6ul) |
| 631 | #define SPU_ECC_STATUS_CNT_MASK (256ull << 8) |
| 632 | u64 spu_ecc_addr_RW; /* 0x1010 */ |
| 633 | u64 spu_err_mask_RW; /* 0x1018 */ |
| 634 | #define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul) |
| 635 | #define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul) |
| 636 | u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */ |
| 637 | |
| 638 | /* SPU Debug-Trace Bus (DTB) Selection Registers */ |
| 639 | u64 spu_trig0_sel; /* 0x1028 */ |
| 640 | u64 spu_trig1_sel; /* 0x1030 */ |
| 641 | u64 spu_trig2_sel; /* 0x1038 */ |
| 642 | u64 spu_trig3_sel; /* 0x1040 */ |
| 643 | u64 spu_trace_sel; /* 0x1048 */ |
| 644 | #define spu_trace_sel_mask 0x1f1fLL |
| 645 | #define spu_trace_sel_bus0_bits 0x1000LL |
| 646 | #define spu_trace_sel_bus2_bits 0x0010LL |
| 647 | u64 spu_event0_sel; /* 0x1050 */ |
| 648 | u64 spu_event1_sel; /* 0x1058 */ |
| 649 | u64 spu_event2_sel; /* 0x1060 */ |
| 650 | u64 spu_event3_sel; /* 0x1068 */ |
| 651 | u64 spu_trace_cntl; /* 0x1070 */ |
| 652 | } __attribute__ ((aligned(0x2000))); |
| 653 | |
Arnd Bergmann | 88ced03 | 2005-12-16 22:43:46 +0100 | [diff] [blame] | 654 | #endif /* __KERNEL__ */ |
Arnd Bergmann | 67207b9 | 2005-11-15 15:53:48 -0500 | [diff] [blame] | 655 | #endif |