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Jacopo Mondi762c2812018-02-21 12:48:00 -05001// SPDX-License-Identifier: GPL-2.0
Jacopo Mondi1112bab2018-02-21 12:47:59 -05002/*
3 * ov772x Camera Driver
4 *
Jacopo Mondi762c2812018-02-21 12:48:00 -05005 * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 *
Jacopo Mondi1112bab2018-02-21 12:47:59 -05007 * Copyright (C) 2008 Renesas Solutions Corp.
8 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
9 *
10 * Based on ov7670 and soc_camera_platform driver,
11 *
12 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
13 * Copyright (C) 2008 Magnus Damm
14 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
Jacopo Mondi1112bab2018-02-21 12:47:59 -050015 */
16
Jacopo Mondi762c2812018-02-21 12:48:00 -050017#include <linux/clk.h>
18#include <linux/delay.h>
19#include <linux/gpio/consumer.h>
20#include <linux/i2c.h>
Jacopo Mondi1112bab2018-02-21 12:47:59 -050021#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
Akinobu Mita5bbf3222018-07-16 11:47:49 -040024#include <linux/regmap.h>
Jacopo Mondi1112bab2018-02-21 12:47:59 -050025#include <linux/slab.h>
Jacopo Mondi1112bab2018-02-21 12:47:59 -050026#include <linux/v4l2-mediabus.h>
27#include <linux/videodev2.h>
28
29#include <media/i2c/ov772x.h>
Jacopo Mondi762c2812018-02-21 12:48:00 -050030
Jacopo Mondi1112bab2018-02-21 12:47:59 -050031#include <media/v4l2-ctrls.h>
Jacopo Mondi762c2812018-02-21 12:48:00 -050032#include <media/v4l2-device.h>
Akinobu Mitabedfcd42018-11-12 11:00:54 -050033#include <media/v4l2-event.h>
Jacopo Mondi1112bab2018-02-21 12:47:59 -050034#include <media/v4l2-image-sizes.h>
Jacopo Mondi762c2812018-02-21 12:48:00 -050035#include <media/v4l2-subdev.h>
Jacopo Mondi1112bab2018-02-21 12:47:59 -050036
37/*
38 * register offset
39 */
40#define GAIN 0x00 /* AGC - Gain control gain setting */
41#define BLUE 0x01 /* AWB - Blue channel gain setting */
42#define RED 0x02 /* AWB - Red channel gain setting */
43#define GREEN 0x03 /* AWB - Green channel gain setting */
44#define COM1 0x04 /* Common control 1 */
45#define BAVG 0x05 /* U/B Average Level */
46#define GAVG 0x06 /* Y/Gb Average Level */
47#define RAVG 0x07 /* V/R Average Level */
48#define AECH 0x08 /* Exposure Value - AEC MSBs */
49#define COM2 0x09 /* Common control 2 */
50#define PID 0x0A /* Product ID Number MSB */
51#define VER 0x0B /* Product ID Number LSB */
52#define COM3 0x0C /* Common control 3 */
53#define COM4 0x0D /* Common control 4 */
54#define COM5 0x0E /* Common control 5 */
55#define COM6 0x0F /* Common control 6 */
56#define AEC 0x10 /* Exposure Value */
57#define CLKRC 0x11 /* Internal clock */
58#define COM7 0x12 /* Common control 7 */
59#define COM8 0x13 /* Common control 8 */
60#define COM9 0x14 /* Common control 9 */
61#define COM10 0x15 /* Common control 10 */
62#define REG16 0x16 /* Register 16 */
63#define HSTART 0x17 /* Horizontal sensor size */
64#define HSIZE 0x18 /* Horizontal frame (HREF column) end high 8-bit */
65#define VSTART 0x19 /* Vertical frame (row) start high 8-bit */
66#define VSIZE 0x1A /* Vertical sensor size */
67#define PSHFT 0x1B /* Data format - pixel delay select */
68#define MIDH 0x1C /* Manufacturer ID byte - high */
69#define MIDL 0x1D /* Manufacturer ID byte - low */
70#define LAEC 0x1F /* Fine AEC value */
71#define COM11 0x20 /* Common control 11 */
72#define BDBASE 0x22 /* Banding filter Minimum AEC value */
73#define DBSTEP 0x23 /* Banding filter Maximum Setp */
74#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
75#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
76#define VPT 0x26 /* AGC/AEC Fast mode operating region */
77#define REG28 0x28 /* Register 28 */
78#define HOUTSIZE 0x29 /* Horizontal data output size MSBs */
79#define EXHCH 0x2A /* Dummy pixel insert MSB */
80#define EXHCL 0x2B /* Dummy pixel insert LSB */
81#define VOUTSIZE 0x2C /* Vertical data output size MSBs */
82#define ADVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
83#define ADVFH 0x2E /* MSG of insert dummy lines in Vertical direction */
84#define YAVE 0x2F /* Y/G Channel Average value */
85#define LUMHTH 0x30 /* Histogram AEC/AGC Luminance high level threshold */
86#define LUMLTH 0x31 /* Histogram AEC/AGC Luminance low level threshold */
87#define HREF 0x32 /* Image start and size control */
88#define DM_LNL 0x33 /* Dummy line low 8 bits */
89#define DM_LNH 0x34 /* Dummy line high 8 bits */
90#define ADOFF_B 0x35 /* AD offset compensation value for B channel */
91#define ADOFF_R 0x36 /* AD offset compensation value for R channel */
92#define ADOFF_GB 0x37 /* AD offset compensation value for Gb channel */
93#define ADOFF_GR 0x38 /* AD offset compensation value for Gr channel */
94#define OFF_B 0x39 /* Analog process B channel offset value */
95#define OFF_R 0x3A /* Analog process R channel offset value */
96#define OFF_GB 0x3B /* Analog process Gb channel offset value */
97#define OFF_GR 0x3C /* Analog process Gr channel offset value */
98#define COM12 0x3D /* Common control 12 */
99#define COM13 0x3E /* Common control 13 */
100#define COM14 0x3F /* Common control 14 */
101#define COM15 0x40 /* Common control 15*/
102#define COM16 0x41 /* Common control 16 */
103#define TGT_B 0x42 /* BLC blue channel target value */
104#define TGT_R 0x43 /* BLC red channel target value */
105#define TGT_GB 0x44 /* BLC Gb channel target value */
106#define TGT_GR 0x45 /* BLC Gr channel target value */
107/* for ov7720 */
108#define LCC0 0x46 /* Lens correction control 0 */
109#define LCC1 0x47 /* Lens correction option 1 - X coordinate */
110#define LCC2 0x48 /* Lens correction option 2 - Y coordinate */
111#define LCC3 0x49 /* Lens correction option 3 */
112#define LCC4 0x4A /* Lens correction option 4 - radius of the circular */
113#define LCC5 0x4B /* Lens correction option 5 */
114#define LCC6 0x4C /* Lens correction option 6 */
115/* for ov7725 */
116#define LC_CTR 0x46 /* Lens correction control */
117#define LC_XC 0x47 /* X coordinate of lens correction center relative */
118#define LC_YC 0x48 /* Y coordinate of lens correction center relative */
119#define LC_COEF 0x49 /* Lens correction coefficient */
120#define LC_RADI 0x4A /* Lens correction radius */
121#define LC_COEFB 0x4B /* Lens B channel compensation coefficient */
122#define LC_COEFR 0x4C /* Lens R channel compensation coefficient */
123
124#define FIXGAIN 0x4D /* Analog fix gain amplifer */
125#define AREF0 0x4E /* Sensor reference control */
126#define AREF1 0x4F /* Sensor reference current control */
127#define AREF2 0x50 /* Analog reference control */
128#define AREF3 0x51 /* ADC reference control */
129#define AREF4 0x52 /* ADC reference control */
130#define AREF5 0x53 /* ADC reference control */
131#define AREF6 0x54 /* Analog reference control */
132#define AREF7 0x55 /* Analog reference control */
133#define UFIX 0x60 /* U channel fixed value output */
134#define VFIX 0x61 /* V channel fixed value output */
135#define AWBB_BLK 0x62 /* AWB option for advanced AWB */
136#define AWB_CTRL0 0x63 /* AWB control byte 0 */
137#define DSP_CTRL1 0x64 /* DSP control byte 1 */
138#define DSP_CTRL2 0x65 /* DSP control byte 2 */
139#define DSP_CTRL3 0x66 /* DSP control byte 3 */
140#define DSP_CTRL4 0x67 /* DSP control byte 4 */
141#define AWB_BIAS 0x68 /* AWB BLC level clip */
142#define AWB_CTRL1 0x69 /* AWB control 1 */
143#define AWB_CTRL2 0x6A /* AWB control 2 */
144#define AWB_CTRL3 0x6B /* AWB control 3 */
145#define AWB_CTRL4 0x6C /* AWB control 4 */
146#define AWB_CTRL5 0x6D /* AWB control 5 */
147#define AWB_CTRL6 0x6E /* AWB control 6 */
148#define AWB_CTRL7 0x6F /* AWB control 7 */
149#define AWB_CTRL8 0x70 /* AWB control 8 */
150#define AWB_CTRL9 0x71 /* AWB control 9 */
151#define AWB_CTRL10 0x72 /* AWB control 10 */
152#define AWB_CTRL11 0x73 /* AWB control 11 */
153#define AWB_CTRL12 0x74 /* AWB control 12 */
154#define AWB_CTRL13 0x75 /* AWB control 13 */
155#define AWB_CTRL14 0x76 /* AWB control 14 */
156#define AWB_CTRL15 0x77 /* AWB control 15 */
157#define AWB_CTRL16 0x78 /* AWB control 16 */
158#define AWB_CTRL17 0x79 /* AWB control 17 */
159#define AWB_CTRL18 0x7A /* AWB control 18 */
160#define AWB_CTRL19 0x7B /* AWB control 19 */
161#define AWB_CTRL20 0x7C /* AWB control 20 */
162#define AWB_CTRL21 0x7D /* AWB control 21 */
163#define GAM1 0x7E /* Gamma Curve 1st segment input end point */
164#define GAM2 0x7F /* Gamma Curve 2nd segment input end point */
165#define GAM3 0x80 /* Gamma Curve 3rd segment input end point */
166#define GAM4 0x81 /* Gamma Curve 4th segment input end point */
167#define GAM5 0x82 /* Gamma Curve 5th segment input end point */
168#define GAM6 0x83 /* Gamma Curve 6th segment input end point */
169#define GAM7 0x84 /* Gamma Curve 7th segment input end point */
170#define GAM8 0x85 /* Gamma Curve 8th segment input end point */
171#define GAM9 0x86 /* Gamma Curve 9th segment input end point */
172#define GAM10 0x87 /* Gamma Curve 10th segment input end point */
173#define GAM11 0x88 /* Gamma Curve 11th segment input end point */
174#define GAM12 0x89 /* Gamma Curve 12th segment input end point */
175#define GAM13 0x8A /* Gamma Curve 13th segment input end point */
176#define GAM14 0x8B /* Gamma Curve 14th segment input end point */
177#define GAM15 0x8C /* Gamma Curve 15th segment input end point */
178#define SLOP 0x8D /* Gamma curve highest segment slope */
179#define DNSTH 0x8E /* De-noise threshold */
180#define EDGE_STRNGT 0x8F /* Edge strength control when manual mode */
181#define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */
182#define DNSOFF 0x91 /* Auto De-noise threshold control */
183#define EDGE_UPPER 0x92 /* Edge strength upper limit when Auto mode */
184#define EDGE_LOWER 0x93 /* Edge strength lower limit when Auto mode */
185#define MTX1 0x94 /* Matrix coefficient 1 */
186#define MTX2 0x95 /* Matrix coefficient 2 */
187#define MTX3 0x96 /* Matrix coefficient 3 */
188#define MTX4 0x97 /* Matrix coefficient 4 */
189#define MTX5 0x98 /* Matrix coefficient 5 */
190#define MTX6 0x99 /* Matrix coefficient 6 */
191#define MTX_CTRL 0x9A /* Matrix control */
192#define BRIGHT 0x9B /* Brightness control */
193#define CNTRST 0x9C /* Contrast contrast */
194#define CNTRST_CTRL 0x9D /* Contrast contrast center */
195#define UVAD_J0 0x9E /* Auto UV adjust contrast 0 */
196#define UVAD_J1 0x9F /* Auto UV adjust contrast 1 */
197#define SCAL0 0xA0 /* Scaling control 0 */
198#define SCAL1 0xA1 /* Scaling control 1 */
199#define SCAL2 0xA2 /* Scaling control 2 */
200#define FIFODLYM 0xA3 /* FIFO manual mode delay control */
201#define FIFODLYA 0xA4 /* FIFO auto mode delay control */
202#define SDE 0xA6 /* Special digital effect control */
203#define USAT 0xA7 /* U component saturation control */
204#define VSAT 0xA8 /* V component saturation control */
205/* for ov7720 */
206#define HUE0 0xA9 /* Hue control 0 */
207#define HUE1 0xAA /* Hue control 1 */
208/* for ov7725 */
209#define HUECOS 0xA9 /* Cosine value */
210#define HUESIN 0xAA /* Sine value */
211
212#define SIGN 0xAB /* Sign bit for Hue and contrast */
213#define DSPAUTO 0xAC /* DSP auto function ON/OFF control */
214
215/*
216 * register detail
217 */
218
219/* COM2 */
220#define SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
221 /* Output drive capability */
222#define OCAP_1x 0x00 /* 1x */
223#define OCAP_2x 0x01 /* 2x */
224#define OCAP_3x 0x02 /* 3x */
225#define OCAP_4x 0x03 /* 4x */
226
227/* COM3 */
228#define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML)
229#define IMG_MASK (VFLIP_IMG | HFLIP_IMG)
230
231#define VFLIP_IMG 0x80 /* Vertical flip image ON/OFF selection */
232#define HFLIP_IMG 0x40 /* Horizontal mirror image ON/OFF selection */
233#define SWAP_RGB 0x20 /* Swap B/R output sequence in RGB mode */
234#define SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV mode */
235#define SWAP_ML 0x08 /* Swap output MSB/LSB */
236 /* Tri-state option for output clock */
237#define NOTRI_CLOCK 0x04 /* 0: Tri-state at this period */
238 /* 1: No tri-state at this period */
239 /* Tri-state option for output data */
240#define NOTRI_DATA 0x02 /* 0: Tri-state at this period */
241 /* 1: No tri-state at this period */
242#define SCOLOR_TEST 0x01 /* Sensor color bar test pattern */
243
244/* COM4 */
245 /* PLL frequency control */
246#define PLL_BYPASS 0x00 /* 00: Bypass PLL */
247#define PLL_4x 0x40 /* 01: PLL 4x */
248#define PLL_6x 0x80 /* 10: PLL 6x */
249#define PLL_8x 0xc0 /* 11: PLL 8x */
250 /* AEC evaluate window */
251#define AEC_FULL 0x00 /* 00: Full window */
252#define AEC_1p2 0x10 /* 01: 1/2 window */
253#define AEC_1p4 0x20 /* 10: 1/4 window */
254#define AEC_2p3 0x30 /* 11: Low 2/3 window */
Jacopo Mondi35089492018-02-21 12:48:01 -0500255#define COM4_RESERVED 0x01 /* Reserved bit */
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500256
257/* COM5 */
258#define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */
259#define AFR_SPPED 0x40 /* Auto frame rate control speed selection */
260 /* Auto frame rate max rate control */
261#define AFR_NO_RATE 0x00 /* No reduction of frame rate */
262#define AFR_1p2 0x10 /* Max reduction to 1/2 frame rate */
263#define AFR_1p4 0x20 /* Max reduction to 1/4 frame rate */
264#define AFR_1p8 0x30 /* Max reduction to 1/8 frame rate */
265 /* Auto frame rate active point control */
266#define AF_2x 0x00 /* Add frame when AGC reaches 2x gain */
267#define AF_4x 0x04 /* Add frame when AGC reaches 4x gain */
268#define AF_8x 0x08 /* Add frame when AGC reaches 8x gain */
269#define AF_16x 0x0c /* Add frame when AGC reaches 16x gain */
270 /* AEC max step control */
271#define AEC_NO_LIMIT 0x01 /* 0 : AEC incease step has limit */
272 /* 1 : No limit to AEC increase step */
Jacopo Mondi35089492018-02-21 12:48:01 -0500273/* CLKRC */
274 /* Input clock divider register */
275#define CLKRC_RESERVED 0x80 /* Reserved bit */
276#define CLKRC_DIV(n) ((n) - 1)
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500277
278/* COM7 */
279 /* SCCB Register Reset */
280#define SCCB_RESET 0x80 /* 0 : No change */
281 /* 1 : Resets all registers to default */
282 /* Resolution selection */
283#define SLCT_MASK 0x40 /* Mask of VGA or QVGA */
284#define SLCT_VGA 0x00 /* 0 : VGA */
285#define SLCT_QVGA 0x40 /* 1 : QVGA */
286#define ITU656_ON_OFF 0x20 /* ITU656 protocol ON/OFF selection */
287#define SENSOR_RAW 0x10 /* Sensor RAW */
288 /* RGB output format control */
289#define FMT_MASK 0x0c /* Mask of color format */
290#define FMT_GBR422 0x00 /* 00 : GBR 4:2:2 */
291#define FMT_RGB565 0x04 /* 01 : RGB 565 */
292#define FMT_RGB555 0x08 /* 10 : RGB 555 */
293#define FMT_RGB444 0x0c /* 11 : RGB 444 */
294 /* Output format control */
295#define OFMT_MASK 0x03 /* Mask of output format */
296#define OFMT_YUV 0x00 /* 00 : YUV */
297#define OFMT_P_BRAW 0x01 /* 01 : Processed Bayer RAW */
298#define OFMT_RGB 0x02 /* 10 : RGB */
299#define OFMT_BRAW 0x03 /* 11 : Bayer RAW */
300
301/* COM8 */
302#define FAST_ALGO 0x80 /* Enable fast AGC/AEC algorithm */
303 /* AEC Setp size limit */
304#define UNLMT_STEP 0x40 /* 0 : Step size is limited */
305 /* 1 : Unlimited step size */
306#define BNDF_ON_OFF 0x20 /* Banding filter ON/OFF */
307#define AEC_BND 0x10 /* Enable AEC below banding value */
308#define AEC_ON_OFF 0x08 /* Fine AEC ON/OFF control */
309#define AGC_ON 0x04 /* AGC Enable */
310#define AWB_ON 0x02 /* AWB Enable */
311#define AEC_ON 0x01 /* AEC Enable */
312
313/* COM9 */
314#define BASE_AECAGC 0x80 /* Histogram or average based AEC/AGC */
315 /* Automatic gain ceiling - maximum AGC value */
316#define GAIN_2x 0x00 /* 000 : 2x */
317#define GAIN_4x 0x10 /* 001 : 4x */
318#define GAIN_8x 0x20 /* 010 : 8x */
319#define GAIN_16x 0x30 /* 011 : 16x */
320#define GAIN_32x 0x40 /* 100 : 32x */
321#define GAIN_64x 0x50 /* 101 : 64x */
322#define GAIN_128x 0x60 /* 110 : 128x */
323#define DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
324#define DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
325
326/* COM11 */
327#define SGLF_ON_OFF 0x02 /* Single frame ON/OFF selection */
328#define SGLF_TRIG 0x01 /* Single frame transfer trigger */
329
330/* HREF */
331#define HREF_VSTART_SHIFT 6 /* VSTART LSB */
332#define HREF_HSTART_SHIFT 4 /* HSTART 2 LSBs */
333#define HREF_VSIZE_SHIFT 2 /* VSIZE LSB */
334#define HREF_HSIZE_SHIFT 0 /* HSIZE 2 LSBs */
335
336/* EXHCH */
337#define EXHCH_VSIZE_SHIFT 2 /* VOUTSIZE LSB */
338#define EXHCH_HSIZE_SHIFT 0 /* HOUTSIZE 2 LSBs */
339
340/* DSP_CTRL1 */
341#define FIFO_ON 0x80 /* FIFO enable/disable selection */
342#define UV_ON_OFF 0x40 /* UV adjust function ON/OFF selection */
343#define YUV444_2_422 0x20 /* YUV444 to 422 UV channel option selection */
344#define CLR_MTRX_ON_OFF 0x10 /* Color matrix ON/OFF selection */
345#define INTPLT_ON_OFF 0x08 /* Interpolation ON/OFF selection */
346#define GMM_ON_OFF 0x04 /* Gamma function ON/OFF selection */
347#define AUTO_BLK_ON_OFF 0x02 /* Black defect auto correction ON/OFF */
348#define AUTO_WHT_ON_OFF 0x01 /* White define auto correction ON/OFF */
349
350/* DSP_CTRL3 */
351#define UV_MASK 0x80 /* UV output sequence option */
352#define UV_ON 0x80 /* ON */
353#define UV_OFF 0x00 /* OFF */
354#define CBAR_MASK 0x20 /* DSP Color bar mask */
355#define CBAR_ON 0x20 /* ON */
356#define CBAR_OFF 0x00 /* OFF */
357
358/* DSP_CTRL4 */
359#define DSP_OFMT_YUV 0x00
360#define DSP_OFMT_RGB 0x00
361#define DSP_OFMT_RAW8 0x02
362#define DSP_OFMT_RAW10 0x03
363
364/* DSPAUTO (DSP Auto Function ON/OFF Control) */
365#define AWB_ACTRL 0x80 /* AWB auto threshold control */
366#define DENOISE_ACTRL 0x40 /* De-noise auto threshold control */
367#define EDGE_ACTRL 0x20 /* Edge enhancement auto strength control */
368#define UV_ACTRL 0x10 /* UV adjust auto slope control */
369#define SCAL0_ACTRL 0x08 /* Auto scaling factor control */
370#define SCAL1_2_ACTRL 0x04 /* Auto scaling factor control */
371
372#define OV772X_MAX_WIDTH VGA_WIDTH
373#define OV772X_MAX_HEIGHT VGA_HEIGHT
374
375/*
376 * ID
377 */
378#define OV7720 0x7720
379#define OV7725 0x7721
Mauro Carvalho Chehab054d8832018-02-26 09:23:32 -0500380#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF))
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500381
382/*
Jacopo Mondi35089492018-02-21 12:48:01 -0500383 * PLL multipliers
384 */
385static struct {
386 unsigned int mult;
387 u8 com4;
388} ov772x_pll[] = {
389 { 1, PLL_BYPASS, },
390 { 4, PLL_4x, },
391 { 6, PLL_6x, },
392 { 8, PLL_8x, },
393};
394
395/*
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500396 * struct
397 */
398
399struct ov772x_color_format {
400 u32 code;
401 enum v4l2_colorspace colorspace;
402 u8 dsp3;
403 u8 dsp4;
404 u8 com3;
405 u8 com7;
406};
407
408struct ov772x_win_size {
409 char *name;
410 unsigned char com7_bit;
Jacopo Mondi35089492018-02-21 12:48:01 -0500411 unsigned int sizeimage;
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500412 struct v4l2_rect rect;
413};
414
415struct ov772x_priv {
416 struct v4l2_subdev subdev;
417 struct v4l2_ctrl_handler hdl;
Jacopo Mondi762c2812018-02-21 12:48:00 -0500418 struct clk *clk;
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400419 struct regmap *regmap;
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500420 struct ov772x_camera_info *info;
Jacopo Mondi762c2812018-02-21 12:48:00 -0500421 struct gpio_desc *pwdn_gpio;
422 struct gpio_desc *rstb_gpio;
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500423 const struct ov772x_color_format *cfmt;
424 const struct ov772x_win_size *win;
Akinobu Mita09e620c2018-05-06 10:19:26 -0400425 struct v4l2_ctrl *vflip_ctrl;
426 struct v4l2_ctrl *hflip_ctrl;
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500427 /* band_filter = COM8[5] ? 256 - BDBASE : 0 */
Akinobu Mita09e620c2018-05-06 10:19:26 -0400428 struct v4l2_ctrl *band_filter_ctrl;
Jacopo Mondi35089492018-02-21 12:48:01 -0500429 unsigned int fps;
Akinobu Mita7b9998c2018-05-06 10:19:28 -0400430 /* lock to protect power_count and streaming */
Akinobu Mita34af7d92018-05-06 10:19:24 -0400431 struct mutex lock;
432 int power_count;
Akinobu Mita7b9998c2018-05-06 10:19:28 -0400433 int streaming;
Akinobu Mita4b610d62018-05-06 10:19:20 -0400434#ifdef CONFIG_MEDIA_CONTROLLER
435 struct media_pad pad;
436#endif
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500437};
438
439/*
440 * supported color format list
441 */
442static const struct ov772x_color_format ov772x_cfmts[] = {
443 {
444 .code = MEDIA_BUS_FMT_YUYV8_2X8,
Jacopo Mondi762c2812018-02-21 12:48:00 -0500445 .colorspace = V4L2_COLORSPACE_SRGB,
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500446 .dsp3 = 0x0,
447 .dsp4 = DSP_OFMT_YUV,
448 .com3 = SWAP_YUV,
449 .com7 = OFMT_YUV,
450 },
451 {
452 .code = MEDIA_BUS_FMT_YVYU8_2X8,
Jacopo Mondi762c2812018-02-21 12:48:00 -0500453 .colorspace = V4L2_COLORSPACE_SRGB,
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500454 .dsp3 = UV_ON,
455 .dsp4 = DSP_OFMT_YUV,
456 .com3 = SWAP_YUV,
457 .com7 = OFMT_YUV,
458 },
459 {
460 .code = MEDIA_BUS_FMT_UYVY8_2X8,
Jacopo Mondi762c2812018-02-21 12:48:00 -0500461 .colorspace = V4L2_COLORSPACE_SRGB,
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500462 .dsp3 = 0x0,
463 .dsp4 = DSP_OFMT_YUV,
464 .com3 = 0x0,
465 .com7 = OFMT_YUV,
466 },
467 {
468 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
469 .colorspace = V4L2_COLORSPACE_SRGB,
470 .dsp3 = 0x0,
471 .dsp4 = DSP_OFMT_YUV,
472 .com3 = SWAP_RGB,
473 .com7 = FMT_RGB555 | OFMT_RGB,
474 },
475 {
476 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
477 .colorspace = V4L2_COLORSPACE_SRGB,
478 .dsp3 = 0x0,
479 .dsp4 = DSP_OFMT_YUV,
480 .com3 = 0x0,
481 .com7 = FMT_RGB555 | OFMT_RGB,
482 },
483 {
484 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
485 .colorspace = V4L2_COLORSPACE_SRGB,
486 .dsp3 = 0x0,
487 .dsp4 = DSP_OFMT_YUV,
488 .com3 = SWAP_RGB,
489 .com7 = FMT_RGB565 | OFMT_RGB,
490 },
491 {
492 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
493 .colorspace = V4L2_COLORSPACE_SRGB,
494 .dsp3 = 0x0,
495 .dsp4 = DSP_OFMT_YUV,
496 .com3 = 0x0,
497 .com7 = FMT_RGB565 | OFMT_RGB,
498 },
499 {
500 /* Setting DSP4 to DSP_OFMT_RAW8 still gives 10-bit output,
501 * regardless of the COM7 value. We can thus only support 10-bit
502 * Bayer until someone figures it out.
503 */
504 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
505 .colorspace = V4L2_COLORSPACE_SRGB,
506 .dsp3 = 0x0,
507 .dsp4 = DSP_OFMT_RAW10,
508 .com3 = 0x0,
509 .com7 = SENSOR_RAW | OFMT_BRAW,
510 },
511};
512
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500513/*
514 * window size list
515 */
516
517static const struct ov772x_win_size ov772x_win_sizes[] = {
518 {
Jacopo Mondi35089492018-02-21 12:48:01 -0500519 .name = "VGA",
520 .com7_bit = SLCT_VGA,
521 .sizeimage = 510 * 748,
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500522 .rect = {
Jacopo Mondi35089492018-02-21 12:48:01 -0500523 .left = 140,
524 .top = 14,
525 .width = VGA_WIDTH,
526 .height = VGA_HEIGHT,
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500527 },
528 }, {
Jacopo Mondi35089492018-02-21 12:48:01 -0500529 .name = "QVGA",
530 .com7_bit = SLCT_QVGA,
531 .sizeimage = 278 * 576,
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500532 .rect = {
Jacopo Mondi35089492018-02-21 12:48:01 -0500533 .left = 252,
534 .top = 6,
535 .width = QVGA_WIDTH,
536 .height = QVGA_HEIGHT,
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500537 },
538 },
539};
540
541/*
Jacopo Mondi35089492018-02-21 12:48:01 -0500542 * frame rate settings lists
543 */
Mauro Carvalho Chehab7b69f2c2018-03-06 10:34:44 -0500544static const unsigned int ov772x_frame_intervals[] = { 5, 10, 15, 20, 30, 60 };
Jacopo Mondi35089492018-02-21 12:48:01 -0500545
546/*
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500547 * general function
548 */
549
550static struct ov772x_priv *to_ov772x(struct v4l2_subdev *sd)
551{
552 return container_of(sd, struct ov772x_priv, subdev);
553}
554
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400555static int ov772x_reset(struct ov772x_priv *priv)
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500556{
557 int ret;
558
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400559 ret = regmap_write(priv->regmap, COM7, SCCB_RESET);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500560 if (ret < 0)
561 return ret;
562
Jacopo Mondid9c70bb2018-03-02 09:46:42 -0500563 usleep_range(1000, 5000);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500564
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400565 return regmap_update_bits(priv->regmap, COM2, SOFT_SLEEP_MODE,
566 SOFT_SLEEP_MODE);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500567}
568
569/*
Jacopo Mondi762c2812018-02-21 12:48:00 -0500570 * subdev ops
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500571 */
572
573static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
574{
575 struct i2c_client *client = v4l2_get_subdevdata(sd);
576 struct ov772x_priv *priv = to_ov772x(sd);
Akinobu Mita7b9998c2018-05-06 10:19:28 -0400577 int ret = 0;
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500578
Akinobu Mita7b9998c2018-05-06 10:19:28 -0400579 mutex_lock(&priv->lock);
580
581 if (priv->streaming == enable)
582 goto done;
583
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400584 ret = regmap_update_bits(priv->regmap, COM2, SOFT_SLEEP_MODE,
585 enable ? 0 : SOFT_SLEEP_MODE);
Akinobu Mita7b9998c2018-05-06 10:19:28 -0400586 if (ret)
587 goto done;
588
589 if (enable) {
590 dev_dbg(&client->dev, "format %d, win %s\n",
591 priv->cfmt->code, priv->win->name);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500592 }
Akinobu Mita7b9998c2018-05-06 10:19:28 -0400593 priv->streaming = enable;
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500594
Akinobu Mita7b9998c2018-05-06 10:19:28 -0400595done:
596 mutex_unlock(&priv->lock);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500597
Akinobu Mita7b9998c2018-05-06 10:19:28 -0400598 return ret;
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500599}
600
Akinobu Mita80dc2a42018-05-06 10:19:25 -0400601static unsigned int ov772x_select_fps(struct ov772x_priv *priv,
602 struct v4l2_fract *tpf)
Jacopo Mondi35089492018-02-21 12:48:01 -0500603{
Jacopo Mondi35089492018-02-21 12:48:01 -0500604 unsigned int fps = tpf->numerator ?
605 tpf->denominator / tpf->numerator :
606 tpf->denominator;
607 unsigned int best_diff;
Jacopo Mondi35089492018-02-21 12:48:01 -0500608 unsigned int diff;
609 unsigned int idx;
610 unsigned int i;
Jacopo Mondi35089492018-02-21 12:48:01 -0500611
612 /* Approximate to the closest supported frame interval. */
613 best_diff = ~0L;
614 for (i = 0, idx = 0; i < ARRAY_SIZE(ov772x_frame_intervals); i++) {
615 diff = abs(fps - ov772x_frame_intervals[i]);
616 if (diff < best_diff) {
617 idx = i;
618 best_diff = diff;
619 }
620 }
Akinobu Mita80dc2a42018-05-06 10:19:25 -0400621
622 return ov772x_frame_intervals[idx];
623}
624
625static int ov772x_set_frame_rate(struct ov772x_priv *priv,
626 unsigned int fps,
627 const struct ov772x_color_format *cfmt,
628 const struct ov772x_win_size *win)
629{
Akinobu Mita80dc2a42018-05-06 10:19:25 -0400630 unsigned long fin = clk_get_rate(priv->clk);
631 unsigned int best_diff;
632 unsigned int fsize;
633 unsigned int pclk;
634 unsigned int diff;
635 unsigned int i;
636 u8 clkrc = 0;
637 u8 com4 = 0;
638 int ret;
Jacopo Mondi35089492018-02-21 12:48:01 -0500639
640 /* Use image size (with blankings) to calculate desired pixel clock. */
641 switch (cfmt->com7 & OFMT_MASK) {
642 case OFMT_BRAW:
643 fsize = win->sizeimage;
644 break;
645 case OFMT_RGB:
646 case OFMT_YUV:
647 default:
648 fsize = win->sizeimage * 2;
649 break;
650 }
651
652 pclk = fps * fsize;
653
654 /*
655 * Pixel clock generation circuit is pretty simple:
656 *
657 * Fin -> [ / CLKRC_div] -> [ * PLL_mult] -> pclk
658 *
659 * Try to approximate the desired pixel clock testing all available
660 * PLL multipliers (1x, 4x, 6x, 8x) and calculate corresponding
661 * divisor with:
662 *
663 * div = PLL_mult * Fin / pclk
664 *
665 * and re-calculate the pixel clock using it:
666 *
667 * pclk = Fin * PLL_mult / CLKRC_div
668 *
669 * Choose the PLL_mult and CLKRC_div pair that gives a pixel clock
670 * closer to the desired one.
671 *
672 * The desired pixel clock is calculated using a known frame size
673 * (blanking included) and FPS.
674 */
675 best_diff = ~0L;
676 for (i = 0; i < ARRAY_SIZE(ov772x_pll); i++) {
677 unsigned int pll_mult = ov772x_pll[i].mult;
678 unsigned int pll_out = pll_mult * fin;
679 unsigned int t_pclk;
680 unsigned int div;
681
682 if (pll_out < pclk)
683 continue;
684
685 div = DIV_ROUND_CLOSEST(pll_out, pclk);
686 t_pclk = DIV_ROUND_CLOSEST(fin * pll_mult, div);
687 diff = abs(pclk - t_pclk);
688 if (diff < best_diff) {
689 best_diff = diff;
690 clkrc = CLKRC_DIV(div);
691 com4 = ov772x_pll[i].com4;
692 }
693 }
694
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400695 ret = regmap_write(priv->regmap, COM4, com4 | COM4_RESERVED);
Jacopo Mondi35089492018-02-21 12:48:01 -0500696 if (ret < 0)
697 return ret;
698
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400699 ret = regmap_write(priv->regmap, CLKRC, clkrc | CLKRC_RESERVED);
Jacopo Mondi35089492018-02-21 12:48:01 -0500700 if (ret < 0)
701 return ret;
702
Jacopo Mondi35089492018-02-21 12:48:01 -0500703 return 0;
704}
705
706static int ov772x_g_frame_interval(struct v4l2_subdev *sd,
707 struct v4l2_subdev_frame_interval *ival)
708{
709 struct ov772x_priv *priv = to_ov772x(sd);
710 struct v4l2_fract *tpf = &ival->interval;
711
712 tpf->numerator = 1;
713 tpf->denominator = priv->fps;
714
715 return 0;
716}
717
718static int ov772x_s_frame_interval(struct v4l2_subdev *sd,
719 struct v4l2_subdev_frame_interval *ival)
720{
721 struct ov772x_priv *priv = to_ov772x(sd);
722 struct v4l2_fract *tpf = &ival->interval;
Akinobu Mita80dc2a42018-05-06 10:19:25 -0400723 unsigned int fps;
Akinobu Mita95f5a452018-05-06 10:19:27 -0400724 int ret = 0;
Jacopo Mondi35089492018-02-21 12:48:01 -0500725
Akinobu Mita7b9998c2018-05-06 10:19:28 -0400726 mutex_lock(&priv->lock);
727
728 if (priv->streaming) {
729 ret = -EBUSY;
730 goto error;
731 }
732
Akinobu Mita80dc2a42018-05-06 10:19:25 -0400733 fps = ov772x_select_fps(priv, tpf);
734
Akinobu Mita95f5a452018-05-06 10:19:27 -0400735 /*
736 * If the device is not powered up by the host driver do
737 * not apply any changes to H/W at this time. Instead
738 * the frame rate will be restored right after power-up.
739 */
740 if (priv->power_count > 0) {
741 ret = ov772x_set_frame_rate(priv, fps, priv->cfmt, priv->win);
742 if (ret)
743 goto error;
744 }
Akinobu Mita80dc2a42018-05-06 10:19:25 -0400745
746 tpf->numerator = 1;
747 tpf->denominator = fps;
748 priv->fps = fps;
749
Akinobu Mita95f5a452018-05-06 10:19:27 -0400750error:
751 mutex_unlock(&priv->lock);
752
753 return ret;
Jacopo Mondi35089492018-02-21 12:48:01 -0500754}
755
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500756static int ov772x_s_ctrl(struct v4l2_ctrl *ctrl)
757{
758 struct ov772x_priv *priv = container_of(ctrl->handler,
759 struct ov772x_priv, hdl);
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400760 struct regmap *regmap = priv->regmap;
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500761 int ret = 0;
762 u8 val;
763
Akinobu Mita95f5a452018-05-06 10:19:27 -0400764 /* v4l2_ctrl_lock() locks our own mutex */
765
766 /*
767 * If the device is not powered up by the host driver do
768 * not apply any controls to H/W at this time. Instead
769 * the controls will be restored right after power-up.
770 */
771 if (priv->power_count == 0)
772 return 0;
773
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500774 switch (ctrl->id) {
775 case V4L2_CID_VFLIP:
776 val = ctrl->val ? VFLIP_IMG : 0x00;
Akinobu Mitac2cae892018-05-06 10:19:23 -0400777 if (priv->info && (priv->info->flags & OV772X_FLAG_VFLIP))
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500778 val ^= VFLIP_IMG;
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400779 return regmap_update_bits(regmap, COM3, VFLIP_IMG, val);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500780 case V4L2_CID_HFLIP:
781 val = ctrl->val ? HFLIP_IMG : 0x00;
Akinobu Mitac2cae892018-05-06 10:19:23 -0400782 if (priv->info && (priv->info->flags & OV772X_FLAG_HFLIP))
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500783 val ^= HFLIP_IMG;
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400784 return regmap_update_bits(regmap, COM3, HFLIP_IMG, val);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500785 case V4L2_CID_BAND_STOP_FILTER:
786 if (!ctrl->val) {
787 /* Switch the filter off, it is on now */
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400788 ret = regmap_update_bits(regmap, BDBASE, 0xff, 0xff);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500789 if (!ret)
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400790 ret = regmap_update_bits(regmap, COM8,
791 BNDF_ON_OFF, 0);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500792 } else {
793 /* Switch the filter on, set AEC low limit */
794 val = 256 - ctrl->val;
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400795 ret = regmap_update_bits(regmap, COM8,
796 BNDF_ON_OFF, BNDF_ON_OFF);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500797 if (!ret)
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400798 ret = regmap_update_bits(regmap, BDBASE,
799 0xff, val);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500800 }
Akinobu Mita09e620c2018-05-06 10:19:26 -0400801
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500802 return ret;
803 }
804
805 return -EINVAL;
806}
807
808#ifdef CONFIG_VIDEO_ADV_DEBUG
809static int ov772x_g_register(struct v4l2_subdev *sd,
810 struct v4l2_dbg_register *reg)
811{
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400812 struct ov772x_priv *priv = to_ov772x(sd);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500813 int ret;
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400814 unsigned int val;
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500815
816 reg->size = 1;
817 if (reg->reg > 0xff)
818 return -EINVAL;
819
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400820 ret = regmap_read(priv->regmap, reg->reg, &val);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500821 if (ret < 0)
822 return ret;
823
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400824 reg->val = (__u64)val;
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500825
826 return 0;
827}
828
829static int ov772x_s_register(struct v4l2_subdev *sd,
830 const struct v4l2_dbg_register *reg)
831{
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400832 struct ov772x_priv *priv = to_ov772x(sd);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500833
834 if (reg->reg > 0xff ||
835 reg->val > 0xff)
836 return -EINVAL;
837
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400838 return regmap_write(priv->regmap, reg->reg, reg->val);
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500839}
840#endif
841
Jacopo Mondi762c2812018-02-21 12:48:00 -0500842static int ov772x_power_on(struct ov772x_priv *priv)
843{
844 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
845 int ret;
846
847 if (priv->clk) {
848 ret = clk_prepare_enable(priv->clk);
849 if (ret)
850 return ret;
851 }
852
853 if (priv->pwdn_gpio) {
854 gpiod_set_value(priv->pwdn_gpio, 1);
855 usleep_range(500, 1000);
856 }
857
858 /*
859 * FIXME: The reset signal is connected to a shared GPIO on some
860 * platforms (namely the SuperH Migo-R). Until a framework becomes
861 * available to handle this cleanly, request the GPIO temporarily
862 * to avoid conflicts.
863 */
Akinobu Mita40519d52018-05-06 10:19:21 -0400864 priv->rstb_gpio = gpiod_get_optional(&client->dev, "reset",
Jacopo Mondi762c2812018-02-21 12:48:00 -0500865 GPIOD_OUT_LOW);
866 if (IS_ERR(priv->rstb_gpio)) {
Akinobu Mita40519d52018-05-06 10:19:21 -0400867 dev_info(&client->dev, "Unable to get GPIO \"reset\"");
Alexey Khoroshilov1d18c2c2018-08-15 16:10:39 -0400868 clk_disable_unprepare(priv->clk);
Jacopo Mondi762c2812018-02-21 12:48:00 -0500869 return PTR_ERR(priv->rstb_gpio);
870 }
871
872 if (priv->rstb_gpio) {
873 gpiod_set_value(priv->rstb_gpio, 1);
874 usleep_range(500, 1000);
875 gpiod_set_value(priv->rstb_gpio, 0);
876 usleep_range(500, 1000);
877
878 gpiod_put(priv->rstb_gpio);
879 }
880
881 return 0;
882}
883
884static int ov772x_power_off(struct ov772x_priv *priv)
885{
886 clk_disable_unprepare(priv->clk);
887
888 if (priv->pwdn_gpio) {
889 gpiod_set_value(priv->pwdn_gpio, 0);
890 usleep_range(500, 1000);
891 }
892
893 return 0;
894}
895
Akinobu Mita95f5a452018-05-06 10:19:27 -0400896static int ov772x_set_params(struct ov772x_priv *priv,
897 const struct ov772x_color_format *cfmt,
898 const struct ov772x_win_size *win);
899
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500900static int ov772x_s_power(struct v4l2_subdev *sd, int on)
901{
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500902 struct ov772x_priv *priv = to_ov772x(sd);
Akinobu Mita34af7d92018-05-06 10:19:24 -0400903 int ret = 0;
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500904
Akinobu Mita34af7d92018-05-06 10:19:24 -0400905 mutex_lock(&priv->lock);
906
907 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
908 * update the power state.
909 */
Akinobu Mita95f5a452018-05-06 10:19:27 -0400910 if (priv->power_count == !on) {
911 if (on) {
912 ret = ov772x_power_on(priv);
913 /*
914 * Restore the format, the frame rate, and
915 * the controls
916 */
917 if (!ret)
918 ret = ov772x_set_params(priv, priv->cfmt,
919 priv->win);
920 } else {
921 ret = ov772x_power_off(priv);
922 }
923 }
Akinobu Mita34af7d92018-05-06 10:19:24 -0400924
925 if (!ret) {
926 /* Update the power count. */
927 priv->power_count += on ? 1 : -1;
928 WARN(priv->power_count < 0, "Unbalanced power count\n");
929 WARN(priv->power_count > 1, "Duplicated s_power call\n");
930 }
931
932 mutex_unlock(&priv->lock);
933
934 return ret;
Jacopo Mondi1112bab2018-02-21 12:47:59 -0500935}
936
937static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height)
938{
939 const struct ov772x_win_size *win = &ov772x_win_sizes[0];
940 u32 best_diff = UINT_MAX;
941 unsigned int i;
942
943 for (i = 0; i < ARRAY_SIZE(ov772x_win_sizes); ++i) {
944 u32 diff = abs(width - ov772x_win_sizes[i].rect.width)
945 + abs(height - ov772x_win_sizes[i].rect.height);
946 if (diff < best_diff) {
947 best_diff = diff;
948 win = &ov772x_win_sizes[i];
949 }
950 }
951
952 return win;
953}
954
955static void ov772x_select_params(const struct v4l2_mbus_framefmt *mf,
956 const struct ov772x_color_format **cfmt,
957 const struct ov772x_win_size **win)
958{
959 unsigned int i;
960
961 /* Select a format. */
962 *cfmt = &ov772x_cfmts[0];
963
964 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
965 if (mf->code == ov772x_cfmts[i].code) {
966 *cfmt = &ov772x_cfmts[i];
967 break;
968 }
969 }
970
971 /* Select a window size. */
972 *win = ov772x_select_win(mf->width, mf->height);
973}
974
Akinobu Mitac2cae892018-05-06 10:19:23 -0400975static int ov772x_edgectrl(struct ov772x_priv *priv)
976{
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400977 struct regmap *regmap = priv->regmap;
Akinobu Mitac2cae892018-05-06 10:19:23 -0400978 int ret;
979
980 if (!priv->info)
981 return 0;
982
983 if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) {
984 /*
985 * Manual Edge Control Mode.
986 *
987 * Edge auto strength bit is set by default.
988 * Remove it when manual mode.
989 */
990
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400991 ret = regmap_update_bits(regmap, DSPAUTO, EDGE_ACTRL, 0x00);
Akinobu Mitac2cae892018-05-06 10:19:23 -0400992 if (ret < 0)
993 return ret;
994
Akinobu Mita5bbf3222018-07-16 11:47:49 -0400995 ret = regmap_update_bits(regmap, EDGE_TRSHLD,
996 OV772X_EDGE_THRESHOLD_MASK,
997 priv->info->edgectrl.threshold);
Akinobu Mitac2cae892018-05-06 10:19:23 -0400998 if (ret < 0)
999 return ret;
1000
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001001 ret = regmap_update_bits(regmap, EDGE_STRNGT,
1002 OV772X_EDGE_STRENGTH_MASK,
1003 priv->info->edgectrl.strength);
Akinobu Mitac2cae892018-05-06 10:19:23 -04001004 if (ret < 0)
1005 return ret;
1006
1007 } else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) {
1008 /*
1009 * Auto Edge Control Mode.
1010 *
1011 * Set upper and lower limit.
1012 */
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001013 ret = regmap_update_bits(regmap, EDGE_UPPER,
1014 OV772X_EDGE_UPPER_MASK,
1015 priv->info->edgectrl.upper);
Akinobu Mitac2cae892018-05-06 10:19:23 -04001016 if (ret < 0)
1017 return ret;
1018
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001019 ret = regmap_update_bits(regmap, EDGE_LOWER,
1020 OV772X_EDGE_LOWER_MASK,
1021 priv->info->edgectrl.lower);
Akinobu Mitac2cae892018-05-06 10:19:23 -04001022 if (ret < 0)
1023 return ret;
1024 }
1025
1026 return 0;
1027}
1028
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001029static int ov772x_set_params(struct ov772x_priv *priv,
1030 const struct ov772x_color_format *cfmt,
1031 const struct ov772x_win_size *win)
1032{
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001033 int ret;
1034 u8 val;
1035
Jacopo Mondi2a2f21e2018-03-02 09:46:39 -05001036 /* Reset hardware. */
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001037 ov772x_reset(priv);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001038
Jacopo Mondi2a2f21e2018-03-02 09:46:39 -05001039 /* Edge Ctrl. */
Akinobu Mitac2cae892018-05-06 10:19:23 -04001040 ret = ov772x_edgectrl(priv);
1041 if (ret < 0)
1042 return ret;
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001043
Jacopo Mondi2a2f21e2018-03-02 09:46:39 -05001044 /* Format and window size. */
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001045 ret = regmap_write(priv->regmap, HSTART, win->rect.left >> 2);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001046 if (ret < 0)
1047 goto ov772x_set_fmt_error;
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001048 ret = regmap_write(priv->regmap, HSIZE, win->rect.width >> 2);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001049 if (ret < 0)
1050 goto ov772x_set_fmt_error;
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001051 ret = regmap_write(priv->regmap, VSTART, win->rect.top >> 1);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001052 if (ret < 0)
1053 goto ov772x_set_fmt_error;
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001054 ret = regmap_write(priv->regmap, VSIZE, win->rect.height >> 1);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001055 if (ret < 0)
1056 goto ov772x_set_fmt_error;
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001057 ret = regmap_write(priv->regmap, HOUTSIZE, win->rect.width >> 2);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001058 if (ret < 0)
1059 goto ov772x_set_fmt_error;
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001060 ret = regmap_write(priv->regmap, VOUTSIZE, win->rect.height >> 1);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001061 if (ret < 0)
1062 goto ov772x_set_fmt_error;
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001063 ret = regmap_write(priv->regmap, HREF,
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001064 ((win->rect.top & 1) << HREF_VSTART_SHIFT) |
1065 ((win->rect.left & 3) << HREF_HSTART_SHIFT) |
1066 ((win->rect.height & 1) << HREF_VSIZE_SHIFT) |
1067 ((win->rect.width & 3) << HREF_HSIZE_SHIFT));
1068 if (ret < 0)
1069 goto ov772x_set_fmt_error;
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001070 ret = regmap_write(priv->regmap, EXHCH,
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001071 ((win->rect.height & 1) << EXHCH_VSIZE_SHIFT) |
1072 ((win->rect.width & 3) << EXHCH_HSIZE_SHIFT));
1073 if (ret < 0)
1074 goto ov772x_set_fmt_error;
1075
Jacopo Mondi2a2f21e2018-03-02 09:46:39 -05001076 /* Set DSP_CTRL3. */
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001077 val = cfmt->dsp3;
1078 if (val) {
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001079 ret = regmap_update_bits(priv->regmap, DSP_CTRL3, UV_MASK, val);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001080 if (ret < 0)
1081 goto ov772x_set_fmt_error;
1082 }
1083
1084 /* DSP_CTRL4: AEC reference point and DSP output format. */
1085 if (cfmt->dsp4) {
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001086 ret = regmap_write(priv->regmap, DSP_CTRL4, cfmt->dsp4);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001087 if (ret < 0)
1088 goto ov772x_set_fmt_error;
1089 }
1090
Jacopo Mondi2a2f21e2018-03-02 09:46:39 -05001091 /* Set COM3. */
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001092 val = cfmt->com3;
Akinobu Mitac2cae892018-05-06 10:19:23 -04001093 if (priv->info && (priv->info->flags & OV772X_FLAG_VFLIP))
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001094 val |= VFLIP_IMG;
Akinobu Mitac2cae892018-05-06 10:19:23 -04001095 if (priv->info && (priv->info->flags & OV772X_FLAG_HFLIP))
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001096 val |= HFLIP_IMG;
Akinobu Mita09e620c2018-05-06 10:19:26 -04001097 if (priv->vflip_ctrl->val)
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001098 val ^= VFLIP_IMG;
Akinobu Mita09e620c2018-05-06 10:19:26 -04001099 if (priv->hflip_ctrl->val)
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001100 val ^= HFLIP_IMG;
1101
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001102 ret = regmap_update_bits(priv->regmap, COM3, SWAP_MASK | IMG_MASK, val);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001103 if (ret < 0)
1104 goto ov772x_set_fmt_error;
1105
1106 /* COM7: Sensor resolution and output format control. */
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001107 ret = regmap_write(priv->regmap, COM7, win->com7_bit | cfmt->com7);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001108 if (ret < 0)
1109 goto ov772x_set_fmt_error;
1110
Jacopo Mondi35089492018-02-21 12:48:01 -05001111 /* COM4, CLKRC: Set pixel clock and framerate. */
Akinobu Mita80dc2a42018-05-06 10:19:25 -04001112 ret = ov772x_set_frame_rate(priv, priv->fps, cfmt, win);
Jacopo Mondi35089492018-02-21 12:48:01 -05001113 if (ret < 0)
1114 goto ov772x_set_fmt_error;
1115
Jacopo Mondi2a2f21e2018-03-02 09:46:39 -05001116 /* Set COM8. */
Akinobu Mita09e620c2018-05-06 10:19:26 -04001117 if (priv->band_filter_ctrl->val) {
1118 unsigned short band_filter = priv->band_filter_ctrl->val;
1119
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001120 ret = regmap_update_bits(priv->regmap, COM8,
1121 BNDF_ON_OFF, BNDF_ON_OFF);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001122 if (!ret)
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001123 ret = regmap_update_bits(priv->regmap, BDBASE,
1124 0xff, 256 - band_filter);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001125 if (ret < 0)
1126 goto ov772x_set_fmt_error;
1127 }
1128
1129 return ret;
1130
1131ov772x_set_fmt_error:
1132
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001133 ov772x_reset(priv);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001134
1135 return ret;
1136}
1137
1138static int ov772x_get_selection(struct v4l2_subdev *sd,
Mauro Carvalho Chehab054d8832018-02-26 09:23:32 -05001139 struct v4l2_subdev_pad_config *cfg,
Jacopo Mondieee34d82018-03-02 09:46:38 -05001140 struct v4l2_subdev_selection *sel)
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001141{
Jacopo Mondi762c2812018-02-21 12:48:00 -05001142 struct ov772x_priv *priv = to_ov772x(sd);
1143
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001144 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1145 return -EINVAL;
1146
1147 sel->r.left = 0;
1148 sel->r.top = 0;
1149 switch (sel->target) {
1150 case V4L2_SEL_TGT_CROP_BOUNDS:
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001151 case V4L2_SEL_TGT_CROP:
Jacopo Mondi762c2812018-02-21 12:48:00 -05001152 sel->r.width = priv->win->rect.width;
1153 sel->r.height = priv->win->rect.height;
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001154 return 0;
1155 default:
1156 return -EINVAL;
1157 }
1158}
1159
1160static int ov772x_get_fmt(struct v4l2_subdev *sd,
Mauro Carvalho Chehab054d8832018-02-26 09:23:32 -05001161 struct v4l2_subdev_pad_config *cfg,
Jacopo Mondieee34d82018-03-02 09:46:38 -05001162 struct v4l2_subdev_format *format)
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001163{
1164 struct v4l2_mbus_framefmt *mf = &format->format;
1165 struct ov772x_priv *priv = to_ov772x(sd);
1166
1167 if (format->pad)
1168 return -EINVAL;
1169
1170 mf->width = priv->win->rect.width;
1171 mf->height = priv->win->rect.height;
1172 mf->code = priv->cfmt->code;
1173 mf->colorspace = priv->cfmt->colorspace;
1174 mf->field = V4L2_FIELD_NONE;
1175
1176 return 0;
1177}
1178
1179static int ov772x_set_fmt(struct v4l2_subdev *sd,
Mauro Carvalho Chehab054d8832018-02-26 09:23:32 -05001180 struct v4l2_subdev_pad_config *cfg,
Jacopo Mondieee34d82018-03-02 09:46:38 -05001181 struct v4l2_subdev_format *format)
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001182{
1183 struct ov772x_priv *priv = to_ov772x(sd);
1184 struct v4l2_mbus_framefmt *mf = &format->format;
1185 const struct ov772x_color_format *cfmt;
1186 const struct ov772x_win_size *win;
Akinobu Mita95f5a452018-05-06 10:19:27 -04001187 int ret = 0;
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001188
1189 if (format->pad)
1190 return -EINVAL;
1191
1192 ov772x_select_params(mf, &cfmt, &win);
1193
1194 mf->code = cfmt->code;
1195 mf->width = win->rect.width;
1196 mf->height = win->rect.height;
1197 mf->field = V4L2_FIELD_NONE;
1198 mf->colorspace = cfmt->colorspace;
Jacopo Mondi762c2812018-02-21 12:48:00 -05001199 mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
1200 mf->quantization = V4L2_QUANTIZATION_DEFAULT;
1201 mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001202
1203 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1204 cfg->try_fmt = *mf;
1205 return 0;
1206 }
1207
Akinobu Mita95f5a452018-05-06 10:19:27 -04001208 mutex_lock(&priv->lock);
Akinobu Mita7b9998c2018-05-06 10:19:28 -04001209
1210 if (priv->streaming) {
1211 ret = -EBUSY;
1212 goto error;
1213 }
1214
Akinobu Mita95f5a452018-05-06 10:19:27 -04001215 /*
1216 * If the device is not powered up by the host driver do
1217 * not apply any changes to H/W at this time. Instead
1218 * the format will be restored right after power-up.
1219 */
1220 if (priv->power_count > 0) {
1221 ret = ov772x_set_params(priv, cfmt, win);
1222 if (ret < 0)
1223 goto error;
1224 }
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001225 priv->win = win;
1226 priv->cfmt = cfmt;
Jacopo Mondie0853a42018-03-02 09:46:40 -05001227
Akinobu Mita95f5a452018-05-06 10:19:27 -04001228error:
1229 mutex_unlock(&priv->lock);
1230
1231 return ret;
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001232}
1233
1234static int ov772x_video_probe(struct ov772x_priv *priv)
1235{
1236 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
Akinobu Mita30f3b172018-05-06 10:19:19 -04001237 int pid, ver, midh, midl;
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001238 const char *devname;
1239 int ret;
1240
Akinobu Mita95f5a452018-05-06 10:19:27 -04001241 ret = ov772x_power_on(priv);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001242 if (ret < 0)
1243 return ret;
1244
Jacopo Mondi2a2f21e2018-03-02 09:46:39 -05001245 /* Check and show product ID and manufacturer ID. */
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001246 ret = regmap_read(priv->regmap, PID, &pid);
1247 if (ret < 0)
1248 return ret;
1249 ret = regmap_read(priv->regmap, VER, &ver);
1250 if (ret < 0)
1251 return ret;
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001252
1253 switch (VERSION(pid, ver)) {
1254 case OV7720:
1255 devname = "ov7720";
1256 break;
1257 case OV7725:
1258 devname = "ov7725";
1259 break;
1260 default:
1261 dev_err(&client->dev,
1262 "Product ID error %x:%x\n", pid, ver);
1263 ret = -ENODEV;
1264 goto done;
1265 }
1266
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001267 ret = regmap_read(priv->regmap, MIDH, &midh);
1268 if (ret < 0)
1269 return ret;
1270 ret = regmap_read(priv->regmap, MIDL, &midl);
1271 if (ret < 0)
1272 return ret;
Akinobu Mita30f3b172018-05-06 10:19:19 -04001273
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001274 dev_info(&client->dev,
1275 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
Akinobu Mita30f3b172018-05-06 10:19:19 -04001276 devname, pid, ver, midh, midl);
1277
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001278 ret = v4l2_ctrl_handler_setup(&priv->hdl);
1279
1280done:
Akinobu Mita95f5a452018-05-06 10:19:27 -04001281 ov772x_power_off(priv);
Jacopo Mondie0853a42018-03-02 09:46:40 -05001282
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001283 return ret;
1284}
1285
1286static const struct v4l2_ctrl_ops ov772x_ctrl_ops = {
1287 .s_ctrl = ov772x_s_ctrl,
1288};
1289
1290static const struct v4l2_subdev_core_ops ov772x_subdev_core_ops = {
Akinobu Mitabedfcd42018-11-12 11:00:54 -05001291 .log_status = v4l2_ctrl_subdev_log_status,
1292 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1293 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001294#ifdef CONFIG_VIDEO_ADV_DEBUG
1295 .g_register = ov772x_g_register,
1296 .s_register = ov772x_s_register,
1297#endif
1298 .s_power = ov772x_s_power,
1299};
1300
Jacopo Mondi35089492018-02-21 12:48:01 -05001301static int ov772x_enum_frame_interval(struct v4l2_subdev *sd,
1302 struct v4l2_subdev_pad_config *cfg,
1303 struct v4l2_subdev_frame_interval_enum *fie)
1304{
1305 if (fie->pad || fie->index >= ARRAY_SIZE(ov772x_frame_intervals))
1306 return -EINVAL;
1307
1308 if (fie->width != VGA_WIDTH && fie->width != QVGA_WIDTH)
1309 return -EINVAL;
1310 if (fie->height != VGA_HEIGHT && fie->height != QVGA_HEIGHT)
1311 return -EINVAL;
1312
1313 fie->interval.numerator = 1;
1314 fie->interval.denominator = ov772x_frame_intervals[fie->index];
1315
1316 return 0;
1317}
1318
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001319static int ov772x_enum_mbus_code(struct v4l2_subdev *sd,
Mauro Carvalho Chehab054d8832018-02-26 09:23:32 -05001320 struct v4l2_subdev_pad_config *cfg,
Jacopo Mondieee34d82018-03-02 09:46:38 -05001321 struct v4l2_subdev_mbus_code_enum *code)
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001322{
1323 if (code->pad || code->index >= ARRAY_SIZE(ov772x_cfmts))
1324 return -EINVAL;
1325
1326 code->code = ov772x_cfmts[code->index].code;
Jacopo Mondie0853a42018-03-02 09:46:40 -05001327
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001328 return 0;
1329}
1330
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001331static const struct v4l2_subdev_video_ops ov772x_subdev_video_ops = {
Jacopo Mondi35089492018-02-21 12:48:01 -05001332 .s_stream = ov772x_s_stream,
1333 .s_frame_interval = ov772x_s_frame_interval,
1334 .g_frame_interval = ov772x_g_frame_interval,
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001335};
1336
1337static const struct v4l2_subdev_pad_ops ov772x_subdev_pad_ops = {
Jacopo Mondi35089492018-02-21 12:48:01 -05001338 .enum_frame_interval = ov772x_enum_frame_interval,
1339 .enum_mbus_code = ov772x_enum_mbus_code,
1340 .get_selection = ov772x_get_selection,
1341 .get_fmt = ov772x_get_fmt,
1342 .set_fmt = ov772x_set_fmt,
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001343};
1344
1345static const struct v4l2_subdev_ops ov772x_subdev_ops = {
1346 .core = &ov772x_subdev_core_ops,
1347 .video = &ov772x_subdev_video_ops,
1348 .pad = &ov772x_subdev_pad_ops,
1349};
1350
1351/*
1352 * i2c_driver function
1353 */
1354
Kieran Binghame6714992019-07-10 18:51:49 -03001355static int ov772x_probe(struct i2c_client *client)
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001356{
1357 struct ov772x_priv *priv;
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001358 int ret;
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001359 static const struct regmap_config ov772x_regmap_config = {
1360 .reg_bits = 8,
1361 .val_bits = 8,
1362 .max_register = DSPAUTO,
1363 };
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001364
Akinobu Mitac2cae892018-05-06 10:19:23 -04001365 if (!client->dev.of_node && !client->dev.platform_data) {
1366 dev_err(&client->dev,
1367 "Missing ov772x platform data for non-DT device\n");
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001368 return -EINVAL;
1369 }
1370
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001371 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1372 if (!priv)
1373 return -ENOMEM;
1374
Akinobu Mita5bbf3222018-07-16 11:47:49 -04001375 priv->regmap = devm_regmap_init_sccb(client, &ov772x_regmap_config);
1376 if (IS_ERR(priv->regmap)) {
1377 dev_err(&client->dev, "Failed to allocate register map\n");
1378 return PTR_ERR(priv->regmap);
1379 }
1380
Jacopo Mondi762c2812018-02-21 12:48:00 -05001381 priv->info = client->dev.platform_data;
Akinobu Mita34af7d92018-05-06 10:19:24 -04001382 mutex_init(&priv->lock);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001383
1384 v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops);
Akinobu Mitabedfcd42018-11-12 11:00:54 -05001385 priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1386 V4L2_SUBDEV_FL_HAS_EVENTS;
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001387 v4l2_ctrl_handler_init(&priv->hdl, 3);
Akinobu Mita95f5a452018-05-06 10:19:27 -04001388 /* Use our mutex for the controls */
1389 priv->hdl.lock = &priv->lock;
Akinobu Mita09e620c2018-05-06 10:19:26 -04001390 priv->vflip_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1391 V4L2_CID_VFLIP, 0, 1, 1, 0);
1392 priv->hflip_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1393 V4L2_CID_HFLIP, 0, 1, 1, 0);
1394 priv->band_filter_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1395 V4L2_CID_BAND_STOP_FILTER,
1396 0, 256, 1, 0);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001397 priv->subdev.ctrl_handler = &priv->hdl;
Akinobu Mita34af7d92018-05-06 10:19:24 -04001398 if (priv->hdl.error) {
1399 ret = priv->hdl.error;
1400 goto error_mutex_destroy;
1401 }
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001402
Akinobu Mita89ce93f2018-05-06 10:19:22 -04001403 priv->clk = clk_get(&client->dev, NULL);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001404 if (IS_ERR(priv->clk)) {
Jacopo Mondi762c2812018-02-21 12:48:00 -05001405 dev_err(&client->dev, "Unable to get xclk clock\n");
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001406 ret = PTR_ERR(priv->clk);
Jacopo Mondi762c2812018-02-21 12:48:00 -05001407 goto error_ctrl_free;
1408 }
1409
Akinobu Mita40519d52018-05-06 10:19:21 -04001410 priv->pwdn_gpio = gpiod_get_optional(&client->dev, "powerdown",
Jacopo Mondi762c2812018-02-21 12:48:00 -05001411 GPIOD_OUT_LOW);
1412 if (IS_ERR(priv->pwdn_gpio)) {
Akinobu Mita40519d52018-05-06 10:19:21 -04001413 dev_info(&client->dev, "Unable to get GPIO \"powerdown\"");
Jacopo Mondi762c2812018-02-21 12:48:00 -05001414 ret = PTR_ERR(priv->pwdn_gpio);
1415 goto error_clk_put;
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001416 }
1417
1418 ret = ov772x_video_probe(priv);
Jacopo Mondi762c2812018-02-21 12:48:00 -05001419 if (ret < 0)
1420 goto error_gpio_put;
1421
Akinobu Mita4b610d62018-05-06 10:19:20 -04001422#ifdef CONFIG_MEDIA_CONTROLLER
1423 priv->pad.flags = MEDIA_PAD_FL_SOURCE;
1424 priv->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1425 ret = media_entity_pads_init(&priv->subdev.entity, 1, &priv->pad);
1426 if (ret < 0)
1427 goto error_gpio_put;
1428#endif
1429
Jacopo Mondi762c2812018-02-21 12:48:00 -05001430 priv->cfmt = &ov772x_cfmts[0];
1431 priv->win = &ov772x_win_sizes[0];
Jacopo Mondi35089492018-02-21 12:48:01 -05001432 priv->fps = 15;
Jacopo Mondi762c2812018-02-21 12:48:00 -05001433
1434 ret = v4l2_async_register_subdev(&priv->subdev);
1435 if (ret)
Akinobu Mita4b610d62018-05-06 10:19:20 -04001436 goto error_entity_cleanup;
Jacopo Mondi762c2812018-02-21 12:48:00 -05001437
1438 return 0;
1439
Akinobu Mita4b610d62018-05-06 10:19:20 -04001440error_entity_cleanup:
1441 media_entity_cleanup(&priv->subdev.entity);
Jacopo Mondi762c2812018-02-21 12:48:00 -05001442error_gpio_put:
1443 if (priv->pwdn_gpio)
1444 gpiod_put(priv->pwdn_gpio);
1445error_clk_put:
1446 clk_put(priv->clk);
1447error_ctrl_free:
1448 v4l2_ctrl_handler_free(&priv->hdl);
Akinobu Mita34af7d92018-05-06 10:19:24 -04001449error_mutex_destroy:
1450 mutex_destroy(&priv->lock);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001451
1452 return ret;
1453}
1454
1455static int ov772x_remove(struct i2c_client *client)
1456{
1457 struct ov772x_priv *priv = to_ov772x(i2c_get_clientdata(client));
1458
Akinobu Mita4b610d62018-05-06 10:19:20 -04001459 media_entity_cleanup(&priv->subdev.entity);
Jacopo Mondi762c2812018-02-21 12:48:00 -05001460 clk_put(priv->clk);
1461 if (priv->pwdn_gpio)
1462 gpiod_put(priv->pwdn_gpio);
Jacopo Mondi27a48fe2018-03-02 09:46:43 -05001463 v4l2_async_unregister_subdev(&priv->subdev);
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001464 v4l2_ctrl_handler_free(&priv->hdl);
Akinobu Mita34af7d92018-05-06 10:19:24 -04001465 mutex_destroy(&priv->lock);
Jacopo Mondie0853a42018-03-02 09:46:40 -05001466
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001467 return 0;
1468}
1469
1470static const struct i2c_device_id ov772x_id[] = {
1471 { "ov772x", 0 },
1472 { }
1473};
1474MODULE_DEVICE_TABLE(i2c, ov772x_id);
1475
Akinobu Mitac2cae892018-05-06 10:19:23 -04001476static const struct of_device_id ov772x_of_match[] = {
1477 { .compatible = "ovti,ov7725", },
1478 { .compatible = "ovti,ov7720", },
1479 { /* sentinel */ },
1480};
1481MODULE_DEVICE_TABLE(of, ov772x_of_match);
1482
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001483static struct i2c_driver ov772x_i2c_driver = {
1484 .driver = {
1485 .name = "ov772x",
Akinobu Mitac2cae892018-05-06 10:19:23 -04001486 .of_match_table = ov772x_of_match,
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001487 },
Kieran Binghame6714992019-07-10 18:51:49 -03001488 .probe_new = ov772x_probe,
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001489 .remove = ov772x_remove,
1490 .id_table = ov772x_id,
1491};
1492
1493module_i2c_driver(ov772x_i2c_driver);
1494
Jacopo Mondi762c2812018-02-21 12:48:00 -05001495MODULE_DESCRIPTION("V4L2 driver for OV772x image sensor");
Jacopo Mondi1112bab2018-02-21 12:47:59 -05001496MODULE_AUTHOR("Kuninori Morimoto");
1497MODULE_LICENSE("GPL v2");