blob: a688f7f87829f760c9fdee9008f6ca365e342dd3 [file] [log] [blame]
Greg Kroah-Hartman5fd54ac2017-11-03 11:28:30 +01001// SPDX-License-Identifier: GPL-2.0
Felipe Balbi550a7372008-07-24 12:27:36 +03002/*
3 * MUSB OTG driver - support for Mentor's DMA controller
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2007 by Texas Instruments
Felipe Balbi550a7372008-07-24 12:27:36 +03007 */
8#include <linux/device.h>
9#include <linux/interrupt.h>
10#include <linux/platform_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090011#include <linux/slab.h>
Felipe Balbi550a7372008-07-24 12:27:36 +030012#include "musb_core.h"
Bin Liu78fba982018-05-21 08:42:09 -050013
14#define MUSB_HSDMA_BASE 0x200
15#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
16#define MUSB_HSDMA_CONTROL 0x4
17#define MUSB_HSDMA_ADDRESS 0x8
18#define MUSB_HSDMA_COUNT 0xc
19
20#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
21 (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
22
23#define musb_read_hsdma_addr(mbase, bchannel) \
24 musb_readl(mbase, \
25 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
26
27#define musb_write_hsdma_addr(mbase, bchannel, addr) \
28 musb_writel(mbase, \
29 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
30 addr)
31
32#define musb_read_hsdma_count(mbase, bchannel) \
33 musb_readl(mbase, \
34 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
35
36#define musb_write_hsdma_count(mbase, bchannel, len) \
37 musb_writel(mbase, \
38 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
39 len)
40/* control register (16-bit): */
41#define MUSB_HSDMA_ENABLE_SHIFT 0
42#define MUSB_HSDMA_TRANSMIT_SHIFT 1
43#define MUSB_HSDMA_MODE1_SHIFT 2
44#define MUSB_HSDMA_IRQENABLE_SHIFT 3
45#define MUSB_HSDMA_ENDPOINT_SHIFT 4
46#define MUSB_HSDMA_BUSERROR_SHIFT 8
47#define MUSB_HSDMA_BURSTMODE_SHIFT 9
48#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
49#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
50#define MUSB_HSDMA_BURSTMODE_INCR4 1
51#define MUSB_HSDMA_BURSTMODE_INCR8 2
52#define MUSB_HSDMA_BURSTMODE_INCR16 3
53
54#define MUSB_HSDMA_CHANNELS 8
55
56struct musb_dma_controller;
57
58struct musb_dma_channel {
59 struct dma_channel channel;
60 struct musb_dma_controller *controller;
61 u32 start_addr;
62 u32 len;
63 u16 max_packet_sz;
64 u8 idx;
65 u8 epnum;
66 u8 transmit;
67};
68
69struct musb_dma_controller {
70 struct dma_controller controller;
71 struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
72 void *private_data;
73 void __iomem *base;
74 u8 channel_count;
75 u8 used_channels;
76 int irq;
77};
Felipe Balbi550a7372008-07-24 12:27:36 +030078
Felipe Balbi458e6a52008-09-11 11:53:24 +030079static void dma_channel_release(struct dma_channel *channel);
Felipe Balbi550a7372008-07-24 12:27:36 +030080
Sebastian Andrzej Siewior66c01882013-06-19 17:38:11 +020081static void dma_controller_stop(struct musb_dma_controller *controller)
Felipe Balbi550a7372008-07-24 12:27:36 +030082{
Felipe Balbi458e6a52008-09-11 11:53:24 +030083 struct musb *musb = controller->private_data;
84 struct dma_channel *channel;
85 u8 bit;
Felipe Balbi550a7372008-07-24 12:27:36 +030086
Felipe Balbi458e6a52008-09-11 11:53:24 +030087 if (controller->used_channels != 0) {
Felipe Balbi550a7372008-07-24 12:27:36 +030088 dev_err(musb->controller,
89 "Stopping DMA controller while channel active\n");
90
Felipe Balbi458e6a52008-09-11 11:53:24 +030091 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
92 if (controller->used_channels & (1 << bit)) {
93 channel = &controller->channel[bit].channel;
94 dma_channel_release(channel);
Felipe Balbi550a7372008-07-24 12:27:36 +030095
Felipe Balbi458e6a52008-09-11 11:53:24 +030096 if (!controller->used_channels)
Felipe Balbi550a7372008-07-24 12:27:36 +030097 break;
98 }
99 }
100 }
Felipe Balbi550a7372008-07-24 12:27:36 +0300101}
102
103static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
104 struct musb_hw_ep *hw_ep, u8 transmit)
105{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300106 struct musb_dma_controller *controller = container_of(c,
107 struct musb_dma_controller, controller);
108 struct musb_dma_channel *musb_channel = NULL;
109 struct dma_channel *channel = NULL;
110 u8 bit;
Felipe Balbi550a7372008-07-24 12:27:36 +0300111
Felipe Balbi458e6a52008-09-11 11:53:24 +0300112 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
113 if (!(controller->used_channels & (1 << bit))) {
114 controller->used_channels |= (1 << bit);
115 musb_channel = &(controller->channel[bit]);
116 musb_channel->controller = controller;
117 musb_channel->idx = bit;
118 musb_channel->epnum = hw_ep->epnum;
119 musb_channel->transmit = transmit;
120 channel = &(musb_channel->channel);
121 channel->private_data = musb_channel;
122 channel->status = MUSB_DMA_STATUS_FREE;
Anil Shetty6587cc02010-09-24 13:44:05 +0300123 channel->max_len = 0x100000;
Felipe Balbi550a7372008-07-24 12:27:36 +0300124 /* Tx => mode 1; Rx => mode 0 */
Felipe Balbi458e6a52008-09-11 11:53:24 +0300125 channel->desired_mode = transmit;
126 channel->actual_len = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300127 break;
128 }
129 }
Felipe Balbi458e6a52008-09-11 11:53:24 +0300130
131 return channel;
Felipe Balbi550a7372008-07-24 12:27:36 +0300132}
133
Felipe Balbi458e6a52008-09-11 11:53:24 +0300134static void dma_channel_release(struct dma_channel *channel)
Felipe Balbi550a7372008-07-24 12:27:36 +0300135{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300136 struct musb_dma_channel *musb_channel = channel->private_data;
Felipe Balbi550a7372008-07-24 12:27:36 +0300137
Felipe Balbi458e6a52008-09-11 11:53:24 +0300138 channel->actual_len = 0;
139 musb_channel->start_addr = 0;
140 musb_channel->len = 0;
Felipe Balbi550a7372008-07-24 12:27:36 +0300141
Felipe Balbi458e6a52008-09-11 11:53:24 +0300142 musb_channel->controller->used_channels &=
143 ~(1 << musb_channel->idx);
Felipe Balbi550a7372008-07-24 12:27:36 +0300144
Felipe Balbi458e6a52008-09-11 11:53:24 +0300145 channel->status = MUSB_DMA_STATUS_UNKNOWN;
Felipe Balbi550a7372008-07-24 12:27:36 +0300146}
147
Felipe Balbi458e6a52008-09-11 11:53:24 +0300148static void configure_channel(struct dma_channel *channel,
Felipe Balbi550a7372008-07-24 12:27:36 +0300149 u16 packet_sz, u8 mode,
150 dma_addr_t dma_addr, u32 len)
151{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300152 struct musb_dma_channel *musb_channel = channel->private_data;
153 struct musb_dma_controller *controller = musb_channel->controller;
Felipe Balbi5c8a86e2011-05-11 12:44:08 +0300154 struct musb *musb = controller->private_data;
Felipe Balbi458e6a52008-09-11 11:53:24 +0300155 void __iomem *mbase = controller->base;
156 u8 bchannel = musb_channel->idx;
Felipe Balbi550a7372008-07-24 12:27:36 +0300157 u16 csr = 0;
158
Bin Liub99d3652016-06-30 12:12:22 -0500159 musb_dbg(musb, "%p, pkt_sz %d, addr %pad, len %d, mode %d",
Arnd Bergmann3ec08dd2016-01-28 17:23:14 +0100160 channel, packet_sz, &dma_addr, len, mode);
Felipe Balbi550a7372008-07-24 12:27:36 +0300161
162 if (mode) {
163 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
164 BUG_ON(len < packet_sz);
Felipe Balbi550a7372008-07-24 12:27:36 +0300165 }
Hema HKc0f1f8e2010-06-24 23:07:09 +0530166 csr |= MUSB_HSDMA_BURSTMODE_INCR16
167 << MUSB_HSDMA_BURSTMODE_SHIFT;
Felipe Balbi550a7372008-07-24 12:27:36 +0300168
Felipe Balbi458e6a52008-09-11 11:53:24 +0300169 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
Felipe Balbi550a7372008-07-24 12:27:36 +0300170 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
171 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
Felipe Balbi458e6a52008-09-11 11:53:24 +0300172 | (musb_channel->transmit
Felipe Balbi550a7372008-07-24 12:27:36 +0300173 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
174 : 0);
175
176 /* address/count */
Bryan Wu6995eb62008-12-02 21:33:47 +0200177 musb_write_hsdma_addr(mbase, bchannel, dma_addr);
178 musb_write_hsdma_count(mbase, bchannel, len);
Felipe Balbi550a7372008-07-24 12:27:36 +0300179
180 /* control (this should start things) */
181 musb_writew(mbase,
Felipe Balbi458e6a52008-09-11 11:53:24 +0300182 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
Felipe Balbi550a7372008-07-24 12:27:36 +0300183 csr);
184}
185
Felipe Balbi458e6a52008-09-11 11:53:24 +0300186static int dma_channel_program(struct dma_channel *channel,
Felipe Balbi550a7372008-07-24 12:27:36 +0300187 u16 packet_sz, u8 mode,
188 dma_addr_t dma_addr, u32 len)
189{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300190 struct musb_dma_channel *musb_channel = channel->private_data;
Anand Gadiyar6e16edf2010-11-08 00:20:30 -0600191 struct musb_dma_controller *controller = musb_channel->controller;
192 struct musb *musb = controller->private_data;
Felipe Balbi550a7372008-07-24 12:27:36 +0300193
Bin Liub99d3652016-06-30 12:12:22 -0500194 musb_dbg(musb, "ep%d-%s pkt_sz %d, dma_addr %pad length %d, mode %d",
Felipe Balbi458e6a52008-09-11 11:53:24 +0300195 musb_channel->epnum,
196 musb_channel->transmit ? "Tx" : "Rx",
Arnd Bergmann3ec08dd2016-01-28 17:23:14 +0100197 packet_sz, &dma_addr, len, mode);
Felipe Balbi550a7372008-07-24 12:27:36 +0300198
Felipe Balbi458e6a52008-09-11 11:53:24 +0300199 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
200 channel->status == MUSB_DMA_STATUS_BUSY);
Felipe Balbi550a7372008-07-24 12:27:36 +0300201
Anand Gadiyar6e16edf2010-11-08 00:20:30 -0600202 /*
203 * The DMA engine in RTL1.8 and above cannot handle
204 * DMA addresses that are not aligned to a 4 byte boundary.
205 * It ends up masking the last two bits of the address
206 * programmed in DMA_ADDR.
207 *
208 * Fail such DMA transfers, so that the backup PIO mode
209 * can carry out the transfer
210 */
211 if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
212 return false;
213
Felipe Balbi458e6a52008-09-11 11:53:24 +0300214 channel->actual_len = 0;
215 musb_channel->start_addr = dma_addr;
216 musb_channel->len = len;
217 musb_channel->max_packet_sz = packet_sz;
218 channel->status = MUSB_DMA_STATUS_BUSY;
Felipe Balbi550a7372008-07-24 12:27:36 +0300219
Anand Gadiyar8ca47c82010-07-08 16:34:55 +0530220 configure_channel(channel, packet_sz, mode, dma_addr, len);
Felipe Balbi550a7372008-07-24 12:27:36 +0300221
222 return true;
223}
224
Felipe Balbi458e6a52008-09-11 11:53:24 +0300225static int dma_channel_abort(struct dma_channel *channel)
Felipe Balbi550a7372008-07-24 12:27:36 +0300226{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300227 struct musb_dma_channel *musb_channel = channel->private_data;
228 void __iomem *mbase = musb_channel->controller->base;
Tony Lindgrend026e9c2014-11-24 11:05:03 -0800229 struct musb *musb = musb_channel->controller->private_data;
Felipe Balbi458e6a52008-09-11 11:53:24 +0300230
231 u8 bchannel = musb_channel->idx;
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700232 int offset;
Felipe Balbi550a7372008-07-24 12:27:36 +0300233 u16 csr;
234
Felipe Balbi458e6a52008-09-11 11:53:24 +0300235 if (channel->status == MUSB_DMA_STATUS_BUSY) {
236 if (musb_channel->transmit) {
Tony Lindgrend026e9c2014-11-24 11:05:03 -0800237 offset = musb->io.ep_offset(musb_channel->epnum,
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700238 MUSB_TXCSR);
Felipe Balbi550a7372008-07-24 12:27:36 +0300239
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700240 /*
241 * The programming guide says that we must clear
242 * the DMAENAB bit before the DMAMODE bit...
243 */
244 csr = musb_readw(mbase, offset);
245 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
246 musb_writew(mbase, offset, csr);
247 csr &= ~MUSB_TXCSR_DMAMODE;
248 musb_writew(mbase, offset, csr);
Felipe Balbi550a7372008-07-24 12:27:36 +0300249 } else {
Tony Lindgrend026e9c2014-11-24 11:05:03 -0800250 offset = musb->io.ep_offset(musb_channel->epnum,
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700251 MUSB_RXCSR);
252
253 csr = musb_readw(mbase, offset);
Felipe Balbi550a7372008-07-24 12:27:36 +0300254 csr &= ~(MUSB_RXCSR_AUTOCLEAR |
255 MUSB_RXCSR_DMAENAB |
256 MUSB_RXCSR_DMAMODE);
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700257 musb_writew(mbase, offset, csr);
Felipe Balbi550a7372008-07-24 12:27:36 +0300258 }
259
260 musb_writew(mbase,
Felipe Balbi458e6a52008-09-11 11:53:24 +0300261 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
Felipe Balbi550a7372008-07-24 12:27:36 +0300262 0);
Bryan Wu6995eb62008-12-02 21:33:47 +0200263 musb_write_hsdma_addr(mbase, bchannel, 0);
264 musb_write_hsdma_count(mbase, bchannel, 0);
Felipe Balbi458e6a52008-09-11 11:53:24 +0300265 channel->status = MUSB_DMA_STATUS_FREE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300266 }
Felipe Balbi458e6a52008-09-11 11:53:24 +0300267
Felipe Balbi550a7372008-07-24 12:27:36 +0300268 return 0;
269}
270
271static irqreturn_t dma_controller_irq(int irq, void *private_data)
272{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300273 struct musb_dma_controller *controller = private_data;
274 struct musb *musb = controller->private_data;
275 struct musb_dma_channel *musb_channel;
276 struct dma_channel *channel;
277
278 void __iomem *mbase = controller->base;
279
Felipe Balbi550a7372008-07-24 12:27:36 +0300280 irqreturn_t retval = IRQ_NONE;
Felipe Balbi458e6a52008-09-11 11:53:24 +0300281
Felipe Balbi550a7372008-07-24 12:27:36 +0300282 unsigned long flags;
283
Felipe Balbi458e6a52008-09-11 11:53:24 +0300284 u8 bchannel;
285 u8 int_hsdma;
286
Anand Gadiyarf933a0c2009-12-28 13:40:36 +0200287 u32 addr, count;
Felipe Balbi458e6a52008-09-11 11:53:24 +0300288 u16 csr;
289
Felipe Balbi550a7372008-07-24 12:27:36 +0300290 spin_lock_irqsave(&musb->lock, flags);
291
292 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
Felipe Balbi550a7372008-07-24 12:27:36 +0300293
Anand Gadiyarf933a0c2009-12-28 13:40:36 +0200294 if (!int_hsdma) {
Bin Liub99d3652016-06-30 12:12:22 -0500295 musb_dbg(musb, "spurious DMA irq");
Anand Gadiyarf933a0c2009-12-28 13:40:36 +0200296
297 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
298 musb_channel = (struct musb_dma_channel *)
299 &(controller->channel[bchannel]);
300 channel = &musb_channel->channel;
301 if (channel->status == MUSB_DMA_STATUS_BUSY) {
302 count = musb_read_hsdma_count(mbase, bchannel);
303
304 if (count == 0)
305 int_hsdma |= (1 << bchannel);
306 }
307 }
308
Bin Liub99d3652016-06-30 12:12:22 -0500309 musb_dbg(musb, "int_hsdma = 0x%x", int_hsdma);
Anand Gadiyarf933a0c2009-12-28 13:40:36 +0200310
311 if (!int_hsdma)
312 goto done;
313 }
314
Felipe Balbi458e6a52008-09-11 11:53:24 +0300315 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
316 if (int_hsdma & (1 << bchannel)) {
317 musb_channel = (struct musb_dma_channel *)
318 &(controller->channel[bchannel]);
319 channel = &musb_channel->channel;
Felipe Balbi550a7372008-07-24 12:27:36 +0300320
321 csr = musb_readw(mbase,
Felipe Balbi458e6a52008-09-11 11:53:24 +0300322 MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
Felipe Balbi550a7372008-07-24 12:27:36 +0300323 MUSB_HSDMA_CONTROL));
324
Felipe Balbi458e6a52008-09-11 11:53:24 +0300325 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
326 musb_channel->channel.status =
Felipe Balbi550a7372008-07-24 12:27:36 +0300327 MUSB_DMA_STATUS_BUS_ABORT;
Felipe Balbi458e6a52008-09-11 11:53:24 +0300328 } else {
Felipe Balbi550a7372008-07-24 12:27:36 +0300329 u8 devctl;
330
Bryan Wu6995eb62008-12-02 21:33:47 +0200331 addr = musb_read_hsdma_addr(mbase,
332 bchannel);
Felipe Balbi458e6a52008-09-11 11:53:24 +0300333 channel->actual_len = addr
334 - musb_channel->start_addr;
Felipe Balbi550a7372008-07-24 12:27:36 +0300335
Bin Liub99d3652016-06-30 12:12:22 -0500336 musb_dbg(musb, "ch %p, 0x%x -> 0x%x (%zu / %d) %s",
Felipe Balbi458e6a52008-09-11 11:53:24 +0300337 channel, musb_channel->start_addr,
338 addr, channel->actual_len,
339 musb_channel->len,
340 (channel->actual_len
341 < musb_channel->len) ?
Felipe Balbi550a7372008-07-24 12:27:36 +0300342 "=> reconfig 0" : "=> complete");
343
344 devctl = musb_readb(mbase, MUSB_DEVCTL);
345
Felipe Balbi458e6a52008-09-11 11:53:24 +0300346 channel->status = MUSB_DMA_STATUS_FREE;
Felipe Balbi550a7372008-07-24 12:27:36 +0300347
348 /* completed */
349 if ((devctl & MUSB_DEVCTL_HM)
Felipe Balbi458e6a52008-09-11 11:53:24 +0300350 && (musb_channel->transmit)
351 && ((channel->desired_mode == 0)
352 || (channel->actual_len &
353 (musb_channel->max_packet_sz - 1)))
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700354 ) {
355 u8 epnum = musb_channel->epnum;
Tony Lindgrend026e9c2014-11-24 11:05:03 -0800356 int offset = musb->io.ep_offset(epnum,
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700357 MUSB_TXCSR);
358 u16 txcsr;
359
360 /*
361 * The programming guide says that we
362 * must clear DMAENAB before DMAMODE.
363 */
364 musb_ep_select(mbase, epnum);
365 txcsr = musb_readw(mbase, offset);
366 txcsr &= ~(MUSB_TXCSR_DMAENAB
367 | MUSB_TXCSR_AUTOSET);
368 musb_writew(mbase, offset, txcsr);
Felipe Balbi550a7372008-07-24 12:27:36 +0300369 /* Send out the packet */
Sergei Shtylyovb6e434a2009-03-26 18:27:47 -0700370 txcsr &= ~MUSB_TXCSR_DMAMODE;
371 txcsr |= MUSB_TXCSR_TXPKTRDY;
372 musb_writew(mbase, offset, txcsr);
Felipe Balbi458e6a52008-09-11 11:53:24 +0300373 }
Sergei Shtylyovc7bbc052009-03-26 18:26:40 -0700374 musb_dma_completion(musb, musb_channel->epnum,
375 musb_channel->transmit);
Felipe Balbi550a7372008-07-24 12:27:36 +0300376 }
377 }
378 }
Bryan Wu6995eb62008-12-02 21:33:47 +0200379
Felipe Balbi550a7372008-07-24 12:27:36 +0300380 retval = IRQ_HANDLED;
381done:
382 spin_unlock_irqrestore(&musb->lock, flags);
383 return retval;
384}
385
Tony Lindgren7f6283e2015-05-01 12:29:28 -0700386void musbhs_dma_controller_destroy(struct dma_controller *c)
Felipe Balbi550a7372008-07-24 12:27:36 +0300387{
Felipe Balbi458e6a52008-09-11 11:53:24 +0300388 struct musb_dma_controller *controller = container_of(c,
389 struct musb_dma_controller, controller);
Felipe Balbi550a7372008-07-24 12:27:36 +0300390
Sebastian Andrzej Siewior66c01882013-06-19 17:38:11 +0200391 dma_controller_stop(controller);
392
Felipe Balbi550a7372008-07-24 12:27:36 +0300393 if (controller->irq)
394 free_irq(controller->irq, c);
395
396 kfree(controller);
397}
Tony Lindgren7f6283e2015-05-01 12:29:28 -0700398EXPORT_SYMBOL_GPL(musbhs_dma_controller_destroy);
Felipe Balbi550a7372008-07-24 12:27:36 +0300399
Tony Lindgren7f6283e2015-05-01 12:29:28 -0700400struct dma_controller *musbhs_dma_controller_create(struct musb *musb,
401 void __iomem *base)
Felipe Balbi550a7372008-07-24 12:27:36 +0300402{
403 struct musb_dma_controller *controller;
404 struct device *dev = musb->controller;
405 struct platform_device *pdev = to_platform_device(dev);
Hema Kalliguddifcf173e2010-09-29 11:26:39 -0500406 int irq = platform_get_irq_byname(pdev, "dma");
Felipe Balbi550a7372008-07-24 12:27:36 +0300407
Sergei Shtylyov7effdbd2012-08-20 22:34:46 +0400408 if (irq <= 0) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300409 dev_err(dev, "No DMA interrupt line!\n");
410 return NULL;
411 }
412
Felipe Balbi458e6a52008-09-11 11:53:24 +0300413 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
Felipe Balbi550a7372008-07-24 12:27:36 +0300414 if (!controller)
415 return NULL;
416
Felipe Balbi458e6a52008-09-11 11:53:24 +0300417 controller->channel_count = MUSB_HSDMA_CHANNELS;
418 controller->private_data = musb;
419 controller->base = base;
Felipe Balbi550a7372008-07-24 12:27:36 +0300420
Felipe Balbi458e6a52008-09-11 11:53:24 +0300421 controller->controller.channel_alloc = dma_channel_allocate;
422 controller->controller.channel_release = dma_channel_release;
423 controller->controller.channel_program = dma_channel_program;
424 controller->controller.channel_abort = dma_channel_abort;
Felipe Balbi550a7372008-07-24 12:27:36 +0300425
Yong Zhangb5dd18d2011-09-07 16:10:52 +0800426 if (request_irq(irq, dma_controller_irq, 0,
Kay Sievers427c4f32008-11-07 01:52:53 +0100427 dev_name(musb->controller), &controller->controller)) {
Felipe Balbi550a7372008-07-24 12:27:36 +0300428 dev_err(dev, "request_irq %d failed!\n", irq);
Tony Lindgren7f6283e2015-05-01 12:29:28 -0700429 musb_dma_controller_destroy(&controller->controller);
Felipe Balbi458e6a52008-09-11 11:53:24 +0300430
Felipe Balbi550a7372008-07-24 12:27:36 +0300431 return NULL;
432 }
433
434 controller->irq = irq;
435
Felipe Balbi458e6a52008-09-11 11:53:24 +0300436 return &controller->controller;
Felipe Balbi550a7372008-07-24 12:27:36 +0300437}
Tony Lindgren7f6283e2015-05-01 12:29:28 -0700438EXPORT_SYMBOL_GPL(musbhs_dma_controller_create);