Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Driver for Atmel AT32 and AT91 SPI Controllers |
| 3 | * |
| 4 | * Copyright (C) 2006 Atmel Corporation |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/clk.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/platform_device.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/dma-mapping.h> |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 18 | #include <linux/dmaengine.h> |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 19 | #include <linux/err.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/spi/spi.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 22 | #include <linux/slab.h> |
Jean-Christophe PLAGNIOL-VILLARD | bcd2360 | 2012-10-30 05:12:23 +0800 | [diff] [blame] | 23 | #include <linux/platform_data/atmel.h> |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 24 | #include <linux/platform_data/dma-atmel.h> |
Jean-Christophe PLAGNIOL-VILLARD | 850a5b6 | 2012-11-23 13:44:39 +0100 | [diff] [blame] | 25 | #include <linux/of.h> |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 26 | |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 27 | #include <linux/io.h> |
| 28 | #include <linux/gpio.h> |
David Brownell | bb2d1c3 | 2007-02-20 13:58:19 -0800 | [diff] [blame] | 29 | |
Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 30 | /* SPI register offsets */ |
| 31 | #define SPI_CR 0x0000 |
| 32 | #define SPI_MR 0x0004 |
| 33 | #define SPI_RDR 0x0008 |
| 34 | #define SPI_TDR 0x000c |
| 35 | #define SPI_SR 0x0010 |
| 36 | #define SPI_IER 0x0014 |
| 37 | #define SPI_IDR 0x0018 |
| 38 | #define SPI_IMR 0x001c |
| 39 | #define SPI_CSR0 0x0030 |
| 40 | #define SPI_CSR1 0x0034 |
| 41 | #define SPI_CSR2 0x0038 |
| 42 | #define SPI_CSR3 0x003c |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 43 | #define SPI_VERSION 0x00fc |
Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 44 | #define SPI_RPR 0x0100 |
| 45 | #define SPI_RCR 0x0104 |
| 46 | #define SPI_TPR 0x0108 |
| 47 | #define SPI_TCR 0x010c |
| 48 | #define SPI_RNPR 0x0110 |
| 49 | #define SPI_RNCR 0x0114 |
| 50 | #define SPI_TNPR 0x0118 |
| 51 | #define SPI_TNCR 0x011c |
| 52 | #define SPI_PTCR 0x0120 |
| 53 | #define SPI_PTSR 0x0124 |
| 54 | |
| 55 | /* Bitfields in CR */ |
| 56 | #define SPI_SPIEN_OFFSET 0 |
| 57 | #define SPI_SPIEN_SIZE 1 |
| 58 | #define SPI_SPIDIS_OFFSET 1 |
| 59 | #define SPI_SPIDIS_SIZE 1 |
| 60 | #define SPI_SWRST_OFFSET 7 |
| 61 | #define SPI_SWRST_SIZE 1 |
| 62 | #define SPI_LASTXFER_OFFSET 24 |
| 63 | #define SPI_LASTXFER_SIZE 1 |
| 64 | |
| 65 | /* Bitfields in MR */ |
| 66 | #define SPI_MSTR_OFFSET 0 |
| 67 | #define SPI_MSTR_SIZE 1 |
| 68 | #define SPI_PS_OFFSET 1 |
| 69 | #define SPI_PS_SIZE 1 |
| 70 | #define SPI_PCSDEC_OFFSET 2 |
| 71 | #define SPI_PCSDEC_SIZE 1 |
| 72 | #define SPI_FDIV_OFFSET 3 |
| 73 | #define SPI_FDIV_SIZE 1 |
| 74 | #define SPI_MODFDIS_OFFSET 4 |
| 75 | #define SPI_MODFDIS_SIZE 1 |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 76 | #define SPI_WDRBT_OFFSET 5 |
| 77 | #define SPI_WDRBT_SIZE 1 |
Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 78 | #define SPI_LLB_OFFSET 7 |
| 79 | #define SPI_LLB_SIZE 1 |
| 80 | #define SPI_PCS_OFFSET 16 |
| 81 | #define SPI_PCS_SIZE 4 |
| 82 | #define SPI_DLYBCS_OFFSET 24 |
| 83 | #define SPI_DLYBCS_SIZE 8 |
| 84 | |
| 85 | /* Bitfields in RDR */ |
| 86 | #define SPI_RD_OFFSET 0 |
| 87 | #define SPI_RD_SIZE 16 |
| 88 | |
| 89 | /* Bitfields in TDR */ |
| 90 | #define SPI_TD_OFFSET 0 |
| 91 | #define SPI_TD_SIZE 16 |
| 92 | |
| 93 | /* Bitfields in SR */ |
| 94 | #define SPI_RDRF_OFFSET 0 |
| 95 | #define SPI_RDRF_SIZE 1 |
| 96 | #define SPI_TDRE_OFFSET 1 |
| 97 | #define SPI_TDRE_SIZE 1 |
| 98 | #define SPI_MODF_OFFSET 2 |
| 99 | #define SPI_MODF_SIZE 1 |
| 100 | #define SPI_OVRES_OFFSET 3 |
| 101 | #define SPI_OVRES_SIZE 1 |
| 102 | #define SPI_ENDRX_OFFSET 4 |
| 103 | #define SPI_ENDRX_SIZE 1 |
| 104 | #define SPI_ENDTX_OFFSET 5 |
| 105 | #define SPI_ENDTX_SIZE 1 |
| 106 | #define SPI_RXBUFF_OFFSET 6 |
| 107 | #define SPI_RXBUFF_SIZE 1 |
| 108 | #define SPI_TXBUFE_OFFSET 7 |
| 109 | #define SPI_TXBUFE_SIZE 1 |
| 110 | #define SPI_NSSR_OFFSET 8 |
| 111 | #define SPI_NSSR_SIZE 1 |
| 112 | #define SPI_TXEMPTY_OFFSET 9 |
| 113 | #define SPI_TXEMPTY_SIZE 1 |
| 114 | #define SPI_SPIENS_OFFSET 16 |
| 115 | #define SPI_SPIENS_SIZE 1 |
| 116 | |
| 117 | /* Bitfields in CSR0 */ |
| 118 | #define SPI_CPOL_OFFSET 0 |
| 119 | #define SPI_CPOL_SIZE 1 |
| 120 | #define SPI_NCPHA_OFFSET 1 |
| 121 | #define SPI_NCPHA_SIZE 1 |
| 122 | #define SPI_CSAAT_OFFSET 3 |
| 123 | #define SPI_CSAAT_SIZE 1 |
| 124 | #define SPI_BITS_OFFSET 4 |
| 125 | #define SPI_BITS_SIZE 4 |
| 126 | #define SPI_SCBR_OFFSET 8 |
| 127 | #define SPI_SCBR_SIZE 8 |
| 128 | #define SPI_DLYBS_OFFSET 16 |
| 129 | #define SPI_DLYBS_SIZE 8 |
| 130 | #define SPI_DLYBCT_OFFSET 24 |
| 131 | #define SPI_DLYBCT_SIZE 8 |
| 132 | |
| 133 | /* Bitfields in RCR */ |
| 134 | #define SPI_RXCTR_OFFSET 0 |
| 135 | #define SPI_RXCTR_SIZE 16 |
| 136 | |
| 137 | /* Bitfields in TCR */ |
| 138 | #define SPI_TXCTR_OFFSET 0 |
| 139 | #define SPI_TXCTR_SIZE 16 |
| 140 | |
| 141 | /* Bitfields in RNCR */ |
| 142 | #define SPI_RXNCR_OFFSET 0 |
| 143 | #define SPI_RXNCR_SIZE 16 |
| 144 | |
| 145 | /* Bitfields in TNCR */ |
| 146 | #define SPI_TXNCR_OFFSET 0 |
| 147 | #define SPI_TXNCR_SIZE 16 |
| 148 | |
| 149 | /* Bitfields in PTCR */ |
| 150 | #define SPI_RXTEN_OFFSET 0 |
| 151 | #define SPI_RXTEN_SIZE 1 |
| 152 | #define SPI_RXTDIS_OFFSET 1 |
| 153 | #define SPI_RXTDIS_SIZE 1 |
| 154 | #define SPI_TXTEN_OFFSET 8 |
| 155 | #define SPI_TXTEN_SIZE 1 |
| 156 | #define SPI_TXTDIS_OFFSET 9 |
| 157 | #define SPI_TXTDIS_SIZE 1 |
| 158 | |
| 159 | /* Constants for BITS */ |
| 160 | #define SPI_BITS_8_BPT 0 |
| 161 | #define SPI_BITS_9_BPT 1 |
| 162 | #define SPI_BITS_10_BPT 2 |
| 163 | #define SPI_BITS_11_BPT 3 |
| 164 | #define SPI_BITS_12_BPT 4 |
| 165 | #define SPI_BITS_13_BPT 5 |
| 166 | #define SPI_BITS_14_BPT 6 |
| 167 | #define SPI_BITS_15_BPT 7 |
| 168 | #define SPI_BITS_16_BPT 8 |
| 169 | |
| 170 | /* Bit manipulation macros */ |
| 171 | #define SPI_BIT(name) \ |
| 172 | (1 << SPI_##name##_OFFSET) |
Sachin Kamat | a536d76 | 2013-09-10 17:06:27 +0530 | [diff] [blame] | 173 | #define SPI_BF(name, value) \ |
Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 174 | (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET) |
Sachin Kamat | a536d76 | 2013-09-10 17:06:27 +0530 | [diff] [blame] | 175 | #define SPI_BFEXT(name, value) \ |
Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 176 | (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1)) |
Sachin Kamat | a536d76 | 2013-09-10 17:06:27 +0530 | [diff] [blame] | 177 | #define SPI_BFINS(name, value, old) \ |
| 178 | (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \ |
| 179 | | SPI_BF(name, value)) |
Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 180 | |
| 181 | /* Register access macros */ |
Sachin Kamat | a536d76 | 2013-09-10 17:06:27 +0530 | [diff] [blame] | 182 | #define spi_readl(port, reg) \ |
Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 183 | __raw_readl((port)->regs + SPI_##reg) |
Sachin Kamat | a536d76 | 2013-09-10 17:06:27 +0530 | [diff] [blame] | 184 | #define spi_writel(port, reg, value) \ |
Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 185 | __raw_writel((value), (port)->regs + SPI_##reg) |
| 186 | |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 187 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and |
| 188 | * cache operations; better heuristics consider wordsize and bitrate. |
| 189 | */ |
| 190 | #define DMA_MIN_BYTES 16 |
| 191 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 192 | #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) |
| 193 | |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 194 | struct atmel_spi_dma { |
| 195 | struct dma_chan *chan_rx; |
| 196 | struct dma_chan *chan_tx; |
| 197 | struct scatterlist sgrx; |
| 198 | struct scatterlist sgtx; |
| 199 | struct dma_async_tx_descriptor *data_desc_rx; |
| 200 | struct dma_async_tx_descriptor *data_desc_tx; |
| 201 | |
| 202 | struct at_dma_slave dma_slave; |
| 203 | }; |
| 204 | |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 205 | struct atmel_spi_caps { |
| 206 | bool is_spi2; |
| 207 | bool has_wdrbt; |
| 208 | bool has_dma_support; |
| 209 | }; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 210 | |
| 211 | /* |
| 212 | * The core SPI transfer engine just talks to a register bank to set up |
| 213 | * DMA transfers; transfer queue progress is driven by IRQs. The clock |
| 214 | * framework provides the base clock, subdivided for each spi_device. |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 215 | */ |
| 216 | struct atmel_spi { |
| 217 | spinlock_t lock; |
Nicolas Ferre | 8aad792 | 2013-04-03 13:58:36 +0800 | [diff] [blame] | 218 | unsigned long flags; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 219 | |
Nicolas Ferre | dfab30e | 2013-04-03 13:57:42 +0800 | [diff] [blame] | 220 | phys_addr_t phybase; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 221 | void __iomem *regs; |
| 222 | int irq; |
| 223 | struct clk *clk; |
| 224 | struct platform_device *pdev; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 225 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 226 | struct spi_transfer *current_transfer; |
Silvester Erdeg | 154443c | 2008-02-06 01:38:12 -0800 | [diff] [blame] | 227 | unsigned long current_remaining_bytes; |
Nicolas Ferre | 823cd04 | 2013-03-19 15:45:01 +0800 | [diff] [blame] | 228 | int done_status; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 229 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 230 | struct completion xfer_completion; |
| 231 | |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 232 | /* scratch buffer */ |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 233 | void *buffer; |
| 234 | dma_addr_t buffer_dma; |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 235 | |
| 236 | struct atmel_spi_caps caps; |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 237 | |
| 238 | bool use_dma; |
| 239 | bool use_pdc; |
| 240 | /* dmaengine data */ |
| 241 | struct atmel_spi_dma dma; |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 242 | |
| 243 | bool keep_cs; |
| 244 | bool cs_active; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 245 | }; |
| 246 | |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 247 | /* Controller-specific per-slave state */ |
| 248 | struct atmel_spi_device { |
| 249 | unsigned int npcs_pin; |
| 250 | u32 csr; |
| 251 | }; |
| 252 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 253 | #define BUFFER_SIZE PAGE_SIZE |
| 254 | #define INVALID_DMA_ADDRESS 0xffffffff |
| 255 | |
| 256 | /* |
Haavard Skinnemoen | 5bfa26c | 2009-01-06 14:41:42 -0800 | [diff] [blame] | 257 | * Version 2 of the SPI controller has |
| 258 | * - CR.LASTXFER |
| 259 | * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero) |
| 260 | * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs) |
| 261 | * - SPI_CSRx.CSAAT |
| 262 | * - SPI_CSRx.SBCR allows faster clocking |
Haavard Skinnemoen | 5bfa26c | 2009-01-06 14:41:42 -0800 | [diff] [blame] | 263 | */ |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 264 | static bool atmel_spi_is_v2(struct atmel_spi *as) |
Haavard Skinnemoen | 5bfa26c | 2009-01-06 14:41:42 -0800 | [diff] [blame] | 265 | { |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 266 | return as->caps.is_spi2; |
Haavard Skinnemoen | 5bfa26c | 2009-01-06 14:41:42 -0800 | [diff] [blame] | 267 | } |
| 268 | |
| 269 | /* |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 270 | * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby |
| 271 | * they assume that spi slave device state will not change on deselect, so |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 272 | * that automagic deselection is OK. ("NPCSx rises if no data is to be |
| 273 | * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer |
| 274 | * controllers have CSAAT and friends. |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 275 | * |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 276 | * Since the CSAAT functionality is a bit weird on newer controllers as |
| 277 | * well, we use GPIO to control nCSx pins on all controllers, updating |
| 278 | * MR.PCS to avoid confusing the controller. Using GPIOs also lets us |
| 279 | * support active-high chipselects despite the controller's belief that |
| 280 | * only active-low devices/systems exists. |
| 281 | * |
| 282 | * However, at91rm9200 has a second erratum whereby nCS0 doesn't work |
| 283 | * right when driven with GPIO. ("Mode Fault does not allow more than one |
| 284 | * Master on Chip Select 0.") No workaround exists for that ... so for |
| 285 | * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, |
| 286 | * and (c) will trigger that first erratum in some cases. |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 287 | */ |
| 288 | |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 289 | static void cs_activate(struct atmel_spi *as, struct spi_device *spi) |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 290 | { |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 291 | struct atmel_spi_device *asd = spi->controller_state; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 292 | unsigned active = spi->mode & SPI_CS_HIGH; |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 293 | u32 mr; |
Atsushi Nemoto | f6febcc | 2008-02-23 15:23:39 -0800 | [diff] [blame] | 294 | |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 295 | if (atmel_spi_is_v2(as)) { |
Wenyou Yang | 97ed465 | 2013-03-19 15:43:01 +0800 | [diff] [blame] | 296 | spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr); |
| 297 | /* For the low SPI version, there is a issue that PDC transfer |
| 298 | * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 299 | */ |
| 300 | spi_writel(as, CSR0, asd->csr); |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 301 | if (as->caps.has_wdrbt) { |
Wenyou Yang | 97ed465 | 2013-03-19 15:43:01 +0800 | [diff] [blame] | 302 | spi_writel(as, MR, |
| 303 | SPI_BF(PCS, ~(0x01 << spi->chip_select)) |
| 304 | | SPI_BIT(WDRBT) |
| 305 | | SPI_BIT(MODFDIS) |
| 306 | | SPI_BIT(MSTR)); |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 307 | } else { |
Wenyou Yang | 97ed465 | 2013-03-19 15:43:01 +0800 | [diff] [blame] | 308 | spi_writel(as, MR, |
| 309 | SPI_BF(PCS, ~(0x01 << spi->chip_select)) |
| 310 | | SPI_BIT(MODFDIS) |
| 311 | | SPI_BIT(MSTR)); |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 312 | } |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 313 | |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 314 | mr = spi_readl(as, MR); |
| 315 | gpio_set_value(asd->npcs_pin, active); |
| 316 | } else { |
| 317 | u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0; |
| 318 | int i; |
| 319 | u32 csr; |
| 320 | |
| 321 | /* Make sure clock polarity is correct */ |
| 322 | for (i = 0; i < spi->master->num_chipselect; i++) { |
| 323 | csr = spi_readl(as, CSR0 + 4 * i); |
| 324 | if ((csr ^ cpol) & SPI_BIT(CPOL)) |
| 325 | spi_writel(as, CSR0 + 4 * i, |
| 326 | csr ^ SPI_BIT(CPOL)); |
| 327 | } |
| 328 | |
| 329 | mr = spi_readl(as, MR); |
| 330 | mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr); |
| 331 | if (spi->chip_select != 0) |
| 332 | gpio_set_value(asd->npcs_pin, active); |
| 333 | spi_writel(as, MR, mr); |
Atsushi Nemoto | f6febcc | 2008-02-23 15:23:39 -0800 | [diff] [blame] | 334 | } |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 335 | |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 336 | dev_dbg(&spi->dev, "activate %u%s, mr %08x\n", |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 337 | asd->npcs_pin, active ? " (high)" : "", |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 338 | mr); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 339 | } |
| 340 | |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 341 | static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi) |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 342 | { |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 343 | struct atmel_spi_device *asd = spi->controller_state; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 344 | unsigned active = spi->mode & SPI_CS_HIGH; |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 345 | u32 mr; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 346 | |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 347 | /* only deactivate *this* device; sometimes transfers to |
| 348 | * another device may be active when this routine is called. |
| 349 | */ |
| 350 | mr = spi_readl(as, MR); |
| 351 | if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) { |
| 352 | mr = SPI_BFINS(PCS, 0xf, mr); |
| 353 | spi_writel(as, MR, mr); |
| 354 | } |
| 355 | |
| 356 | dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n", |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 357 | asd->npcs_pin, active ? " (low)" : "", |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 358 | mr); |
| 359 | |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 360 | if (atmel_spi_is_v2(as) || spi->chip_select != 0) |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 361 | gpio_set_value(asd->npcs_pin, !active); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 362 | } |
| 363 | |
Mark Brown | 6c07ef2 | 2013-07-28 14:32:27 +0100 | [diff] [blame] | 364 | static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock) |
Nicolas Ferre | 8aad792 | 2013-04-03 13:58:36 +0800 | [diff] [blame] | 365 | { |
| 366 | spin_lock_irqsave(&as->lock, as->flags); |
| 367 | } |
| 368 | |
Mark Brown | 6c07ef2 | 2013-07-28 14:32:27 +0100 | [diff] [blame] | 369 | static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock) |
Nicolas Ferre | 8aad792 | 2013-04-03 13:58:36 +0800 | [diff] [blame] | 370 | { |
| 371 | spin_unlock_irqrestore(&as->lock, as->flags); |
| 372 | } |
| 373 | |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 374 | static inline bool atmel_spi_use_dma(struct atmel_spi *as, |
| 375 | struct spi_transfer *xfer) |
| 376 | { |
| 377 | return as->use_dma && xfer->len >= DMA_MIN_BYTES; |
| 378 | } |
| 379 | |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 380 | static int atmel_spi_dma_slave_config(struct atmel_spi *as, |
| 381 | struct dma_slave_config *slave_config, |
| 382 | u8 bits_per_word) |
| 383 | { |
| 384 | int err = 0; |
| 385 | |
| 386 | if (bits_per_word > 8) { |
| 387 | slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
| 388 | slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; |
| 389 | } else { |
| 390 | slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
| 391 | slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; |
| 392 | } |
| 393 | |
| 394 | slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR; |
| 395 | slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR; |
| 396 | slave_config->src_maxburst = 1; |
| 397 | slave_config->dst_maxburst = 1; |
| 398 | slave_config->device_fc = false; |
| 399 | |
| 400 | slave_config->direction = DMA_MEM_TO_DEV; |
| 401 | if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) { |
| 402 | dev_err(&as->pdev->dev, |
| 403 | "failed to configure tx dma channel\n"); |
| 404 | err = -EINVAL; |
| 405 | } |
| 406 | |
| 407 | slave_config->direction = DMA_DEV_TO_MEM; |
| 408 | if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) { |
| 409 | dev_err(&as->pdev->dev, |
| 410 | "failed to configure rx dma channel\n"); |
| 411 | err = -EINVAL; |
| 412 | } |
| 413 | |
| 414 | return err; |
| 415 | } |
| 416 | |
Richard Genoud | 2f767a9 | 2013-05-31 17:01:59 +0200 | [diff] [blame] | 417 | static bool filter(struct dma_chan *chan, void *pdata) |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 418 | { |
Richard Genoud | 2f767a9 | 2013-05-31 17:01:59 +0200 | [diff] [blame] | 419 | struct atmel_spi_dma *sl_pdata = pdata; |
| 420 | struct at_dma_slave *sl; |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 421 | |
Richard Genoud | 2f767a9 | 2013-05-31 17:01:59 +0200 | [diff] [blame] | 422 | if (!sl_pdata) |
| 423 | return false; |
| 424 | |
| 425 | sl = &sl_pdata->dma_slave; |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 426 | if (sl->dma_dev == chan->device->dev) { |
| 427 | chan->private = sl; |
| 428 | return true; |
| 429 | } else { |
| 430 | return false; |
| 431 | } |
| 432 | } |
| 433 | |
| 434 | static int atmel_spi_configure_dma(struct atmel_spi *as) |
| 435 | { |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 436 | struct dma_slave_config slave_config; |
Richard Genoud | 2f767a9 | 2013-05-31 17:01:59 +0200 | [diff] [blame] | 437 | struct device *dev = &as->pdev->dev; |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 438 | int err; |
| 439 | |
Richard Genoud | 2f767a9 | 2013-05-31 17:01:59 +0200 | [diff] [blame] | 440 | dma_cap_mask_t mask; |
| 441 | dma_cap_zero(mask); |
| 442 | dma_cap_set(DMA_SLAVE, mask); |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 443 | |
Richard Genoud | 2f767a9 | 2013-05-31 17:01:59 +0200 | [diff] [blame] | 444 | as->dma.chan_tx = dma_request_slave_channel_compat(mask, filter, |
| 445 | &as->dma, |
| 446 | dev, "tx"); |
| 447 | if (!as->dma.chan_tx) { |
| 448 | dev_err(dev, |
| 449 | "DMA TX channel not available, SPI unable to use DMA\n"); |
| 450 | err = -EBUSY; |
| 451 | goto error; |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 452 | } |
Richard Genoud | 2f767a9 | 2013-05-31 17:01:59 +0200 | [diff] [blame] | 453 | |
| 454 | as->dma.chan_rx = dma_request_slave_channel_compat(mask, filter, |
| 455 | &as->dma, |
| 456 | dev, "rx"); |
| 457 | |
| 458 | if (!as->dma.chan_rx) { |
| 459 | dev_err(dev, |
| 460 | "DMA RX channel not available, SPI unable to use DMA\n"); |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 461 | err = -EBUSY; |
| 462 | goto error; |
| 463 | } |
| 464 | |
| 465 | err = atmel_spi_dma_slave_config(as, &slave_config, 8); |
| 466 | if (err) |
| 467 | goto error; |
| 468 | |
| 469 | dev_info(&as->pdev->dev, |
| 470 | "Using %s (tx) and %s (rx) for DMA transfers\n", |
| 471 | dma_chan_name(as->dma.chan_tx), |
| 472 | dma_chan_name(as->dma.chan_rx)); |
| 473 | return 0; |
| 474 | error: |
| 475 | if (as->dma.chan_rx) |
| 476 | dma_release_channel(as->dma.chan_rx); |
| 477 | if (as->dma.chan_tx) |
| 478 | dma_release_channel(as->dma.chan_tx); |
| 479 | return err; |
| 480 | } |
| 481 | |
| 482 | static void atmel_spi_stop_dma(struct atmel_spi *as) |
| 483 | { |
| 484 | if (as->dma.chan_rx) |
| 485 | as->dma.chan_rx->device->device_control(as->dma.chan_rx, |
| 486 | DMA_TERMINATE_ALL, 0); |
| 487 | if (as->dma.chan_tx) |
| 488 | as->dma.chan_tx->device->device_control(as->dma.chan_tx, |
| 489 | DMA_TERMINATE_ALL, 0); |
| 490 | } |
| 491 | |
| 492 | static void atmel_spi_release_dma(struct atmel_spi *as) |
| 493 | { |
| 494 | if (as->dma.chan_rx) |
| 495 | dma_release_channel(as->dma.chan_rx); |
| 496 | if (as->dma.chan_tx) |
| 497 | dma_release_channel(as->dma.chan_tx); |
| 498 | } |
| 499 | |
| 500 | /* This function is called by the DMA driver from tasklet context */ |
| 501 | static void dma_callback(void *data) |
| 502 | { |
| 503 | struct spi_master *master = data; |
| 504 | struct atmel_spi *as = spi_master_get_devdata(master); |
| 505 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 506 | complete(&as->xfer_completion); |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 507 | } |
| 508 | |
| 509 | /* |
| 510 | * Next transfer using PIO. |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 511 | */ |
| 512 | static void atmel_spi_next_xfer_pio(struct spi_master *master, |
| 513 | struct spi_transfer *xfer) |
| 514 | { |
| 515 | struct atmel_spi *as = spi_master_get_devdata(master); |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 516 | unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 517 | |
| 518 | dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n"); |
| 519 | |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 520 | /* Make sure data is not remaining in RDR */ |
| 521 | spi_readl(as, RDR); |
| 522 | while (spi_readl(as, SR) & SPI_BIT(RDRF)) { |
| 523 | spi_readl(as, RDR); |
| 524 | cpu_relax(); |
| 525 | } |
| 526 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 527 | if (xfer->tx_buf) { |
Richard Genoud | f557c98 | 2013-05-02 19:25:11 +0800 | [diff] [blame] | 528 | if (xfer->bits_per_word > 8) |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 529 | spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos)); |
Richard Genoud | f557c98 | 2013-05-02 19:25:11 +0800 | [diff] [blame] | 530 | else |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 531 | spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos)); |
| 532 | } else { |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 533 | spi_writel(as, TDR, 0); |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 534 | } |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 535 | |
| 536 | dev_dbg(master->dev.parent, |
Richard Genoud | f557c98 | 2013-05-02 19:25:11 +0800 | [diff] [blame] | 537 | " start pio xfer %p: len %u tx %p rx %p bitpw %d\n", |
| 538 | xfer, xfer->len, xfer->tx_buf, xfer->rx_buf, |
| 539 | xfer->bits_per_word); |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 540 | |
| 541 | /* Enable relevant interrupts */ |
| 542 | spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES)); |
| 543 | } |
| 544 | |
| 545 | /* |
| 546 | * Submit next transfer for DMA. |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 547 | */ |
| 548 | static int atmel_spi_next_xfer_dma_submit(struct spi_master *master, |
| 549 | struct spi_transfer *xfer, |
| 550 | u32 *plen) |
| 551 | { |
| 552 | struct atmel_spi *as = spi_master_get_devdata(master); |
| 553 | struct dma_chan *rxchan = as->dma.chan_rx; |
| 554 | struct dma_chan *txchan = as->dma.chan_tx; |
| 555 | struct dma_async_tx_descriptor *rxdesc; |
| 556 | struct dma_async_tx_descriptor *txdesc; |
| 557 | struct dma_slave_config slave_config; |
| 558 | dma_cookie_t cookie; |
| 559 | u32 len = *plen; |
| 560 | |
| 561 | dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n"); |
| 562 | |
| 563 | /* Check that the channels are available */ |
| 564 | if (!rxchan || !txchan) |
| 565 | return -ENODEV; |
| 566 | |
| 567 | /* release lock for DMA operations */ |
| 568 | atmel_spi_unlock(as); |
| 569 | |
| 570 | /* prepare the RX dma transfer */ |
| 571 | sg_init_table(&as->dma.sgrx, 1); |
| 572 | if (xfer->rx_buf) { |
| 573 | as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen; |
| 574 | } else { |
| 575 | as->dma.sgrx.dma_address = as->buffer_dma; |
| 576 | if (len > BUFFER_SIZE) |
| 577 | len = BUFFER_SIZE; |
| 578 | } |
| 579 | |
| 580 | /* prepare the TX dma transfer */ |
| 581 | sg_init_table(&as->dma.sgtx, 1); |
| 582 | if (xfer->tx_buf) { |
| 583 | as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen; |
| 584 | } else { |
| 585 | as->dma.sgtx.dma_address = as->buffer_dma; |
| 586 | if (len > BUFFER_SIZE) |
| 587 | len = BUFFER_SIZE; |
| 588 | memset(as->buffer, 0, len); |
| 589 | } |
| 590 | |
| 591 | sg_dma_len(&as->dma.sgtx) = len; |
| 592 | sg_dma_len(&as->dma.sgrx) = len; |
| 593 | |
| 594 | *plen = len; |
| 595 | |
| 596 | if (atmel_spi_dma_slave_config(as, &slave_config, 8)) |
| 597 | goto err_exit; |
| 598 | |
| 599 | /* Send both scatterlists */ |
| 600 | rxdesc = rxchan->device->device_prep_slave_sg(rxchan, |
| 601 | &as->dma.sgrx, |
| 602 | 1, |
| 603 | DMA_FROM_DEVICE, |
| 604 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK, |
| 605 | NULL); |
| 606 | if (!rxdesc) |
| 607 | goto err_dma; |
| 608 | |
| 609 | txdesc = txchan->device->device_prep_slave_sg(txchan, |
| 610 | &as->dma.sgtx, |
| 611 | 1, |
| 612 | DMA_TO_DEVICE, |
| 613 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK, |
| 614 | NULL); |
| 615 | if (!txdesc) |
| 616 | goto err_dma; |
| 617 | |
| 618 | dev_dbg(master->dev.parent, |
Emil Goode | 2de024b | 2013-07-30 19:35:35 +0200 | [diff] [blame] | 619 | " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", |
| 620 | xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma, |
| 621 | xfer->rx_buf, (unsigned long long)xfer->rx_dma); |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 622 | |
| 623 | /* Enable relevant interrupts */ |
| 624 | spi_writel(as, IER, SPI_BIT(OVRES)); |
| 625 | |
| 626 | /* Put the callback on the RX transfer only, that should finish last */ |
| 627 | rxdesc->callback = dma_callback; |
| 628 | rxdesc->callback_param = master; |
| 629 | |
| 630 | /* Submit and fire RX and TX with TX last so we're ready to read! */ |
| 631 | cookie = rxdesc->tx_submit(rxdesc); |
| 632 | if (dma_submit_error(cookie)) |
| 633 | goto err_dma; |
| 634 | cookie = txdesc->tx_submit(txdesc); |
| 635 | if (dma_submit_error(cookie)) |
| 636 | goto err_dma; |
| 637 | rxchan->device->device_issue_pending(rxchan); |
| 638 | txchan->device->device_issue_pending(txchan); |
| 639 | |
| 640 | /* take back lock */ |
| 641 | atmel_spi_lock(as); |
| 642 | return 0; |
| 643 | |
| 644 | err_dma: |
| 645 | spi_writel(as, IDR, SPI_BIT(OVRES)); |
| 646 | atmel_spi_stop_dma(as); |
| 647 | err_exit: |
| 648 | atmel_spi_lock(as); |
| 649 | return -ENOMEM; |
| 650 | } |
| 651 | |
Silvester Erdeg | 154443c | 2008-02-06 01:38:12 -0800 | [diff] [blame] | 652 | static void atmel_spi_next_xfer_data(struct spi_master *master, |
| 653 | struct spi_transfer *xfer, |
| 654 | dma_addr_t *tx_dma, |
| 655 | dma_addr_t *rx_dma, |
| 656 | u32 *plen) |
| 657 | { |
| 658 | struct atmel_spi *as = spi_master_get_devdata(master); |
| 659 | u32 len = *plen; |
| 660 | |
| 661 | /* use scratch buffer only when rx or tx data is unspecified */ |
| 662 | if (xfer->rx_buf) |
Ben Nizette | 6aed4ee | 2009-12-14 22:20:20 -0800 | [diff] [blame] | 663 | *rx_dma = xfer->rx_dma + xfer->len - *plen; |
Silvester Erdeg | 154443c | 2008-02-06 01:38:12 -0800 | [diff] [blame] | 664 | else { |
| 665 | *rx_dma = as->buffer_dma; |
| 666 | if (len > BUFFER_SIZE) |
| 667 | len = BUFFER_SIZE; |
| 668 | } |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 669 | |
Silvester Erdeg | 154443c | 2008-02-06 01:38:12 -0800 | [diff] [blame] | 670 | if (xfer->tx_buf) |
Ben Nizette | 6aed4ee | 2009-12-14 22:20:20 -0800 | [diff] [blame] | 671 | *tx_dma = xfer->tx_dma + xfer->len - *plen; |
Silvester Erdeg | 154443c | 2008-02-06 01:38:12 -0800 | [diff] [blame] | 672 | else { |
| 673 | *tx_dma = as->buffer_dma; |
| 674 | if (len > BUFFER_SIZE) |
| 675 | len = BUFFER_SIZE; |
| 676 | memset(as->buffer, 0, len); |
| 677 | dma_sync_single_for_device(&as->pdev->dev, |
| 678 | as->buffer_dma, len, DMA_TO_DEVICE); |
| 679 | } |
| 680 | |
| 681 | *plen = len; |
| 682 | } |
| 683 | |
Richard Genoud | d3b72c7 | 2013-11-07 10:34:06 +0100 | [diff] [blame] | 684 | static int atmel_spi_set_xfer_speed(struct atmel_spi *as, |
| 685 | struct spi_device *spi, |
| 686 | struct spi_transfer *xfer) |
| 687 | { |
| 688 | u32 scbr, csr; |
| 689 | unsigned long bus_hz; |
| 690 | |
| 691 | /* v1 chips start out at half the peripheral bus speed. */ |
| 692 | bus_hz = clk_get_rate(as->clk); |
| 693 | if (!atmel_spi_is_v2(as)) |
| 694 | bus_hz /= 2; |
| 695 | |
| 696 | /* |
| 697 | * Calculate the lowest divider that satisfies the |
| 698 | * constraint, assuming div32/fdiv/mbz == 0. |
| 699 | */ |
| 700 | if (xfer->speed_hz) |
| 701 | scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz); |
| 702 | else |
| 703 | /* |
| 704 | * This can happend if max_speed is null. |
| 705 | * In this case, we set the lowest possible speed |
| 706 | */ |
| 707 | scbr = 0xff; |
| 708 | |
| 709 | /* |
| 710 | * If the resulting divider doesn't fit into the |
| 711 | * register bitfield, we can't satisfy the constraint. |
| 712 | */ |
| 713 | if (scbr >= (1 << SPI_SCBR_SIZE)) { |
| 714 | dev_err(&spi->dev, |
| 715 | "setup: %d Hz too slow, scbr %u; min %ld Hz\n", |
| 716 | xfer->speed_hz, scbr, bus_hz/255); |
| 717 | return -EINVAL; |
| 718 | } |
| 719 | if (scbr == 0) { |
| 720 | dev_err(&spi->dev, |
| 721 | "setup: %d Hz too high, scbr %u; max %ld Hz\n", |
| 722 | xfer->speed_hz, scbr, bus_hz); |
| 723 | return -EINVAL; |
| 724 | } |
| 725 | csr = spi_readl(as, CSR0 + 4 * spi->chip_select); |
| 726 | csr = SPI_BFINS(SCBR, scbr, csr); |
| 727 | spi_writel(as, CSR0 + 4 * spi->chip_select, csr); |
| 728 | |
| 729 | return 0; |
| 730 | } |
| 731 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 732 | /* |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 733 | * Submit next transfer for PDC. |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 734 | * lock is held, spi irq is blocked |
| 735 | */ |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 736 | static void atmel_spi_pdc_next_xfer(struct spi_master *master, |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 737 | struct spi_message *msg, |
| 738 | struct spi_transfer *xfer) |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 739 | { |
| 740 | struct atmel_spi *as = spi_master_get_devdata(master); |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 741 | u32 len; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 742 | dma_addr_t tx_dma, rx_dma; |
| 743 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 744 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); |
Silvester Erdeg | 154443c | 2008-02-06 01:38:12 -0800 | [diff] [blame] | 745 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 746 | len = as->current_remaining_bytes; |
| 747 | atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); |
| 748 | as->current_remaining_bytes -= len; |
Gerard Kam | dc32944 | 2008-08-04 13:41:12 -0700 | [diff] [blame] | 749 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 750 | spi_writel(as, RPR, rx_dma); |
| 751 | spi_writel(as, TPR, tx_dma); |
| 752 | |
| 753 | if (msg->spi->bits_per_word > 8) |
| 754 | len >>= 1; |
| 755 | spi_writel(as, RCR, len); |
| 756 | spi_writel(as, TCR, len); |
| 757 | |
| 758 | dev_dbg(&msg->spi->dev, |
| 759 | " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", |
| 760 | xfer, xfer->len, xfer->tx_buf, |
| 761 | (unsigned long long)xfer->tx_dma, xfer->rx_buf, |
| 762 | (unsigned long long)xfer->rx_dma); |
| 763 | |
| 764 | if (as->current_remaining_bytes) { |
| 765 | len = as->current_remaining_bytes; |
Silvester Erdeg | 154443c | 2008-02-06 01:38:12 -0800 | [diff] [blame] | 766 | atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 767 | as->current_remaining_bytes -= len; |
Silvester Erdeg | 154443c | 2008-02-06 01:38:12 -0800 | [diff] [blame] | 768 | |
| 769 | spi_writel(as, RNPR, rx_dma); |
| 770 | spi_writel(as, TNPR, tx_dma); |
| 771 | |
| 772 | if (msg->spi->bits_per_word > 8) |
| 773 | len >>= 1; |
| 774 | spi_writel(as, RNCR, len); |
| 775 | spi_writel(as, TNCR, len); |
Haavard Skinnemoen | 8bacb21 | 2008-02-06 01:38:13 -0800 | [diff] [blame] | 776 | |
| 777 | dev_dbg(&msg->spi->dev, |
Emil Goode | 2de024b | 2013-07-30 19:35:35 +0200 | [diff] [blame] | 778 | " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", |
| 779 | xfer, xfer->len, xfer->tx_buf, |
| 780 | (unsigned long long)xfer->tx_dma, xfer->rx_buf, |
| 781 | (unsigned long long)xfer->rx_dma); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 782 | } |
| 783 | |
Silvester Erdeg | 154443c | 2008-02-06 01:38:12 -0800 | [diff] [blame] | 784 | /* REVISIT: We're waiting for ENDRX before we start the next |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 785 | * transfer because we need to handle some difficult timing |
| 786 | * issues otherwise. If we wait for ENDTX in one transfer and |
| 787 | * then starts waiting for ENDRX in the next, it's difficult |
| 788 | * to tell the difference between the ENDRX interrupt we're |
| 789 | * actually waiting for and the ENDRX interrupt of the |
| 790 | * previous transfer. |
| 791 | * |
| 792 | * It should be doable, though. Just not now... |
| 793 | */ |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 794 | spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES)); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 795 | spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); |
| 796 | } |
| 797 | |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 798 | /* |
David Brownell | 8da0859 | 2007-07-17 04:04:07 -0700 | [diff] [blame] | 799 | * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma: |
| 800 | * - The buffer is either valid for CPU access, else NULL |
Uwe Kleine-König | b595076 | 2010-11-01 15:38:34 -0400 | [diff] [blame] | 801 | * - If the buffer is valid, so is its DMA address |
David Brownell | 8da0859 | 2007-07-17 04:04:07 -0700 | [diff] [blame] | 802 | * |
Uwe Kleine-König | b595076 | 2010-11-01 15:38:34 -0400 | [diff] [blame] | 803 | * This driver manages the dma address unless message->is_dma_mapped. |
David Brownell | 8da0859 | 2007-07-17 04:04:07 -0700 | [diff] [blame] | 804 | */ |
| 805 | static int |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 806 | atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer) |
| 807 | { |
David Brownell | 8da0859 | 2007-07-17 04:04:07 -0700 | [diff] [blame] | 808 | struct device *dev = &as->pdev->dev; |
| 809 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 810 | xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; |
David Brownell | 8da0859 | 2007-07-17 04:04:07 -0700 | [diff] [blame] | 811 | if (xfer->tx_buf) { |
Jean-Christophe PLAGNIOL-VILLARD | 214b574 | 2010-11-20 14:52:53 +0800 | [diff] [blame] | 812 | /* tx_buf is a const void* where we need a void * for the dma |
| 813 | * mapping */ |
| 814 | void *nonconst_tx = (void *)xfer->tx_buf; |
| 815 | |
David Brownell | 8da0859 | 2007-07-17 04:04:07 -0700 | [diff] [blame] | 816 | xfer->tx_dma = dma_map_single(dev, |
Jean-Christophe PLAGNIOL-VILLARD | 214b574 | 2010-11-20 14:52:53 +0800 | [diff] [blame] | 817 | nonconst_tx, xfer->len, |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 818 | DMA_TO_DEVICE); |
FUJITA Tomonori | 8d8bb39 | 2008-07-25 19:44:49 -0700 | [diff] [blame] | 819 | if (dma_mapping_error(dev, xfer->tx_dma)) |
David Brownell | 8da0859 | 2007-07-17 04:04:07 -0700 | [diff] [blame] | 820 | return -ENOMEM; |
| 821 | } |
| 822 | if (xfer->rx_buf) { |
| 823 | xfer->rx_dma = dma_map_single(dev, |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 824 | xfer->rx_buf, xfer->len, |
| 825 | DMA_FROM_DEVICE); |
FUJITA Tomonori | 8d8bb39 | 2008-07-25 19:44:49 -0700 | [diff] [blame] | 826 | if (dma_mapping_error(dev, xfer->rx_dma)) { |
David Brownell | 8da0859 | 2007-07-17 04:04:07 -0700 | [diff] [blame] | 827 | if (xfer->tx_buf) |
| 828 | dma_unmap_single(dev, |
| 829 | xfer->tx_dma, xfer->len, |
| 830 | DMA_TO_DEVICE); |
| 831 | return -ENOMEM; |
| 832 | } |
| 833 | } |
| 834 | return 0; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 835 | } |
| 836 | |
| 837 | static void atmel_spi_dma_unmap_xfer(struct spi_master *master, |
| 838 | struct spi_transfer *xfer) |
| 839 | { |
| 840 | if (xfer->tx_dma != INVALID_DMA_ADDRESS) |
Tony Jones | 49dce68 | 2007-10-16 01:27:48 -0700 | [diff] [blame] | 841 | dma_unmap_single(master->dev.parent, xfer->tx_dma, |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 842 | xfer->len, DMA_TO_DEVICE); |
| 843 | if (xfer->rx_dma != INVALID_DMA_ADDRESS) |
Tony Jones | 49dce68 | 2007-10-16 01:27:48 -0700 | [diff] [blame] | 844 | dma_unmap_single(master->dev.parent, xfer->rx_dma, |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 845 | xfer->len, DMA_FROM_DEVICE); |
| 846 | } |
| 847 | |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 848 | static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as) |
| 849 | { |
| 850 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); |
| 851 | } |
| 852 | |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 853 | /* Called from IRQ |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 854 | * |
| 855 | * Must update "current_remaining_bytes" to keep track of data |
| 856 | * to transfer. |
| 857 | */ |
| 858 | static void |
| 859 | atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer) |
| 860 | { |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 861 | u8 *rxp; |
Richard Genoud | f557c98 | 2013-05-02 19:25:11 +0800 | [diff] [blame] | 862 | u16 *rxp16; |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 863 | unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; |
| 864 | |
| 865 | if (xfer->rx_buf) { |
Richard Genoud | f557c98 | 2013-05-02 19:25:11 +0800 | [diff] [blame] | 866 | if (xfer->bits_per_word > 8) { |
| 867 | rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos); |
| 868 | *rxp16 = spi_readl(as, RDR); |
| 869 | } else { |
| 870 | rxp = ((u8 *)xfer->rx_buf) + xfer_pos; |
| 871 | *rxp = spi_readl(as, RDR); |
| 872 | } |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 873 | } else { |
| 874 | spi_readl(as, RDR); |
| 875 | } |
Richard Genoud | f557c98 | 2013-05-02 19:25:11 +0800 | [diff] [blame] | 876 | if (xfer->bits_per_word > 8) { |
| 877 | as->current_remaining_bytes -= 2; |
| 878 | if (as->current_remaining_bytes < 0) |
| 879 | as->current_remaining_bytes = 0; |
| 880 | } else { |
| 881 | as->current_remaining_bytes--; |
| 882 | } |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 883 | } |
| 884 | |
| 885 | /* Interrupt |
| 886 | * |
| 887 | * No need for locking in this Interrupt handler: done_status is the |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 888 | * only information modified. |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 889 | */ |
| 890 | static irqreturn_t |
| 891 | atmel_spi_pio_interrupt(int irq, void *dev_id) |
| 892 | { |
| 893 | struct spi_master *master = dev_id; |
| 894 | struct atmel_spi *as = spi_master_get_devdata(master); |
| 895 | u32 status, pending, imr; |
| 896 | struct spi_transfer *xfer; |
| 897 | int ret = IRQ_NONE; |
| 898 | |
| 899 | imr = spi_readl(as, IMR); |
| 900 | status = spi_readl(as, SR); |
| 901 | pending = status & imr; |
| 902 | |
| 903 | if (pending & SPI_BIT(OVRES)) { |
| 904 | ret = IRQ_HANDLED; |
| 905 | spi_writel(as, IDR, SPI_BIT(OVRES)); |
| 906 | dev_warn(master->dev.parent, "overrun\n"); |
| 907 | |
| 908 | /* |
| 909 | * When we get an overrun, we disregard the current |
| 910 | * transfer. Data will not be copied back from any |
| 911 | * bounce buffer and msg->actual_len will not be |
| 912 | * updated with the last xfer. |
| 913 | * |
| 914 | * We will also not process any remaning transfers in |
| 915 | * the message. |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 916 | */ |
| 917 | as->done_status = -EIO; |
| 918 | smp_wmb(); |
| 919 | |
| 920 | /* Clear any overrun happening while cleaning up */ |
| 921 | spi_readl(as, SR); |
| 922 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 923 | complete(&as->xfer_completion); |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 924 | |
| 925 | } else if (pending & SPI_BIT(RDRF)) { |
| 926 | atmel_spi_lock(as); |
| 927 | |
| 928 | if (as->current_remaining_bytes) { |
| 929 | ret = IRQ_HANDLED; |
| 930 | xfer = as->current_transfer; |
| 931 | atmel_spi_pump_pio_data(as, xfer); |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 932 | if (!as->current_remaining_bytes) |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 933 | spi_writel(as, IDR, pending); |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 934 | |
| 935 | complete(&as->xfer_completion); |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 936 | } |
| 937 | |
| 938 | atmel_spi_unlock(as); |
| 939 | } else { |
| 940 | WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending); |
| 941 | ret = IRQ_HANDLED; |
| 942 | spi_writel(as, IDR, pending); |
| 943 | } |
| 944 | |
| 945 | return ret; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 946 | } |
| 947 | |
| 948 | static irqreturn_t |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 949 | atmel_spi_pdc_interrupt(int irq, void *dev_id) |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 950 | { |
| 951 | struct spi_master *master = dev_id; |
| 952 | struct atmel_spi *as = spi_master_get_devdata(master); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 953 | u32 status, pending, imr; |
| 954 | int ret = IRQ_NONE; |
| 955 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 956 | imr = spi_readl(as, IMR); |
| 957 | status = spi_readl(as, SR); |
| 958 | pending = status & imr; |
| 959 | |
| 960 | if (pending & SPI_BIT(OVRES)) { |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 961 | |
| 962 | ret = IRQ_HANDLED; |
| 963 | |
Gerard Kam | dc32944 | 2008-08-04 13:41:12 -0700 | [diff] [blame] | 964 | spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 965 | | SPI_BIT(OVRES))); |
| 966 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 967 | /* Clear any overrun happening while cleaning up */ |
| 968 | spi_readl(as, SR); |
| 969 | |
Nicolas Ferre | 823cd04 | 2013-03-19 15:45:01 +0800 | [diff] [blame] | 970 | as->done_status = -EIO; |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 971 | |
| 972 | complete(&as->xfer_completion); |
| 973 | |
Gerard Kam | dc32944 | 2008-08-04 13:41:12 -0700 | [diff] [blame] | 974 | } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) { |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 975 | ret = IRQ_HANDLED; |
| 976 | |
| 977 | spi_writel(as, IDR, pending); |
| 978 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 979 | complete(&as->xfer_completion); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 980 | } |
| 981 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 982 | return ret; |
| 983 | } |
| 984 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 985 | static int atmel_spi_setup(struct spi_device *spi) |
| 986 | { |
| 987 | struct atmel_spi *as; |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 988 | struct atmel_spi_device *asd; |
Richard Genoud | d3b72c7 | 2013-11-07 10:34:06 +0100 | [diff] [blame] | 989 | u32 csr; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 990 | unsigned int bits = spi->bits_per_word; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 991 | unsigned int npcs_pin; |
| 992 | int ret; |
| 993 | |
| 994 | as = spi_master_get_devdata(spi->master); |
| 995 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 996 | if (spi->chip_select > spi->master->num_chipselect) { |
| 997 | dev_dbg(&spi->dev, |
| 998 | "setup: invalid chipselect %u (%u defined)\n", |
| 999 | spi->chip_select, spi->master->num_chipselect); |
| 1000 | return -EINVAL; |
| 1001 | } |
| 1002 | |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 1003 | /* see notes above re chipselect */ |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 1004 | if (!atmel_spi_is_v2(as) |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 1005 | && spi->chip_select == 0 |
| 1006 | && (spi->mode & SPI_CS_HIGH)) { |
| 1007 | dev_dbg(&spi->dev, "setup: can't be active-high\n"); |
| 1008 | return -EINVAL; |
| 1009 | } |
| 1010 | |
Richard Genoud | d3b72c7 | 2013-11-07 10:34:06 +0100 | [diff] [blame] | 1011 | csr = SPI_BF(BITS, bits - 8); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1012 | if (spi->mode & SPI_CPOL) |
| 1013 | csr |= SPI_BIT(CPOL); |
| 1014 | if (!(spi->mode & SPI_CPHA)) |
| 1015 | csr |= SPI_BIT(NCPHA); |
| 1016 | |
Haavard Skinnemoen | 1eed29d | 2008-02-06 01:38:11 -0800 | [diff] [blame] | 1017 | /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs. |
| 1018 | * |
| 1019 | * DLYBCT would add delays between words, slowing down transfers. |
| 1020 | * It could potentially be useful to cope with DMA bottlenecks, but |
| 1021 | * in those cases it's probably best to just use a lower bitrate. |
| 1022 | */ |
| 1023 | csr |= SPI_BF(DLYBS, 0); |
| 1024 | csr |= SPI_BF(DLYBCT, 0); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1025 | |
| 1026 | /* chipselect must have been muxed as GPIO (e.g. in board setup) */ |
| 1027 | npcs_pin = (unsigned int)spi->controller_data; |
Jean-Christophe PLAGNIOL-VILLARD | 850a5b6 | 2012-11-23 13:44:39 +0100 | [diff] [blame] | 1028 | |
| 1029 | if (gpio_is_valid(spi->cs_gpio)) |
| 1030 | npcs_pin = spi->cs_gpio; |
| 1031 | |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 1032 | asd = spi->controller_state; |
| 1033 | if (!asd) { |
| 1034 | asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL); |
| 1035 | if (!asd) |
| 1036 | return -ENOMEM; |
| 1037 | |
Kay Sievers | 6c7377a | 2009-03-24 16:38:21 -0700 | [diff] [blame] | 1038 | ret = gpio_request(npcs_pin, dev_name(&spi->dev)); |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 1039 | if (ret) { |
| 1040 | kfree(asd); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1041 | return ret; |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 1042 | } |
| 1043 | |
| 1044 | asd->npcs_pin = npcs_pin; |
| 1045 | spi->controller_state = asd; |
David Brownell | 28735a7 | 2007-03-16 13:38:14 -0800 | [diff] [blame] | 1046 | gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH)); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1047 | } |
| 1048 | |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 1049 | asd->csr = csr; |
| 1050 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1051 | dev_dbg(&spi->dev, |
Richard Genoud | d3b72c7 | 2013-11-07 10:34:06 +0100 | [diff] [blame] | 1052 | "setup: bpw %u mode 0x%x -> csr%d %08x\n", |
| 1053 | bits, spi->mode, spi->chip_select, csr); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1054 | |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 1055 | if (!atmel_spi_is_v2(as)) |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 1056 | spi_writel(as, CSR0 + 4 * spi->chip_select, csr); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1057 | |
| 1058 | return 0; |
| 1059 | } |
| 1060 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 1061 | static int atmel_spi_one_transfer(struct spi_master *master, |
| 1062 | struct spi_message *msg, |
| 1063 | struct spi_transfer *xfer) |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1064 | { |
| 1065 | struct atmel_spi *as; |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 1066 | struct spi_device *spi = msg->spi; |
Matthias Brugger | b9d228f | 2010-10-13 17:51:02 +0200 | [diff] [blame] | 1067 | u8 bits; |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 1068 | u32 len; |
Matthias Brugger | b9d228f | 2010-10-13 17:51:02 +0200 | [diff] [blame] | 1069 | struct atmel_spi_device *asd; |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 1070 | int timeout; |
| 1071 | int ret; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1072 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 1073 | as = spi_master_get_devdata(master); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1074 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 1075 | if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) { |
| 1076 | dev_dbg(&spi->dev, "missing rx or tx buf\n"); |
| 1077 | return -EINVAL; |
| 1078 | } |
| 1079 | |
| 1080 | if (xfer->bits_per_word) { |
| 1081 | asd = spi->controller_state; |
| 1082 | bits = (asd->csr >> 4) & 0xf; |
| 1083 | if (bits != xfer->bits_per_word - 8) { |
| 1084 | dev_dbg(&spi->dev, |
| 1085 | "you can't yet change bits_per_word in transfers\n"); |
| 1086 | return -ENOPROTOOPT; |
| 1087 | } |
| 1088 | } |
| 1089 | |
| 1090 | if (xfer->bits_per_word > 8) { |
| 1091 | if (xfer->len % 2) { |
| 1092 | dev_dbg(&spi->dev, |
| 1093 | "buffer len should be 16 bits aligned\n"); |
| 1094 | return -EINVAL; |
| 1095 | } |
| 1096 | } |
| 1097 | |
| 1098 | /* |
| 1099 | * DMA map early, for performance (empties dcache ASAP) and |
| 1100 | * better fault reporting. |
| 1101 | */ |
| 1102 | if ((!msg->is_dma_mapped) |
| 1103 | && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) { |
| 1104 | if (atmel_spi_dma_map_xfer(as, xfer) < 0) |
| 1105 | return -ENOMEM; |
| 1106 | } |
| 1107 | |
| 1108 | atmel_spi_set_xfer_speed(as, msg->spi, xfer); |
| 1109 | |
| 1110 | as->done_status = 0; |
| 1111 | as->current_transfer = xfer; |
| 1112 | as->current_remaining_bytes = xfer->len; |
| 1113 | while (as->current_remaining_bytes) { |
| 1114 | reinit_completion(&as->xfer_completion); |
| 1115 | |
| 1116 | if (as->use_pdc) { |
| 1117 | atmel_spi_pdc_next_xfer(master, msg, xfer); |
| 1118 | } else if (atmel_spi_use_dma(as, xfer)) { |
| 1119 | len = as->current_remaining_bytes; |
| 1120 | ret = atmel_spi_next_xfer_dma_submit(master, |
| 1121 | xfer, &len); |
| 1122 | if (ret) { |
| 1123 | dev_err(&spi->dev, |
| 1124 | "unable to use DMA, fallback to PIO\n"); |
| 1125 | atmel_spi_next_xfer_pio(master, xfer); |
| 1126 | } else { |
| 1127 | as->current_remaining_bytes -= len; |
| 1128 | } |
| 1129 | } else { |
| 1130 | atmel_spi_next_xfer_pio(master, xfer); |
| 1131 | } |
| 1132 | |
| 1133 | ret = wait_for_completion_timeout(&as->xfer_completion, |
| 1134 | SPI_DMA_TIMEOUT); |
| 1135 | if (WARN_ON(ret == 0)) { |
| 1136 | dev_err(&spi->dev, |
| 1137 | "spi trasfer timeout, err %d\n", ret); |
| 1138 | as->done_status = -EIO; |
| 1139 | } else { |
| 1140 | ret = 0; |
| 1141 | } |
| 1142 | |
| 1143 | if (as->done_status) |
| 1144 | break; |
| 1145 | } |
| 1146 | |
| 1147 | if (as->done_status) { |
| 1148 | if (as->use_pdc) { |
| 1149 | dev_warn(master->dev.parent, |
| 1150 | "overrun (%u/%u remaining)\n", |
| 1151 | spi_readl(as, TCR), spi_readl(as, RCR)); |
| 1152 | |
| 1153 | /* |
| 1154 | * Clean up DMA registers and make sure the data |
| 1155 | * registers are empty. |
| 1156 | */ |
| 1157 | spi_writel(as, RNCR, 0); |
| 1158 | spi_writel(as, TNCR, 0); |
| 1159 | spi_writel(as, RCR, 0); |
| 1160 | spi_writel(as, TCR, 0); |
| 1161 | for (timeout = 1000; timeout; timeout--) |
| 1162 | if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) |
| 1163 | break; |
| 1164 | if (!timeout) |
| 1165 | dev_warn(master->dev.parent, |
| 1166 | "timeout waiting for TXEMPTY"); |
| 1167 | while (spi_readl(as, SR) & SPI_BIT(RDRF)) |
| 1168 | spi_readl(as, RDR); |
| 1169 | |
| 1170 | /* Clear any overrun happening while cleaning up */ |
| 1171 | spi_readl(as, SR); |
| 1172 | |
| 1173 | } else if (atmel_spi_use_dma(as, xfer)) { |
| 1174 | atmel_spi_stop_dma(as); |
| 1175 | } |
| 1176 | |
| 1177 | if (!msg->is_dma_mapped |
| 1178 | && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) |
| 1179 | atmel_spi_dma_unmap_xfer(master, xfer); |
| 1180 | |
| 1181 | return 0; |
| 1182 | |
| 1183 | } else { |
| 1184 | /* only update length if no error */ |
| 1185 | msg->actual_length += xfer->len; |
| 1186 | } |
| 1187 | |
| 1188 | if (!msg->is_dma_mapped |
| 1189 | && (atmel_spi_use_dma(as, xfer) || as->use_pdc)) |
| 1190 | atmel_spi_dma_unmap_xfer(master, xfer); |
| 1191 | |
| 1192 | if (xfer->delay_usecs) |
| 1193 | udelay(xfer->delay_usecs); |
| 1194 | |
| 1195 | if (xfer->cs_change) { |
| 1196 | if (list_is_last(&xfer->transfer_list, |
| 1197 | &msg->transfers)) { |
| 1198 | as->keep_cs = true; |
| 1199 | } else { |
| 1200 | as->cs_active = !as->cs_active; |
| 1201 | if (as->cs_active) |
| 1202 | cs_activate(as, msg->spi); |
| 1203 | else |
| 1204 | cs_deactivate(as, msg->spi); |
| 1205 | } |
| 1206 | } |
| 1207 | |
| 1208 | return 0; |
| 1209 | } |
| 1210 | |
| 1211 | static int atmel_spi_transfer_one_message(struct spi_master *master, |
| 1212 | struct spi_message *msg) |
| 1213 | { |
| 1214 | struct atmel_spi *as; |
| 1215 | struct spi_transfer *xfer; |
| 1216 | struct spi_device *spi = msg->spi; |
| 1217 | int ret = 0; |
| 1218 | |
| 1219 | as = spi_master_get_devdata(master); |
| 1220 | |
| 1221 | dev_dbg(&spi->dev, "new message %p submitted for %s\n", |
| 1222 | msg, dev_name(&spi->dev)); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1223 | |
Stanislaw Gruszka | 5b96f17 | 2009-01-15 13:50:44 -0800 | [diff] [blame] | 1224 | if (unlikely(list_empty(&msg->transfers))) |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1225 | return -EINVAL; |
| 1226 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 1227 | atmel_spi_lock(as); |
| 1228 | cs_activate(as, spi); |
| 1229 | |
| 1230 | as->cs_active = true; |
| 1231 | as->keep_cs = false; |
| 1232 | |
| 1233 | msg->status = 0; |
| 1234 | msg->actual_length = 0; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1235 | |
| 1236 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 1237 | ret = atmel_spi_one_transfer(master, msg, xfer); |
| 1238 | if (ret) |
| 1239 | goto msg_done; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1240 | } |
| 1241 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 1242 | if (as->use_pdc) |
| 1243 | atmel_spi_disable_pdc_transfer(as); |
| 1244 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1245 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 1246 | dev_dbg(&spi->dev, |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1247 | " xfer %p: len %u tx %p/%08x rx %p/%08x\n", |
| 1248 | xfer, xfer->len, |
| 1249 | xfer->tx_buf, xfer->tx_dma, |
| 1250 | xfer->rx_buf, xfer->rx_dma); |
| 1251 | } |
| 1252 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 1253 | msg_done: |
| 1254 | if (!as->keep_cs) |
| 1255 | cs_deactivate(as, msg->spi); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1256 | |
Nicolas Ferre | 8aad792 | 2013-04-03 13:58:36 +0800 | [diff] [blame] | 1257 | atmel_spi_unlock(as); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1258 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 1259 | msg->status = as->done_status; |
| 1260 | spi_finalize_current_message(spi->master); |
| 1261 | |
| 1262 | return ret; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1263 | } |
| 1264 | |
David Brownell | bb2d1c3 | 2007-02-20 13:58:19 -0800 | [diff] [blame] | 1265 | static void atmel_spi_cleanup(struct spi_device *spi) |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1266 | { |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 1267 | struct atmel_spi_device *asd = spi->controller_state; |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 1268 | unsigned gpio = (unsigned) spi->controller_data; |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 1269 | |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 1270 | if (!asd) |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 1271 | return; |
| 1272 | |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 1273 | spi->controller_state = NULL; |
David Brownell | defbd3b | 2007-07-17 04:04:08 -0700 | [diff] [blame] | 1274 | gpio_free(gpio); |
Haavard Skinnemoen | 5ee36c9 | 2009-01-06 14:41:43 -0800 | [diff] [blame] | 1275 | kfree(asd); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1276 | } |
| 1277 | |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 1278 | static inline unsigned int atmel_get_version(struct atmel_spi *as) |
| 1279 | { |
| 1280 | return spi_readl(as, VERSION) & 0x00000fff; |
| 1281 | } |
| 1282 | |
| 1283 | static void atmel_get_caps(struct atmel_spi *as) |
| 1284 | { |
| 1285 | unsigned int version; |
| 1286 | |
| 1287 | version = atmel_get_version(as); |
| 1288 | dev_info(&as->pdev->dev, "version: 0x%x\n", version); |
| 1289 | |
| 1290 | as->caps.is_spi2 = version > 0x121; |
| 1291 | as->caps.has_wdrbt = version >= 0x210; |
| 1292 | as->caps.has_dma_support = version >= 0x212; |
| 1293 | } |
| 1294 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1295 | /*-------------------------------------------------------------------------*/ |
| 1296 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1297 | static int atmel_spi_probe(struct platform_device *pdev) |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1298 | { |
| 1299 | struct resource *regs; |
| 1300 | int irq; |
| 1301 | struct clk *clk; |
| 1302 | int ret; |
| 1303 | struct spi_master *master; |
| 1304 | struct atmel_spi *as; |
| 1305 | |
| 1306 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1307 | if (!regs) |
| 1308 | return -ENXIO; |
| 1309 | |
| 1310 | irq = platform_get_irq(pdev, 0); |
| 1311 | if (irq < 0) |
| 1312 | return irq; |
| 1313 | |
Jingoo Han | 9f87d6f | 2013-12-04 14:07:51 +0900 | [diff] [blame] | 1314 | clk = devm_clk_get(&pdev->dev, "spi_clk"); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1315 | if (IS_ERR(clk)) |
| 1316 | return PTR_ERR(clk); |
| 1317 | |
| 1318 | /* setup spi core then atmel-specific driver state */ |
| 1319 | ret = -ENOMEM; |
Sachin Kamat | a536d76 | 2013-09-10 17:06:27 +0530 | [diff] [blame] | 1320 | master = spi_alloc_master(&pdev->dev, sizeof(*as)); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1321 | if (!master) |
| 1322 | goto out_free; |
| 1323 | |
David Brownell | e7db06b | 2009-06-17 16:26:04 -0700 | [diff] [blame] | 1324 | /* the spi->mode bits understood by this driver: */ |
| 1325 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 1326 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16); |
Jean-Christophe PLAGNIOL-VILLARD | 850a5b6 | 2012-11-23 13:44:39 +0100 | [diff] [blame] | 1327 | master->dev.of_node = pdev->dev.of_node; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1328 | master->bus_num = pdev->id; |
Jean-Christophe PLAGNIOL-VILLARD | 850a5b6 | 2012-11-23 13:44:39 +0100 | [diff] [blame] | 1329 | master->num_chipselect = master->dev.of_node ? 0 : 4; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1330 | master->setup = atmel_spi_setup; |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 1331 | master->transfer_one_message = atmel_spi_transfer_one_message; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1332 | master->cleanup = atmel_spi_cleanup; |
| 1333 | platform_set_drvdata(pdev, master); |
| 1334 | |
| 1335 | as = spi_master_get_devdata(master); |
| 1336 | |
David Brownell | 8da0859 | 2007-07-17 04:04:07 -0700 | [diff] [blame] | 1337 | /* |
| 1338 | * Scratch buffer is used for throwaway rx and tx data. |
| 1339 | * It's coherent to minimize dcache pollution. |
| 1340 | */ |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1341 | as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE, |
| 1342 | &as->buffer_dma, GFP_KERNEL); |
| 1343 | if (!as->buffer) |
| 1344 | goto out_free; |
| 1345 | |
| 1346 | spin_lock_init(&as->lock); |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 1347 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1348 | as->pdev = pdev; |
Mark Brown | 3140747 | 2013-10-16 13:22:35 +0100 | [diff] [blame] | 1349 | as->regs = devm_ioremap_resource(&pdev->dev, regs); |
Wei Yongjun | 543c954 | 2013-10-21 11:12:02 +0800 | [diff] [blame] | 1350 | if (IS_ERR(as->regs)) { |
| 1351 | ret = PTR_ERR(as->regs); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1352 | goto out_free_buffer; |
Wei Yongjun | 543c954 | 2013-10-21 11:12:02 +0800 | [diff] [blame] | 1353 | } |
Nicolas Ferre | dfab30e | 2013-04-03 13:57:42 +0800 | [diff] [blame] | 1354 | as->phybase = regs->start; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1355 | as->irq = irq; |
| 1356 | as->clk = clk; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1357 | |
Wenyou Yang | 8090d6d | 2014-01-09 13:19:15 +0800 | [diff] [blame] | 1358 | init_completion(&as->xfer_completion); |
| 1359 | |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 1360 | atmel_get_caps(as); |
| 1361 | |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 1362 | as->use_dma = false; |
| 1363 | as->use_pdc = false; |
| 1364 | if (as->caps.has_dma_support) { |
| 1365 | if (atmel_spi_configure_dma(as) == 0) |
| 1366 | as->use_dma = true; |
| 1367 | } else { |
| 1368 | as->use_pdc = true; |
| 1369 | } |
| 1370 | |
| 1371 | if (as->caps.has_dma_support && !as->use_dma) |
| 1372 | dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n"); |
| 1373 | |
| 1374 | if (as->use_pdc) { |
Jingoo Han | 9f87d6f | 2013-12-04 14:07:51 +0900 | [diff] [blame] | 1375 | ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt, |
| 1376 | 0, dev_name(&pdev->dev), master); |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 1377 | } else { |
Jingoo Han | 9f87d6f | 2013-12-04 14:07:51 +0900 | [diff] [blame] | 1378 | ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt, |
| 1379 | 0, dev_name(&pdev->dev), master); |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 1380 | } |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1381 | if (ret) |
| 1382 | goto out_unmap_regs; |
| 1383 | |
| 1384 | /* Initialize the hardware */ |
Boris BREZILLON | dfec4a6 | 2013-07-16 17:16:22 +0200 | [diff] [blame] | 1385 | ret = clk_prepare_enable(clk); |
| 1386 | if (ret) |
Sachin Kamat | de8cc23 | 2013-09-10 17:06:26 +0530 | [diff] [blame] | 1387 | goto out_free_irq; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1388 | spi_writel(as, CR, SPI_BIT(SWRST)); |
Jean-Christophe Lallemand | 50d7d5b | 2008-11-12 13:27:00 -0800 | [diff] [blame] | 1389 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
Wenyou Yang | d4820b7 | 2013-03-19 15:42:15 +0800 | [diff] [blame] | 1390 | if (as->caps.has_wdrbt) { |
| 1391 | spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) |
| 1392 | | SPI_BIT(MSTR)); |
| 1393 | } else { |
| 1394 | spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); |
| 1395 | } |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 1396 | |
| 1397 | if (as->use_pdc) |
| 1398 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1399 | spi_writel(as, CR, SPI_BIT(SPIEN)); |
| 1400 | |
| 1401 | /* go! */ |
| 1402 | dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n", |
| 1403 | (unsigned long)regs->start, irq); |
| 1404 | |
Jingoo Han | 9f87d6f | 2013-12-04 14:07:51 +0900 | [diff] [blame] | 1405 | ret = devm_spi_register_master(&pdev->dev, master); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1406 | if (ret) |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 1407 | goto out_free_dma; |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1408 | |
| 1409 | return 0; |
| 1410 | |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 1411 | out_free_dma: |
| 1412 | if (as->use_dma) |
| 1413 | atmel_spi_release_dma(as); |
| 1414 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1415 | spi_writel(as, CR, SPI_BIT(SWRST)); |
Jean-Christophe Lallemand | 50d7d5b | 2008-11-12 13:27:00 -0800 | [diff] [blame] | 1416 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
Boris BREZILLON | dfec4a6 | 2013-07-16 17:16:22 +0200 | [diff] [blame] | 1417 | clk_disable_unprepare(clk); |
Sachin Kamat | de8cc23 | 2013-09-10 17:06:26 +0530 | [diff] [blame] | 1418 | out_free_irq: |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1419 | out_unmap_regs: |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1420 | out_free_buffer: |
| 1421 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, |
| 1422 | as->buffer_dma); |
| 1423 | out_free: |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1424 | spi_master_put(master); |
| 1425 | return ret; |
| 1426 | } |
| 1427 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1428 | static int atmel_spi_remove(struct platform_device *pdev) |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1429 | { |
| 1430 | struct spi_master *master = platform_get_drvdata(pdev); |
| 1431 | struct atmel_spi *as = spi_master_get_devdata(master); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1432 | |
| 1433 | /* reset the hardware and block queue progress */ |
| 1434 | spin_lock_irq(&as->lock); |
Nicolas Ferre | 1ccc404 | 2013-04-03 13:59:19 +0800 | [diff] [blame] | 1435 | if (as->use_dma) { |
| 1436 | atmel_spi_stop_dma(as); |
| 1437 | atmel_spi_release_dma(as); |
| 1438 | } |
| 1439 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1440 | spi_writel(as, CR, SPI_BIT(SWRST)); |
Jean-Christophe Lallemand | 50d7d5b | 2008-11-12 13:27:00 -0800 | [diff] [blame] | 1441 | spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1442 | spi_readl(as, SR); |
| 1443 | spin_unlock_irq(&as->lock); |
| 1444 | |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1445 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, |
| 1446 | as->buffer_dma); |
| 1447 | |
Boris BREZILLON | dfec4a6 | 2013-07-16 17:16:22 +0200 | [diff] [blame] | 1448 | clk_disable_unprepare(as->clk); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1449 | |
| 1450 | return 0; |
| 1451 | } |
| 1452 | |
Jingoo Han | ec60dd3 | 2013-09-09 17:54:12 +0900 | [diff] [blame] | 1453 | #ifdef CONFIG_PM_SLEEP |
| 1454 | static int atmel_spi_suspend(struct device *dev) |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1455 | { |
Jingoo Han | ec60dd3 | 2013-09-09 17:54:12 +0900 | [diff] [blame] | 1456 | struct spi_master *master = dev_get_drvdata(dev); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1457 | struct atmel_spi *as = spi_master_get_devdata(master); |
| 1458 | |
Boris BREZILLON | dfec4a6 | 2013-07-16 17:16:22 +0200 | [diff] [blame] | 1459 | clk_disable_unprepare(as->clk); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1460 | return 0; |
| 1461 | } |
| 1462 | |
Jingoo Han | ec60dd3 | 2013-09-09 17:54:12 +0900 | [diff] [blame] | 1463 | static int atmel_spi_resume(struct device *dev) |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1464 | { |
Jingoo Han | ec60dd3 | 2013-09-09 17:54:12 +0900 | [diff] [blame] | 1465 | struct spi_master *master = dev_get_drvdata(dev); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1466 | struct atmel_spi *as = spi_master_get_devdata(master); |
| 1467 | |
Jingoo Han | ec60dd3 | 2013-09-09 17:54:12 +0900 | [diff] [blame] | 1468 | clk_prepare_enable(as->clk); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1469 | return 0; |
| 1470 | } |
| 1471 | |
Jingoo Han | ec60dd3 | 2013-09-09 17:54:12 +0900 | [diff] [blame] | 1472 | static SIMPLE_DEV_PM_OPS(atmel_spi_pm_ops, atmel_spi_suspend, atmel_spi_resume); |
| 1473 | |
| 1474 | #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops) |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1475 | #else |
Jingoo Han | ec60dd3 | 2013-09-09 17:54:12 +0900 | [diff] [blame] | 1476 | #define ATMEL_SPI_PM_OPS NULL |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1477 | #endif |
| 1478 | |
Jean-Christophe PLAGNIOL-VILLARD | 850a5b6 | 2012-11-23 13:44:39 +0100 | [diff] [blame] | 1479 | #if defined(CONFIG_OF) |
| 1480 | static const struct of_device_id atmel_spi_dt_ids[] = { |
| 1481 | { .compatible = "atmel,at91rm9200-spi" }, |
| 1482 | { /* sentinel */ } |
| 1483 | }; |
| 1484 | |
| 1485 | MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids); |
| 1486 | #endif |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1487 | |
| 1488 | static struct platform_driver atmel_spi_driver = { |
| 1489 | .driver = { |
| 1490 | .name = "atmel_spi", |
| 1491 | .owner = THIS_MODULE, |
Jingoo Han | ec60dd3 | 2013-09-09 17:54:12 +0900 | [diff] [blame] | 1492 | .pm = ATMEL_SPI_PM_OPS, |
Jean-Christophe PLAGNIOL-VILLARD | 850a5b6 | 2012-11-23 13:44:39 +0100 | [diff] [blame] | 1493 | .of_match_table = of_match_ptr(atmel_spi_dt_ids), |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1494 | }, |
Jean-Christophe PLAGNIOL-VILLARD | 1cb201a | 2011-11-04 01:20:21 +0800 | [diff] [blame] | 1495 | .probe = atmel_spi_probe, |
Grant Likely | 2deff8d | 2013-02-05 13:27:35 +0000 | [diff] [blame] | 1496 | .remove = atmel_spi_remove, |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1497 | }; |
Grant Likely | 940ab88 | 2011-10-05 11:29:49 -0600 | [diff] [blame] | 1498 | module_platform_driver(atmel_spi_driver); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1499 | |
| 1500 | MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); |
Jean Delvare | e05503e | 2011-05-18 16:49:24 +0200 | [diff] [blame] | 1501 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
Haavard Skinnemoen | 754ce4f | 2007-02-14 00:33:09 -0800 | [diff] [blame] | 1502 | MODULE_LICENSE("GPL"); |
Kay Sievers | 7e38c3c | 2008-04-10 21:29:20 -0700 | [diff] [blame] | 1503 | MODULE_ALIAS("platform:atmel_spi"); |