Oded Gabbay | 839c480 | 2019-02-16 00:39:16 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 |
| 2 | * |
| 3 | * Copyright 2016-2018 HabanaLabs, Ltd. |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef ARMCP_IF_H |
| 9 | #define ARMCP_IF_H |
| 10 | |
| 11 | #include <linux/types.h> |
| 12 | |
Oded Gabbay | 1251f23 | 2019-02-16 00:39:18 +0200 | [diff] [blame] | 13 | /* |
| 14 | * EVENT QUEUE |
| 15 | */ |
| 16 | |
| 17 | struct hl_eq_header { |
| 18 | __le32 reserved; |
| 19 | __le32 ctl; |
| 20 | }; |
| 21 | |
| 22 | struct hl_eq_entry { |
| 23 | struct hl_eq_header hdr; |
| 24 | __le64 data[7]; |
| 25 | }; |
| 26 | |
| 27 | #define HL_EQ_ENTRY_SIZE sizeof(struct hl_eq_entry) |
| 28 | |
| 29 | #define EQ_CTL_READY_SHIFT 31 |
| 30 | #define EQ_CTL_READY_MASK 0x80000000 |
| 31 | |
| 32 | #define EQ_CTL_EVENT_TYPE_SHIFT 16 |
| 33 | #define EQ_CTL_EVENT_TYPE_MASK 0x03FF0000 |
| 34 | |
Oded Gabbay | 9494a8d | 2019-02-16 00:39:17 +0200 | [diff] [blame] | 35 | enum pq_init_status { |
| 36 | PQ_INIT_STATUS_NA = 0, |
| 37 | PQ_INIT_STATUS_READY_FOR_CP, |
| 38 | PQ_INIT_STATUS_READY_FOR_HOST |
| 39 | }; |
| 40 | |
| 41 | /* |
| 42 | * ArmCP Primary Queue Packets |
| 43 | * |
| 44 | * During normal operation, KMD needs to send various messages to ArmCP, |
| 45 | * usually either to SET some value into a H/W periphery or to GET the current |
| 46 | * value of some H/W periphery. For example, SET the frequency of MME/TPC and |
| 47 | * GET the value of the thermal sensor. |
| 48 | * |
| 49 | * These messages can be initiated either by the User application or by KMD |
| 50 | * itself, e.g. power management code. In either case, the communication from |
| 51 | * KMD to ArmCP will *always* be in synchronous mode, meaning that KMD will |
| 52 | * send a single message and poll until the message was acknowledged and the |
| 53 | * results are ready (if results are needed). |
| 54 | * |
| 55 | * This means that only a single message can be sent at a time and KMD must |
| 56 | * wait for its result before sending the next message. Having said that, |
| 57 | * because these are control messages which are sent in a relatively low |
| 58 | * frequency, this limitation seems acceptable. It's important to note that |
| 59 | * in case of multiple devices, messages to different devices *can* be sent |
| 60 | * at the same time. |
| 61 | * |
| 62 | * The message, inputs/outputs (if relevant) and fence object will be located |
| 63 | * on the device DDR at an address that will be determined by KMD. During |
| 64 | * device initialization phase, KMD will pass to ArmCP that address. Most of |
| 65 | * the message types will contain inputs/outputs inside the message itself. |
| 66 | * The common part of each message will contain the opcode of the message (its |
| 67 | * type) and a field representing a fence object. |
| 68 | * |
| 69 | * When KMD wishes to send a message to ArmCP, it will write the message |
| 70 | * contents to the device DDR, clear the fence object and then write the |
| 71 | * value 484 to the mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR register to issue |
| 72 | * the 484 interrupt-id to the ARM core. |
| 73 | * |
| 74 | * Upon receiving the 484 interrupt-id, ArmCP will read the message from the |
| 75 | * DDR. In case the message is a SET operation, ArmCP will first perform the |
| 76 | * operation and then write to the fence object on the device DDR. In case the |
| 77 | * message is a GET operation, ArmCP will first fill the results section on the |
| 78 | * device DDR and then write to the fence object. If an error occurred, ArmCP |
| 79 | * will fill the rc field with the right error code. |
| 80 | * |
| 81 | * In the meantime, KMD will poll on the fence object. Once KMD sees that the |
| 82 | * fence object is signaled, it will read the results from the device DDR |
| 83 | * (if relevant) and resume the code execution in KMD. |
| 84 | * |
| 85 | * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8 |
| 86 | * so the value being put by the KMD matches the value read by ArmCP |
| 87 | * |
| 88 | * Non-QMAN packets should be limited to values 1 through (2^8 - 1) |
| 89 | * |
| 90 | * Detailed description: |
| 91 | * |
| 92 | * ARMCP_PACKET_DISABLE_PCI_ACCESS - |
| 93 | * After receiving this packet the embedded CPU must NOT issue PCI |
| 94 | * transactions (read/write) towards the Host CPU. This also include |
| 95 | * sending MSI-X interrupts. |
| 96 | * This packet is usually sent before the device is moved to D3Hot state. |
| 97 | * |
| 98 | * ARMCP_PACKET_ENABLE_PCI_ACCESS - |
| 99 | * After receiving this packet the embedded CPU is allowed to issue PCI |
| 100 | * transactions towards the Host CPU, including sending MSI-X interrupts. |
| 101 | * This packet is usually send after the device is moved to D0 state. |
| 102 | * |
| 103 | * ARMCP_PACKET_TEMPERATURE_GET - |
| 104 | * Fetch the current temperature / Max / Max Hyst / Critical / |
| 105 | * Critical Hyst of a specified thermal sensor. The packet's |
| 106 | * arguments specify the desired sensor and the field to get. |
| 107 | * |
| 108 | * ARMCP_PACKET_VOLTAGE_GET - |
| 109 | * Fetch the voltage / Max / Min of a specified sensor. The packet's |
| 110 | * arguments specify the sensor and type. |
| 111 | * |
| 112 | * ARMCP_PACKET_CURRENT_GET - |
| 113 | * Fetch the current / Max / Min of a specified sensor. The packet's |
| 114 | * arguments specify the sensor and type. |
| 115 | * |
| 116 | * ARMCP_PACKET_FAN_SPEED_GET - |
| 117 | * Fetch the speed / Max / Min of a specified fan. The packet's |
| 118 | * arguments specify the sensor and type. |
| 119 | * |
| 120 | * ARMCP_PACKET_PWM_GET - |
| 121 | * Fetch the pwm value / mode of a specified pwm. The packet's |
| 122 | * arguments specify the sensor and type. |
| 123 | * |
| 124 | * ARMCP_PACKET_PWM_SET - |
| 125 | * Set the pwm value / mode of a specified pwm. The packet's |
| 126 | * arguments specify the sensor, type and value. |
| 127 | * |
| 128 | * ARMCP_PACKET_FREQUENCY_SET - |
| 129 | * Set the frequency of a specified PLL. The packet's arguments specify |
| 130 | * the PLL and the desired frequency. The actual frequency in the device |
| 131 | * might differ from the requested frequency. |
| 132 | * |
| 133 | * ARMCP_PACKET_FREQUENCY_GET - |
| 134 | * Fetch the frequency of a specified PLL. The packet's arguments specify |
| 135 | * the PLL. |
| 136 | * |
| 137 | * ARMCP_PACKET_LED_SET - |
| 138 | * Set the state of a specified led. The packet's arguments |
| 139 | * specify the led and the desired state. |
| 140 | * |
| 141 | * ARMCP_PACKET_I2C_WR - |
| 142 | * Write 32-bit value to I2C device. The packet's arguments specify the |
| 143 | * I2C bus, address and value. |
| 144 | * |
| 145 | * ARMCP_PACKET_I2C_RD - |
| 146 | * Read 32-bit value from I2C device. The packet's arguments specify the |
| 147 | * I2C bus and address. |
| 148 | * |
| 149 | * ARMCP_PACKET_INFO_GET - |
| 150 | * Fetch information from the device as specified in the packet's |
| 151 | * structure. KMD passes the max size it allows the ArmCP to write to |
| 152 | * the structure, to prevent data corruption in case of mismatched |
| 153 | * KMD/FW versions. |
| 154 | * |
| 155 | * ARMCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed |
| 156 | * |
| 157 | * ARMCP_PACKET_UNMASK_RAZWI_IRQ - |
| 158 | * Unmask the given IRQ. The IRQ number is specified in the value field. |
| 159 | * The packet is sent after receiving an interrupt and printing its |
| 160 | * relevant information. |
| 161 | * |
| 162 | * ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY - |
| 163 | * Unmask the given IRQs. The IRQs numbers are specified in an array right |
| 164 | * after the armcp_packet structure, where its first element is the array |
| 165 | * length. The packet is sent after a soft reset was done in order to |
| 166 | * handle any interrupts that were sent during the reset process. |
| 167 | * |
| 168 | * ARMCP_PACKET_TEST - |
| 169 | * Test packet for ArmCP connectivity. The CPU will put the fence value |
| 170 | * in the result field. |
| 171 | * |
| 172 | * ARMCP_PACKET_FREQUENCY_CURR_GET - |
| 173 | * Fetch the current frequency of a specified PLL. The packet's arguments |
| 174 | * specify the PLL. |
| 175 | * |
| 176 | * ARMCP_PACKET_MAX_POWER_GET - |
| 177 | * Fetch the maximal power of the device. |
| 178 | * |
| 179 | * ARMCP_PACKET_MAX_POWER_SET - |
| 180 | * Set the maximal power of the device. The packet's arguments specify |
| 181 | * the power. |
| 182 | * |
| 183 | * ARMCP_PACKET_EEPROM_DATA_GET - |
| 184 | * Get EEPROM data from the ArmCP kernel. The buffer is specified in the |
| 185 | * addr field. The CPU will put the returned data size in the result |
| 186 | * field. In addition, KMD passes the max size it allows the ArmCP to |
| 187 | * write to the structure, to prevent data corruption in case of |
| 188 | * mismatched KMD/FW versions. |
| 189 | * |
| 190 | */ |
| 191 | |
| 192 | enum armcp_packet_id { |
| 193 | ARMCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */ |
| 194 | ARMCP_PACKET_ENABLE_PCI_ACCESS, /* internal */ |
| 195 | ARMCP_PACKET_TEMPERATURE_GET, /* sysfs */ |
| 196 | ARMCP_PACKET_VOLTAGE_GET, /* sysfs */ |
| 197 | ARMCP_PACKET_CURRENT_GET, /* sysfs */ |
| 198 | ARMCP_PACKET_FAN_SPEED_GET, /* sysfs */ |
| 199 | ARMCP_PACKET_PWM_GET, /* sysfs */ |
| 200 | ARMCP_PACKET_PWM_SET, /* sysfs */ |
| 201 | ARMCP_PACKET_FREQUENCY_SET, /* sysfs */ |
| 202 | ARMCP_PACKET_FREQUENCY_GET, /* sysfs */ |
| 203 | ARMCP_PACKET_LED_SET, /* debugfs */ |
| 204 | ARMCP_PACKET_I2C_WR, /* debugfs */ |
| 205 | ARMCP_PACKET_I2C_RD, /* debugfs */ |
| 206 | ARMCP_PACKET_INFO_GET, /* IOCTL */ |
| 207 | ARMCP_PACKET_FLASH_PROGRAM_REMOVED, |
| 208 | ARMCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */ |
| 209 | ARMCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */ |
| 210 | ARMCP_PACKET_TEST, /* internal */ |
| 211 | ARMCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */ |
| 212 | ARMCP_PACKET_MAX_POWER_GET, /* sysfs */ |
| 213 | ARMCP_PACKET_MAX_POWER_SET, /* sysfs */ |
| 214 | ARMCP_PACKET_EEPROM_DATA_GET, /* sysfs */ |
| 215 | }; |
| 216 | |
| 217 | #define ARMCP_PACKET_FENCE_VAL 0xFE8CE7A5 |
| 218 | |
| 219 | #define ARMCP_PKT_CTL_RC_SHIFT 12 |
| 220 | #define ARMCP_PKT_CTL_RC_MASK 0x0000F000 |
| 221 | |
| 222 | #define ARMCP_PKT_CTL_OPCODE_SHIFT 16 |
| 223 | #define ARMCP_PKT_CTL_OPCODE_MASK 0x1FFF0000 |
| 224 | |
| 225 | struct armcp_packet { |
| 226 | union { |
| 227 | __le64 value; /* For SET packets */ |
| 228 | __le64 result; /* For GET packets */ |
| 229 | __le64 addr; /* For PQ */ |
| 230 | }; |
| 231 | |
| 232 | __le32 ctl; |
| 233 | |
| 234 | __le32 fence; /* Signal to KMD that message is completed */ |
| 235 | |
| 236 | union { |
| 237 | struct {/* For temperature/current/voltage/fan/pwm get/set */ |
| 238 | __le16 sensor_index; |
| 239 | __le16 type; |
| 240 | }; |
| 241 | |
| 242 | struct { /* For I2C read/write */ |
| 243 | __u8 i2c_bus; |
| 244 | __u8 i2c_addr; |
| 245 | __u8 i2c_reg; |
| 246 | __u8 pad; /* unused */ |
| 247 | }; |
| 248 | |
| 249 | /* For frequency get/set */ |
| 250 | __le32 pll_index; |
| 251 | |
| 252 | /* For led set */ |
| 253 | __le32 led_index; |
| 254 | |
| 255 | /* For get Armcp info/EEPROM data */ |
| 256 | __le32 data_max_size; |
| 257 | }; |
| 258 | }; |
| 259 | |
| 260 | struct armcp_unmask_irq_arr_packet { |
| 261 | struct armcp_packet armcp_pkt; |
| 262 | __le32 length; |
| 263 | __le32 irqs[0]; |
| 264 | }; |
| 265 | |
| 266 | enum armcp_packet_rc { |
| 267 | armcp_packet_success, |
| 268 | armcp_packet_invalid, |
| 269 | armcp_packet_fault |
| 270 | }; |
| 271 | |
| 272 | enum armcp_temp_type { |
| 273 | armcp_temp_input, |
| 274 | armcp_temp_max = 6, |
| 275 | armcp_temp_max_hyst, |
| 276 | armcp_temp_crit, |
| 277 | armcp_temp_crit_hyst |
| 278 | }; |
| 279 | |
| 280 | enum armcp_in_attributes { |
| 281 | armcp_in_input, |
| 282 | armcp_in_min, |
| 283 | armcp_in_max |
| 284 | }; |
| 285 | |
| 286 | enum armcp_curr_attributes { |
| 287 | armcp_curr_input, |
| 288 | armcp_curr_min, |
| 289 | armcp_curr_max |
| 290 | }; |
| 291 | |
| 292 | enum armcp_fan_attributes { |
| 293 | armcp_fan_input, |
| 294 | armcp_fan_min = 2, |
| 295 | armcp_fan_max |
| 296 | }; |
| 297 | |
| 298 | enum armcp_pwm_attributes { |
| 299 | armcp_pwm_input, |
| 300 | armcp_pwm_enable |
| 301 | }; |
| 302 | |
| 303 | /* Event Queue Packets */ |
| 304 | |
| 305 | struct eq_generic_event { |
| 306 | __le64 data[7]; |
| 307 | }; |
| 308 | |
Oded Gabbay | 839c480 | 2019-02-16 00:39:16 +0200 | [diff] [blame] | 309 | /* |
| 310 | * ArmCP info |
| 311 | */ |
| 312 | |
| 313 | #define VERSION_MAX_LEN 128 |
Oded Gabbay | 9494a8d | 2019-02-16 00:39:17 +0200 | [diff] [blame] | 314 | #define ARMCP_MAX_SENSORS 128 |
| 315 | |
| 316 | struct armcp_sensor { |
| 317 | __le32 type; |
| 318 | __le32 flags; |
| 319 | }; |
| 320 | |
| 321 | struct armcp_info { |
| 322 | struct armcp_sensor sensors[ARMCP_MAX_SENSORS]; |
| 323 | __u8 kernel_version[VERSION_MAX_LEN]; |
| 324 | __le32 reserved[3]; |
| 325 | __le32 cpld_version; |
| 326 | __le32 infineon_version; |
| 327 | __u8 fuse_version[VERSION_MAX_LEN]; |
| 328 | __u8 thermal_version[VERSION_MAX_LEN]; |
| 329 | __u8 armcp_version[VERSION_MAX_LEN]; |
| 330 | __le64 dram_size; |
| 331 | }; |
Oded Gabbay | 839c480 | 2019-02-16 00:39:16 +0200 | [diff] [blame] | 332 | |
| 333 | #endif /* ARMCP_IF_H */ |