blob: c82401570c8432654c53591b3d567b644d93aff9 [file] [log] [blame]
Thomas Gleixnerfcaf2032019-05-27 08:55:08 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Liu Yinga49e6c42013-07-04 17:35:46 +08002/*
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
Liu Yinga49e6c42013-07-04 17:35:46 +08004 */
5
Anson Huang7d6b5e4f2020-08-05 07:17:29 +08006#include <linux/bits.h>
Liu Yinga49e6c42013-07-04 17:35:46 +08007#include <linux/clk-provider.h>
8#include <linux/err.h>
9#include <linux/io.h>
10#include <linux/slab.h>
11#include "clk.h"
12
Liu Yinga49e6c42013-07-04 17:35:46 +080013/**
14 * struct clk_fixup_mux - imx integer fixup multiplexer clock
15 * @mux: the parent class
16 * @ops: pointer to clk_ops of parent class
17 * @fixup: a hook to fixup the write value
18 *
19 * The imx fixup multiplexer clock is a subclass of basic clk_mux
20 * with an addtional fixup hook.
21 */
22struct clk_fixup_mux {
23 struct clk_mux mux;
24 const struct clk_ops *ops;
25 void (*fixup)(u32 *val);
26};
27
28static inline struct clk_fixup_mux *to_clk_fixup_mux(struct clk_hw *hw)
29{
30 struct clk_mux *mux = to_clk_mux(hw);
31
32 return container_of(mux, struct clk_fixup_mux, mux);
33}
34
35static u8 clk_fixup_mux_get_parent(struct clk_hw *hw)
36{
37 struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
38
39 return fixup_mux->ops->get_parent(&fixup_mux->mux.hw);
40}
41
42static int clk_fixup_mux_set_parent(struct clk_hw *hw, u8 index)
43{
44 struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
45 struct clk_mux *mux = to_clk_mux(hw);
Anson Huang79ccef62020-02-12 17:03:00 +080046 unsigned long flags;
Liu Yinga49e6c42013-07-04 17:35:46 +080047 u32 val;
48
49 spin_lock_irqsave(mux->lock, flags);
50
51 val = readl(mux->reg);
52 val &= ~(mux->mask << mux->shift);
53 val |= index << mux->shift;
54 fixup_mux->fixup(&val);
55 writel(val, mux->reg);
56
57 spin_unlock_irqrestore(mux->lock, flags);
58
59 return 0;
60}
61
62static const struct clk_ops clk_fixup_mux_ops = {
63 .get_parent = clk_fixup_mux_get_parent,
64 .set_parent = clk_fixup_mux_set_parent,
65};
66
Abel Vesa3ead0f12019-05-29 12:26:44 +000067struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
A.s. Dong9e5ef7a2018-11-14 13:02:00 +000068 u8 shift, u8 width, const char * const *parents,
Liu Yinga49e6c42013-07-04 17:35:46 +080069 int num_parents, void (*fixup)(u32 *val))
70{
71 struct clk_fixup_mux *fixup_mux;
Abel Vesa3ead0f12019-05-29 12:26:44 +000072 struct clk_hw *hw;
Liu Yinga49e6c42013-07-04 17:35:46 +080073 struct clk_init_data init;
Abel Vesa3ead0f12019-05-29 12:26:44 +000074 int ret;
Liu Yinga49e6c42013-07-04 17:35:46 +080075
76 if (!fixup)
77 return ERR_PTR(-EINVAL);
78
79 fixup_mux = kzalloc(sizeof(*fixup_mux), GFP_KERNEL);
80 if (!fixup_mux)
81 return ERR_PTR(-ENOMEM);
82
83 init.name = name;
84 init.ops = &clk_fixup_mux_ops;
85 init.parent_names = parents;
86 init.num_parents = num_parents;
Shawn Guobdb1b5f2013-09-04 20:49:04 +080087 init.flags = 0;
Liu Yinga49e6c42013-07-04 17:35:46 +080088
89 fixup_mux->mux.reg = reg;
90 fixup_mux->mux.shift = shift;
91 fixup_mux->mux.mask = BIT(width) - 1;
92 fixup_mux->mux.lock = &imx_ccm_lock;
93 fixup_mux->mux.hw.init = &init;
94 fixup_mux->ops = &clk_mux_ops;
95 fixup_mux->fixup = fixup;
96
Abel Vesa3ead0f12019-05-29 12:26:44 +000097 hw = &fixup_mux->mux.hw;
Liu Yinga49e6c42013-07-04 17:35:46 +080098
Abel Vesa3ead0f12019-05-29 12:26:44 +000099 ret = clk_hw_register(NULL, hw);
100 if (ret) {
101 kfree(fixup_mux);
102 return ERR_PTR(ret);
103 }
104
105 return hw;
Liu Yinga49e6c42013-07-04 17:35:46 +0800106}