Thomas Gleixner | 2874c5f | 2019-05-27 08:55:01 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 2 | /* |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 3 | * PowerPC version |
| 4 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
| 5 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP |
| 6 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> |
| 7 | * Low-level exception handlers and MMU support |
| 8 | * rewritten by Paul Mackerras. |
| 9 | * Copyright (C) 1996 Paul Mackerras. |
| 10 | * MPC8xx modifications by Dan Malek |
| 11 | * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). |
| 12 | * |
| 13 | * This file contains low-level support and setup for PowerPC 8xx |
| 14 | * embedded processors, including trap and interrupt dispatch. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 15 | */ |
| 16 | |
Tim Abbott | e703984 | 2009-04-25 22:11:05 -0400 | [diff] [blame] | 17 | #include <linux/init.h> |
Christophe Leroy | 3bbd234 | 2019-08-21 10:20:51 +0000 | [diff] [blame] | 18 | #include <linux/magic.h> |
Mike Rapoport | 65fddcf | 2020-06-08 21:32:42 -0700 | [diff] [blame] | 19 | #include <linux/pgtable.h> |
Christophe Leroy | f76c8f6 | 2020-05-19 05:49:13 +0000 | [diff] [blame] | 20 | #include <linux/sizes.h> |
Christophe Leroy | 2da37761 | 2022-11-14 23:27:44 +0530 | [diff] [blame] | 21 | #include <linux/linkage.h> |
| 22 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 23 | #include <asm/processor.h> |
| 24 | #include <asm/page.h> |
| 25 | #include <asm/mmu.h> |
| 26 | #include <asm/cache.h> |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 27 | #include <asm/cputable.h> |
| 28 | #include <asm/thread_info.h> |
| 29 | #include <asm/ppc_asm.h> |
| 30 | #include <asm/asm-offsets.h> |
Stephen Rothwell | 46f5221 | 2010-11-18 15:06:17 +0000 | [diff] [blame] | 31 | #include <asm/ptrace.h> |
Christophe Leroy | 1a21087 | 2018-10-19 06:55:06 +0000 | [diff] [blame] | 32 | #include <asm/code-patching-asm.h> |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 33 | #include <asm/interrupt.h> |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 34 | |
Christophe Leroy | 5b1c9a0d | 2021-03-12 12:50:23 +0000 | [diff] [blame] | 35 | /* |
| 36 | * Value for the bits that have fixed value in RPN entries. |
| 37 | * Also used for tagging DAR for DTLBerror. |
| 38 | */ |
| 39 | #define RPN_PATTERN 0x00f0 |
| 40 | |
Christophe Leroy | 8a23fdec | 2019-04-30 12:38:50 +0000 | [diff] [blame] | 41 | #include "head_32.h" |
| 42 | |
Christophe Leroy | 4b914286 | 2016-12-07 08:47:28 +0100 | [diff] [blame] | 43 | #define PAGE_SHIFT_512K 19 |
| 44 | #define PAGE_SHIFT_8M 23 |
| 45 | |
Tim Abbott | e703984 | 2009-04-25 22:11:05 -0400 | [diff] [blame] | 46 | __HEAD |
Christophe Leroy | 27e21e8 | 2021-11-30 13:04:50 +0100 | [diff] [blame] | 47 | _GLOBAL(_stext); |
| 48 | _GLOBAL(_start); |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 49 | |
| 50 | /* MPC8xx |
| 51 | * This port was done on an MBX board with an 860. Right now I only |
| 52 | * support an ELF compressed (zImage) boot from EPPC-Bug because the |
| 53 | * code there loads up some registers before calling us: |
| 54 | * r3: ptr to board info data |
| 55 | * r4: initrd_start or if no initrd then 0 |
| 56 | * r5: initrd_end - unused if r4 is 0 |
| 57 | * r6: Start of command line string |
| 58 | * r7: End of command line string |
| 59 | * |
| 60 | * I decided to use conditional compilation instead of checking PVR and |
| 61 | * adding more processor specific branches around code I don't need. |
| 62 | * Since this is an embedded processor, I also appreciate any memory |
| 63 | * savings I can get. |
| 64 | * |
| 65 | * The MPC8xx does not have any BATs, but it supports large page sizes. |
| 66 | * We first initialize the MMU to support 8M byte pages, then load one |
| 67 | * entry into each of the instruction and data TLBs to map the first |
| 68 | * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to |
| 69 | * the "internal" processor registers before MMU_init is called. |
| 70 | * |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 71 | * -- Dan |
| 72 | */ |
| 73 | .globl __start |
| 74 | __start: |
Scott Wood | 6dece0eb | 2011-07-25 11:29:33 +0000 | [diff] [blame] | 75 | mr r31,r3 /* save device tree ptr */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 76 | |
| 77 | /* We have to turn on the MMU right away so we get cache modes |
| 78 | * set correctly. |
| 79 | */ |
| 80 | bl initial_mmu |
| 81 | |
| 82 | /* We now have the lower 8 Meg mapped into TLB entries, and the caches |
| 83 | * ready to work. |
| 84 | */ |
| 85 | |
| 86 | turn_on_mmu: |
| 87 | mfmsr r0 |
| 88 | ori r0,r0,MSR_DR|MSR_IR |
| 89 | mtspr SPRN_SRR1,r0 |
| 90 | lis r0,start_here@h |
| 91 | ori r0,r0,start_here@l |
| 92 | mtspr SPRN_SRR0,r0 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 93 | rfi /* enables MMU */ |
| 94 | |
Christophe Leroy | 8cfe4f5 | 2018-11-29 14:07:11 +0000 | [diff] [blame] | 95 | |
| 96 | #ifdef CONFIG_PERF_EVENTS |
| 97 | .align 4 |
| 98 | |
| 99 | .globl itlb_miss_counter |
| 100 | itlb_miss_counter: |
| 101 | .space 4 |
| 102 | |
| 103 | .globl dtlb_miss_counter |
| 104 | dtlb_miss_counter: |
| 105 | .space 4 |
| 106 | |
| 107 | .globl instruction_counter |
| 108 | instruction_counter: |
| 109 | .space 4 |
| 110 | #endif |
| 111 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 112 | /* System reset */ |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 113 | EXCEPTION(INTERRUPT_SYSTEM_RESET, Reset, system_reset_exception) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 114 | |
| 115 | /* Machine check */ |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 116 | START_EXCEPTION(INTERRUPT_MACHINE_CHECK, MachineCheck) |
| 117 | EXCEPTION_PROLOG INTERRUPT_MACHINE_CHECK MachineCheck handle_dar_dsisr=1 |
Christophe Leroy | 4c0104a | 2021-03-12 12:50:41 +0000 | [diff] [blame] | 118 | prepare_transfer_to_handler |
| 119 | bl machine_check_exception |
| 120 | b interrupt_return |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 121 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 122 | /* External interrupt */ |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 123 | EXCEPTION(INTERRUPT_EXTERNAL, HardwareInterrupt, do_IRQ) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 124 | |
| 125 | /* Alignment exception */ |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 126 | START_EXCEPTION(INTERRUPT_ALIGNMENT, Alignment) |
| 127 | EXCEPTION_PROLOG INTERRUPT_ALIGNMENT Alignment handle_dar_dsisr=1 |
Christophe Leroy | 8f6ff5b | 2021-03-12 12:50:40 +0000 | [diff] [blame] | 128 | prepare_transfer_to_handler |
| 129 | bl alignment_exception |
| 130 | REST_NVGPRS(r1) |
| 131 | b interrupt_return |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 132 | |
| 133 | /* Program check exception */ |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 134 | START_EXCEPTION(INTERRUPT_PROGRAM, ProgramCheck) |
| 135 | EXCEPTION_PROLOG INTERRUPT_PROGRAM ProgramCheck |
Christophe Leroy | 8f6ff5b | 2021-03-12 12:50:40 +0000 | [diff] [blame] | 136 | prepare_transfer_to_handler |
| 137 | bl program_check_exception |
| 138 | REST_NVGPRS(r1) |
| 139 | b interrupt_return |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 140 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 141 | /* Decrementer */ |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 142 | EXCEPTION(INTERRUPT_DECREMENTER, Decrementer, timer_interrupt) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 143 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 144 | /* System call */ |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 145 | START_EXCEPTION(INTERRUPT_SYSCALL, SystemCall) |
| 146 | SYSCALL_ENTRY INTERRUPT_SYSCALL |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 147 | |
| 148 | /* Single step - not used on 601 */ |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 149 | EXCEPTION(INTERRUPT_TRACE, SingleStep, single_step_exception) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 150 | |
| 151 | /* On the MPC8xx, this is a software emulation interrupt. It occurs |
| 152 | * for all unimplemented and illegal instructions. |
| 153 | */ |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 154 | START_EXCEPTION(INTERRUPT_SOFT_EMU_8xx, SoftEmu) |
| 155 | EXCEPTION_PROLOG INTERRUPT_SOFT_EMU_8xx SoftEmu |
Christophe Leroy | 8f6ff5b | 2021-03-12 12:50:40 +0000 | [diff] [blame] | 156 | prepare_transfer_to_handler |
| 157 | bl emulation_assist_interrupt |
| 158 | REST_NVGPRS(r1) |
| 159 | b interrupt_return |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 160 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 161 | /* |
| 162 | * For the MPC8xx, this is a software tablewalk to load the instruction |
Christophe Leroy | 6a8f911 | 2018-11-29 14:07:15 +0000 | [diff] [blame] | 163 | * TLB. The task switch loads the M_TWB register with the pointer to the first |
LEROY Christophe | cbc130f | 2014-09-19 10:36:08 +0200 | [diff] [blame] | 164 | * level table. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 165 | * If we discover there is no second level table (value is zero) or if there |
| 166 | * is an invalid pte, we load that into the TLB, which causes another fault |
| 167 | * into the TLB Error interrupt where we can handle such problems. |
| 168 | * We have to use the MD_xxx registers for the tablewalk because the |
| 169 | * equivalent MI_xxx registers only perform the attribute functions. |
| 170 | */ |
LEROY Christophe | 90883a8 | 2015-04-20 07:54:38 +0200 | [diff] [blame] | 171 | |
| 172 | #ifdef CONFIG_8xx_CPU15 |
Christophe Leroy | 576e02b | 2020-11-24 15:24:56 +0000 | [diff] [blame] | 173 | #define INVALIDATE_ADJACENT_PAGES_CPU15(addr, tmp) \ |
| 174 | addi tmp, addr, PAGE_SIZE; \ |
| 175 | tlbie tmp; \ |
| 176 | addi tmp, addr, -PAGE_SIZE; \ |
| 177 | tlbie tmp |
LEROY Christophe | 90883a8 | 2015-04-20 07:54:38 +0200 | [diff] [blame] | 178 | #else |
Christophe Leroy | 576e02b | 2020-11-24 15:24:56 +0000 | [diff] [blame] | 179 | #define INVALIDATE_ADJACENT_PAGES_CPU15(addr, tmp) |
LEROY Christophe | 90883a8 | 2015-04-20 07:54:38 +0200 | [diff] [blame] | 180 | #endif |
| 181 | |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 182 | START_EXCEPTION(INTERRUPT_INST_TLB_MISS_8xx, InstructionTLBMiss) |
Christophe Leroy | a314ea5 | 2020-11-24 15:24:57 +0000 | [diff] [blame] | 183 | mtspr SPRN_SPRG_SCRATCH2, r10 |
| 184 | mtspr SPRN_M_TW, r11 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 185 | |
| 186 | /* If we are faulting a kernel address, we have to use the |
| 187 | * kernel page tables. |
| 188 | */ |
Christophe Leroy | d1b9f81 | 2016-09-16 08:42:04 +0200 | [diff] [blame] | 189 | mfspr r10, SPRN_SRR0 /* Get effective address of fault */ |
Christophe Leroy | 576e02b | 2020-11-24 15:24:56 +0000 | [diff] [blame] | 190 | INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11) |
Christophe Leroy | 6a8f911 | 2018-11-29 14:07:15 +0000 | [diff] [blame] | 191 | mtspr SPRN_MD_EPN, r10 |
Christophe Leroy | 74fabca | 2018-11-29 14:07:24 +0000 | [diff] [blame] | 192 | mfspr r10, SPRN_M_TWB /* Get level 1 table */ |
Christophe Leroy | a891c43 | 2020-05-19 05:49:08 +0000 | [diff] [blame] | 193 | lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */ |
Christophe Leroy | a891c43 | 2020-05-19 05:49:08 +0000 | [diff] [blame] | 194 | mtspr SPRN_MD_TWC, r11 |
Christophe Leroy | a891c43 | 2020-05-19 05:49:08 +0000 | [diff] [blame] | 195 | mfspr r10, SPRN_MD_TWC |
| 196 | lwz r10, 0(r10) /* Get the pte */ |
Christophe Leroy | 33fe43c | 2020-10-12 08:54:33 +0000 | [diff] [blame] | 197 | rlwimi r11, r10, 0, _PAGE_GUARDED | _PAGE_ACCESSED |
Christophe Leroy | b250c8c | 2020-05-19 05:49:09 +0000 | [diff] [blame] | 198 | rlwimi r11, r10, 32 - 9, _PMD_PAGE_512K |
| 199 | mtspr SPRN_MI_TWC, r11 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 200 | /* The Linux PTE won't go exactly into the MMU TLB. |
Christophe Leroy | de0f938 | 2018-01-12 13:45:31 +0100 | [diff] [blame] | 201 | * Software indicator bits 20 and 23 must be clear. |
| 202 | * Software indicator bits 22, 24, 25, 26, and 27 must be |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 203 | * set. All other Linux PTE bits control the behavior |
| 204 | * of the MMU. |
| 205 | */ |
Christophe Leroy | a4031afb9 | 2020-02-09 18:14:42 +0000 | [diff] [blame] | 206 | rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */ |
Christophe Leroy | 74fabca | 2018-11-29 14:07:24 +0000 | [diff] [blame] | 207 | rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */ |
| 208 | ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */ |
Christophe Leroy | 2a45add | 2018-01-12 13:45:19 +0100 | [diff] [blame] | 209 | mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 210 | |
Joakim Tjernlund | 469d62b | 2010-03-02 05:37:12 +0000 | [diff] [blame] | 211 | /* Restore registers */ |
Christophe Leroy | a314ea5 | 2020-11-24 15:24:57 +0000 | [diff] [blame] | 212 | 0: mfspr r10, SPRN_SPRG_SCRATCH2 |
| 213 | mfspr r11, SPRN_M_TW |
Christophe Leroy | cd99ddb | 2018-01-12 13:45:23 +0100 | [diff] [blame] | 214 | rfi |
Christophe Leroy | 709cf19 | 2018-10-19 06:55:08 +0000 | [diff] [blame] | 215 | patch_site 0b, patch__itlbmiss_exit_1 |
| 216 | |
Christophe Leroy | cd99ddb | 2018-01-12 13:45:23 +0100 | [diff] [blame] | 217 | #ifdef CONFIG_PERF_EVENTS |
Christophe Leroy | 709cf19 | 2018-10-19 06:55:08 +0000 | [diff] [blame] | 218 | patch_site 0f, patch__itlbmiss_perf |
Christophe Leroy | 8cfe4f5 | 2018-11-29 14:07:11 +0000 | [diff] [blame] | 219 | 0: lwz r10, (itlb_miss_counter - PAGE_OFFSET)@l(0) |
| 220 | addi r10, r10, 1 |
| 221 | stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0) |
Christophe Leroy | a314ea5 | 2020-11-24 15:24:57 +0000 | [diff] [blame] | 222 | mfspr r10, SPRN_SPRG_SCRATCH2 |
| 223 | mfspr r11, SPRN_M_TW |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 224 | rfi |
Christophe Leroy | 8cfe4f5 | 2018-11-29 14:07:11 +0000 | [diff] [blame] | 225 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 226 | |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 227 | START_EXCEPTION(INTERRUPT_DATA_TLB_MISS_8xx, DataStoreTLBMiss) |
Christophe Leroy | 89eecd9 | 2020-11-24 15:24:58 +0000 | [diff] [blame] | 228 | mtspr SPRN_SPRG_SCRATCH2, r10 |
Christophe Leroy | 6edc318 | 2019-12-21 08:32:31 +0000 | [diff] [blame] | 229 | mtspr SPRN_M_TW, r11 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 230 | |
| 231 | /* If we are faulting a kernel address, we have to use the |
| 232 | * kernel page tables. |
| 233 | */ |
Christophe Leroy | 36eb154 | 2016-09-16 08:42:08 +0200 | [diff] [blame] | 234 | mfspr r10, SPRN_MD_EPN |
Christophe Leroy | 74fabca | 2018-11-29 14:07:24 +0000 | [diff] [blame] | 235 | mfspr r10, SPRN_M_TWB /* Get level 1 table */ |
Christophe Leroy | 74fabca | 2018-11-29 14:07:24 +0000 | [diff] [blame] | 236 | lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 237 | |
Christophe Leroy | 6a8f911 | 2018-11-29 14:07:15 +0000 | [diff] [blame] | 238 | mtspr SPRN_MD_TWC, r11 |
| 239 | mfspr r10, SPRN_MD_TWC |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 240 | lwz r10, 0(r10) /* Get the pte */ |
Christophe Leroy | 6a8f911 | 2018-11-29 14:07:15 +0000 | [diff] [blame] | 241 | |
Christophe Leroy | 33fe43c | 2020-10-12 08:54:33 +0000 | [diff] [blame] | 242 | /* Insert Guarded and Accessed flags into the TWC from the Linux PTE. |
Christophe Leroy | de0f938 | 2018-01-12 13:45:31 +0100 | [diff] [blame] | 243 | * It is bit 27 of both the Linux PTE and the TWC (at least |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 244 | * I got that right :-). It will be better when we can put |
| 245 | * this into the Linux pgd/pmd and load it in the operation |
| 246 | * above. |
| 247 | */ |
Christophe Leroy | 33fe43c | 2020-10-12 08:54:33 +0000 | [diff] [blame] | 248 | rlwimi r11, r10, 0, _PAGE_GUARDED | _PAGE_ACCESSED |
Christophe Leroy | b250c8c | 2020-05-19 05:49:09 +0000 | [diff] [blame] | 249 | rlwimi r11, r10, 32 - 9, _PMD_PAGE_512K |
Christophe Leroy | 2a45add | 2018-01-12 13:45:19 +0100 | [diff] [blame] | 250 | mtspr SPRN_MD_TWC, r11 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 251 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 252 | /* The Linux PTE won't go exactly into the MMU TLB. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 253 | * Software indicator bits 24, 25, 26, and 27 must be |
| 254 | * set. All other Linux PTE bits control the behavior |
| 255 | * of the MMU. |
| 256 | */ |
LEROY Christophe | 5ddb75c | 2015-01-20 10:57:33 +0100 | [diff] [blame] | 257 | li r11, RPN_PATTERN |
Christophe Leroy | 4b914286 | 2016-12-07 08:47:28 +0100 | [diff] [blame] | 258 | rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */ |
Christophe Leroy | 2a45add | 2018-01-12 13:45:19 +0100 | [diff] [blame] | 259 | mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ |
Christophe Leroy | 89eecd9 | 2020-11-24 15:24:58 +0000 | [diff] [blame] | 260 | mtspr SPRN_DAR, r11 /* Tag DAR */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 261 | |
Joakim Tjernlund | 469d62b | 2010-03-02 05:37:12 +0000 | [diff] [blame] | 262 | /* Restore registers */ |
Christophe Leroy | 709cf19 | 2018-10-19 06:55:08 +0000 | [diff] [blame] | 263 | |
Christophe Leroy | 89eecd9 | 2020-11-24 15:24:58 +0000 | [diff] [blame] | 264 | 0: mfspr r10, SPRN_SPRG_SCRATCH2 |
Christophe Leroy | 6edc318 | 2019-12-21 08:32:31 +0000 | [diff] [blame] | 265 | mfspr r11, SPRN_M_TW |
Christophe Leroy | cd99ddb | 2018-01-12 13:45:23 +0100 | [diff] [blame] | 266 | rfi |
Christophe Leroy | 709cf19 | 2018-10-19 06:55:08 +0000 | [diff] [blame] | 267 | patch_site 0b, patch__dtlbmiss_exit_1 |
| 268 | |
Christophe Leroy | 0c8c2c9 | 2020-05-19 05:49:18 +0000 | [diff] [blame] | 269 | #ifdef CONFIG_PERF_EVENTS |
| 270 | patch_site 0f, patch__dtlbmiss_perf |
| 271 | 0: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) |
| 272 | addi r10, r10, 1 |
| 273 | stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0) |
Christophe Leroy | 89eecd9 | 2020-11-24 15:24:58 +0000 | [diff] [blame] | 274 | mfspr r10, SPRN_SPRG_SCRATCH2 |
Christophe Leroy | 0c8c2c9 | 2020-05-19 05:49:18 +0000 | [diff] [blame] | 275 | mfspr r11, SPRN_M_TW |
| 276 | rfi |
| 277 | #endif |
| 278 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 279 | /* This is an instruction TLB error on the MPC8xx. This could be due |
| 280 | * to many reasons, such as executing guarded memory or illegal instruction |
| 281 | * addresses. There is nothing to do but handle a big time error fault. |
| 282 | */ |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 283 | START_EXCEPTION(INTERRUPT_INST_TLB_ERROR_8xx, InstructionTLBError) |
Christophe Leroy | 719e7e2 | 2021-03-12 12:50:38 +0000 | [diff] [blame] | 284 | /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 285 | EXCEPTION_PROLOG INTERRUPT_INST_STORAGE InstructionTLBError |
Benjamin Herrenschmidt | b4c001d | 2017-07-19 14:49:28 +1000 | [diff] [blame] | 286 | andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */ |
| 287 | andis. r10,r9,SRR1_ISI_NOPT@h |
Christophe Leroy | 32ceaa6 | 2018-12-13 08:08:11 +0000 | [diff] [blame] | 288 | beq+ .Litlbie |
Nicholas Piggin | a01a3f2 | 2021-01-30 23:08:16 +1000 | [diff] [blame] | 289 | tlbie r12 |
Christophe Leroy | 32ceaa6 | 2018-12-13 08:08:11 +0000 | [diff] [blame] | 290 | .Litlbie: |
Nicholas Piggin | a01a3f2 | 2021-01-30 23:08:16 +1000 | [diff] [blame] | 291 | stw r12, _DAR(r11) |
| 292 | stw r5, _DSISR(r11) |
Christophe Leroy | 4c0104a | 2021-03-12 12:50:41 +0000 | [diff] [blame] | 293 | prepare_transfer_to_handler |
| 294 | bl do_page_fault |
| 295 | b interrupt_return |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 296 | |
| 297 | /* This is the data TLB error on the MPC8xx. This could be due to |
LEROY Christophe | 140a6a6 | 2014-08-29 11:14:38 +0200 | [diff] [blame] | 298 | * many reasons, including a dirty update to a pte. We bail out to |
| 299 | * a higher level function that can handle it. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 300 | */ |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 301 | START_EXCEPTION(INTERRUPT_DATA_TLB_ERROR_8xx, DataTLBError) |
Christophe Leroy | 99b2291 | 2019-12-21 08:32:35 +0000 | [diff] [blame] | 302 | EXCEPTION_PROLOG_0 handle_dar_dsisr=1 |
LEROY Christophe | 5bcbe24 | 2014-08-29 11:14:38 +0200 | [diff] [blame] | 303 | mfspr r11, SPRN_DAR |
Christophe Leroy | 5ae8fab | 2019-12-21 08:32:25 +0000 | [diff] [blame] | 304 | cmpwi cr1, r11, RPN_PATTERN |
| 305 | beq- cr1, FixupDAR /* must be a buggy dcbX, icbi insn. */ |
LEROY Christophe | 3e43640 | 2014-08-29 11:14:37 +0200 | [diff] [blame] | 306 | DARFixed:/* Return from dcbx instruction bug workaround */ |
Christophe Leroy | ac9f97f | 2024-08-20 19:23:53 +0200 | [diff] [blame] | 307 | mfspr r11, SPRN_DSISR |
| 308 | rlwinm r11, r11, 0, DSISR_NOHPTE |
| 309 | cmpwi cr1, r11, 0 |
| 310 | beq+ cr1, .Ldtlbie |
| 311 | mfspr r11, SPRN_DAR |
| 312 | tlbie r11 |
| 313 | rlwinm r11, r11, 16, 0xffff |
| 314 | cmplwi cr1, r11, TASK_SIZE@h |
| 315 | bge- cr1, FixupPGD |
| 316 | .Ldtlbie: |
LEROY Christophe | 6cde2b6 | 2014-09-19 10:36:08 +0200 | [diff] [blame] | 317 | EXCEPTION_PROLOG_1 |
Christophe Leroy | 719e7e2 | 2021-03-12 12:50:38 +0000 | [diff] [blame] | 318 | /* 0x300 is DataAccess exception, needed by bad_page_fault() */ |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 319 | EXCEPTION_PROLOG_2 INTERRUPT_DATA_STORAGE DataTLBError handle_dar_dsisr=1 |
Christophe Leroy | 4c0104a | 2021-03-12 12:50:41 +0000 | [diff] [blame] | 320 | prepare_transfer_to_handler |
| 321 | bl do_page_fault |
| 322 | b interrupt_return |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 323 | |
Christophe Leroy | 5b5e5bc | 2021-03-12 12:50:27 +0000 | [diff] [blame] | 324 | #ifdef CONFIG_VMAP_STACK |
Christophe Leroy | 99b2291 | 2019-12-21 08:32:35 +0000 | [diff] [blame] | 325 | vmap_stack_overflow_exception |
Christophe Leroy | 5b5e5bc | 2021-03-12 12:50:27 +0000 | [diff] [blame] | 326 | #endif |
Christophe Leroy | 99b2291 | 2019-12-21 08:32:35 +0000 | [diff] [blame] | 327 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 328 | /* On the MPC8xx, these next four traps are used for development |
| 329 | * support of breakpoints and such. Someday I will get around to |
| 330 | * using them. |
| 331 | */ |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 332 | START_EXCEPTION(INTERRUPT_DATA_BREAKPOINT_8xx, DataBreakpoint) |
Christophe Leroy | 99b2291 | 2019-12-21 08:32:35 +0000 | [diff] [blame] | 333 | EXCEPTION_PROLOG_0 handle_dar_dsisr=1 |
Christophe Leroy | afe1ec5 | 2019-12-21 08:32:34 +0000 | [diff] [blame] | 334 | mfspr r11, SPRN_SRR0 |
| 335 | cmplwi cr1, r11, (.Ldtlbie - PAGE_OFFSET)@l |
| 336 | cmplwi cr7, r11, (.Litlbie - PAGE_OFFSET)@l |
| 337 | cror 4*cr1+eq, 4*cr1+eq, 4*cr7+eq |
Christophe Leroy | dc13b88 | 2021-03-12 12:50:29 +0000 | [diff] [blame] | 338 | bne cr1, 1f |
Christophe Leroy | 4ad8622 | 2016-11-29 09:52:15 +0100 | [diff] [blame] | 339 | mtcr r10 |
Christophe Leroy | bb9b5a8 | 2018-01-12 13:45:21 +0100 | [diff] [blame] | 340 | mfspr r10, SPRN_SPRG_SCRATCH0 |
| 341 | mfspr r11, SPRN_SPRG_SCRATCH1 |
Christophe Leroy | 4ad8622 | 2016-11-29 09:52:15 +0100 | [diff] [blame] | 342 | rfi |
| 343 | |
Christophe Leroy | dc13b88 | 2021-03-12 12:50:29 +0000 | [diff] [blame] | 344 | 1: EXCEPTION_PROLOG_1 |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 345 | EXCEPTION_PROLOG_2 INTERRUPT_DATA_BREAKPOINT_8xx DataBreakpoint handle_dar_dsisr=1 |
Christophe Leroy | dc13b88 | 2021-03-12 12:50:29 +0000 | [diff] [blame] | 346 | mfspr r4,SPRN_BAR |
| 347 | stw r4,_DAR(r11) |
Christophe Leroy | 8f6ff5b | 2021-03-12 12:50:40 +0000 | [diff] [blame] | 348 | prepare_transfer_to_handler |
| 349 | bl do_break |
| 350 | REST_NVGPRS(r1) |
| 351 | b interrupt_return |
Christophe Leroy | dc13b88 | 2021-03-12 12:50:29 +0000 | [diff] [blame] | 352 | |
Christophe Leroy | cd99ddb | 2018-01-12 13:45:23 +0100 | [diff] [blame] | 353 | #ifdef CONFIG_PERF_EVENTS |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 354 | START_EXCEPTION(INTERRUPT_INST_BREAKPOINT_8xx, InstructionBreakpoint) |
Christophe Leroy | bb9b5a8 | 2018-01-12 13:45:21 +0100 | [diff] [blame] | 355 | mtspr SPRN_SPRG_SCRATCH0, r10 |
Christophe Leroy | 8cfe4f5 | 2018-11-29 14:07:11 +0000 | [diff] [blame] | 356 | lwz r10, (instruction_counter - PAGE_OFFSET)@l(0) |
| 357 | addi r10, r10, -1 |
| 358 | stw r10, (instruction_counter - PAGE_OFFSET)@l(0) |
Christophe Leroy | 75b8247 | 2016-12-15 13:42:18 +0100 | [diff] [blame] | 359 | lis r10, 0xffff |
| 360 | ori r10, r10, 0x01 |
| 361 | mtspr SPRN_COUNTA, r10 |
Christophe Leroy | bb9b5a8 | 2018-01-12 13:45:21 +0100 | [diff] [blame] | 362 | mfspr r10, SPRN_SPRG_SCRATCH0 |
Christophe Leroy | 75b8247 | 2016-12-15 13:42:18 +0100 | [diff] [blame] | 363 | rfi |
| 364 | #else |
Christophe Leroy | 0f5eb28 | 2021-04-19 15:48:09 +0000 | [diff] [blame] | 365 | EXCEPTION(INTERRUPT_INST_BREAKPOINT_8xx, Trap_1d, unknown_exception) |
Christophe Leroy | 75b8247 | 2016-12-15 13:42:18 +0100 | [diff] [blame] | 366 | #endif |
Christophe Leroy | acc142b | 2021-03-12 12:50:42 +0000 | [diff] [blame] | 367 | EXCEPTION(0x1e00, Trap_1e, unknown_exception) |
| 368 | EXCEPTION(0x1f00, Trap_1f, unknown_exception) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 369 | |
Christophe Leroy | dc13b88 | 2021-03-12 12:50:29 +0000 | [diff] [blame] | 370 | __HEAD |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 371 | . = 0x2000 |
| 372 | |
Christophe Leroy | ac9f97f | 2024-08-20 19:23:53 +0200 | [diff] [blame] | 373 | FixupPGD: |
| 374 | mtspr SPRN_M_TW, r10 |
| 375 | mfspr r10, SPRN_DAR |
| 376 | mtspr SPRN_MD_EPN, r10 |
| 377 | mfspr r11, SPRN_M_TWB /* Get level 1 table */ |
| 378 | lwz r10, (swapper_pg_dir - PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ |
| 379 | cmpwi cr1, r10, 0 |
| 380 | bne cr1, 1f |
| 381 | |
| 382 | rlwinm r10, r11, 0, 20, 31 |
| 383 | oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha |
| 384 | lwz r10, (swapper_pg_dir - PAGE_OFFSET)@l(r10) /* Get the level 1 entry */ |
| 385 | cmpwi cr1, r10, 0 |
| 386 | beq cr1, 1f |
| 387 | stw r10, (swapper_pg_dir - PAGE_OFFSET)@l(r11) /* Set the level 1 entry */ |
| 388 | mfspr r10, SPRN_M_TW |
| 389 | mtcr r10 |
| 390 | mfspr r10, SPRN_SPRG_SCRATCH0 |
| 391 | mfspr r11, SPRN_SPRG_SCRATCH1 |
| 392 | rfi |
| 393 | 1: |
| 394 | mfspr r10, SPRN_M_TW |
| 395 | b .Ldtlbie |
| 396 | |
Joakim Tjernlund | 0a2ab51 | 2009-11-20 00:21:06 +0000 | [diff] [blame] | 397 | /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions |
| 398 | * by decoding the registers used by the dcbx instruction and adding them. |
LEROY Christophe | 3e43640 | 2014-08-29 11:14:37 +0200 | [diff] [blame] | 399 | * DAR is set to the calculated address. |
Joakim Tjernlund | 0a2ab51 | 2009-11-20 00:21:06 +0000 | [diff] [blame] | 400 | */ |
Joakim Tjernlund | 0a2ab51 | 2009-11-20 00:21:06 +0000 | [diff] [blame] | 401 | FixupDAR:/* Entry point for dcbx workaround. */ |
Christophe Leroy | 74fabca | 2018-11-29 14:07:24 +0000 | [diff] [blame] | 402 | mtspr SPRN_M_TW, r10 |
Joakim Tjernlund | 0a2ab51 | 2009-11-20 00:21:06 +0000 | [diff] [blame] | 403 | /* fetch instruction from memory. */ |
| 404 | mfspr r10, SPRN_SRR0 |
Christophe Leroy | 6a8f911 | 2018-11-29 14:07:15 +0000 | [diff] [blame] | 405 | mtspr SPRN_MD_EPN, r10 |
Christophe Leroy | c8a1270 | 2017-07-12 12:08:47 +0200 | [diff] [blame] | 406 | rlwinm r11, r10, 16, 0xfff8 |
Christophe Leroy | 65a82e1 | 2024-08-20 19:23:46 +0200 | [diff] [blame] | 407 | cmpli cr1, r11, TASK_SIZE@h |
Christophe Leroy | 6a8f911 | 2018-11-29 14:07:15 +0000 | [diff] [blame] | 408 | mfspr r11, SPRN_M_TWB /* Get level 1 table */ |
Christophe Leroy | 5ae8fab | 2019-12-21 08:32:25 +0000 | [diff] [blame] | 409 | blt+ cr1, 3f |
Christophe Leroy | 1a21087 | 2018-10-19 06:55:06 +0000 | [diff] [blame] | 410 | |
Christophe Leroy | 36eb154 | 2016-09-16 08:42:08 +0200 | [diff] [blame] | 411 | /* create physical page address from effective address */ |
| 412 | tophys(r11, r10) |
Christophe Leroy | 6a8f911 | 2018-11-29 14:07:15 +0000 | [diff] [blame] | 413 | mfspr r11, SPRN_M_TWB /* Get level 1 table */ |
| 414 | rlwinm r11, r11, 0, 20, 31 |
| 415 | oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha |
| 416 | 3: |
LEROY Christophe | fde5a90 | 2015-01-20 10:57:34 +0100 | [diff] [blame] | 417 | lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */ |
Christophe Leroy | 0549e76 | 2024-07-02 15:51:25 +0200 | [diff] [blame] | 418 | rlwinm r11, r11, 0, ~_PMD_PAGE_8M |
Christophe Leroy | 6a8f911 | 2018-11-29 14:07:15 +0000 | [diff] [blame] | 419 | mtspr SPRN_MD_TWC, r11 |
Christophe Leroy | 6a8f911 | 2018-11-29 14:07:15 +0000 | [diff] [blame] | 420 | mfspr r11, SPRN_MD_TWC |
| 421 | lwz r11, 0(r11) /* Get the pte */ |
Joakim Tjernlund | 0a2ab51 | 2009-11-20 00:21:06 +0000 | [diff] [blame] | 422 | /* concat physical page address(r11) and page offset(r10) */ |
LEROY Christophe | d140680 | 2014-09-19 10:36:09 +0200 | [diff] [blame] | 423 | rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31 |
Christophe Leroy | 0549e76 | 2024-07-02 15:51:25 +0200 | [diff] [blame] | 424 | lwz r11,0(r11) |
Joakim Tjernlund | 0a2ab51 | 2009-11-20 00:21:06 +0000 | [diff] [blame] | 425 | /* Check if it really is a dcbx instruction. */ |
| 426 | /* dcbt and dcbtst does not generate DTLB Misses/Errors, |
| 427 | * no need to include them here */ |
LEROY Christophe | 41cacac | 2014-08-29 11:14:38 +0200 | [diff] [blame] | 428 | xoris r10, r11, 0x7c00 /* check if major OP code is 31 */ |
| 429 | rlwinm r10, r10, 0, 21, 5 |
Christophe Leroy | 5ae8fab | 2019-12-21 08:32:25 +0000 | [diff] [blame] | 430 | cmpwi cr1, r10, 2028 /* Is dcbz? */ |
| 431 | beq+ cr1, 142f |
| 432 | cmpwi cr1, r10, 940 /* Is dcbi? */ |
| 433 | beq+ cr1, 142f |
| 434 | cmpwi cr1, r10, 108 /* Is dcbst? */ |
| 435 | beq+ cr1, 144f /* Fix up store bit! */ |
| 436 | cmpwi cr1, r10, 172 /* Is dcbf? */ |
| 437 | beq+ cr1, 142f |
| 438 | cmpwi cr1, r10, 1964 /* Is icbi? */ |
| 439 | beq+ cr1, 142f |
Christophe Leroy | 74fabca | 2018-11-29 14:07:24 +0000 | [diff] [blame] | 440 | 141: mfspr r10,SPRN_M_TW |
LEROY Christophe | 5bcbe24 | 2014-08-29 11:14:38 +0200 | [diff] [blame] | 441 | b DARFixed /* Nope, go back to normal TLB processing */ |
Joakim Tjernlund | 0a2ab51 | 2009-11-20 00:21:06 +0000 | [diff] [blame] | 442 | |
| 443 | 144: mfspr r10, SPRN_DSISR |
| 444 | rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ |
| 445 | mtspr SPRN_DSISR, r10 |
| 446 | 142: /* continue, it was a dcbx, dcbi instruction. */ |
Joakim Tjernlund | 0a2ab51 | 2009-11-20 00:21:06 +0000 | [diff] [blame] | 447 | mfctr r10 |
| 448 | mtdar r10 /* save ctr reg in DAR */ |
| 449 | rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ |
| 450 | addi r10, r10, 150f@l /* add start of table */ |
| 451 | mtctr r10 /* load ctr with jump address */ |
| 452 | xor r10, r10, r10 /* sum starts at zero */ |
| 453 | bctr /* jump into table */ |
| 454 | 150: |
| 455 | add r10, r10, r0 ;b 151f |
| 456 | add r10, r10, r1 ;b 151f |
| 457 | add r10, r10, r2 ;b 151f |
| 458 | add r10, r10, r3 ;b 151f |
| 459 | add r10, r10, r4 ;b 151f |
| 460 | add r10, r10, r5 ;b 151f |
| 461 | add r10, r10, r6 ;b 151f |
| 462 | add r10, r10, r7 ;b 151f |
| 463 | add r10, r10, r8 ;b 151f |
| 464 | add r10, r10, r9 ;b 151f |
| 465 | mtctr r11 ;b 154f /* r10 needs special handling */ |
| 466 | mtctr r11 ;b 153f /* r11 needs special handling */ |
| 467 | add r10, r10, r12 ;b 151f |
| 468 | add r10, r10, r13 ;b 151f |
| 469 | add r10, r10, r14 ;b 151f |
| 470 | add r10, r10, r15 ;b 151f |
| 471 | add r10, r10, r16 ;b 151f |
| 472 | add r10, r10, r17 ;b 151f |
| 473 | add r10, r10, r18 ;b 151f |
| 474 | add r10, r10, r19 ;b 151f |
| 475 | add r10, r10, r20 ;b 151f |
| 476 | add r10, r10, r21 ;b 151f |
| 477 | add r10, r10, r22 ;b 151f |
| 478 | add r10, r10, r23 ;b 151f |
| 479 | add r10, r10, r24 ;b 151f |
| 480 | add r10, r10, r25 ;b 151f |
| 481 | add r10, r10, r26 ;b 151f |
| 482 | add r10, r10, r27 ;b 151f |
| 483 | add r10, r10, r28 ;b 151f |
| 484 | add r10, r10, r29 ;b 151f |
| 485 | add r10, r10, r30 ;b 151f |
| 486 | add r10, r10, r31 |
| 487 | 151: |
Christophe Leroy | 5ae8fab | 2019-12-21 08:32:25 +0000 | [diff] [blame] | 488 | rlwinm r11,r11,19,24,28 /* offset into jump table for reg RA */ |
| 489 | cmpwi cr1, r11, 0 |
| 490 | beq cr1, 152f /* if reg RA is zero, don't add it */ |
Joakim Tjernlund | 0a2ab51 | 2009-11-20 00:21:06 +0000 | [diff] [blame] | 491 | addi r11, r11, 150b@l /* add start of table */ |
| 492 | mtctr r11 /* load ctr with jump address */ |
| 493 | rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ |
| 494 | bctr /* jump into table */ |
| 495 | 152: |
| 496 | mfdar r11 |
| 497 | mtctr r11 /* restore ctr reg from DAR */ |
Christophe Leroy | 99b2291 | 2019-12-21 08:32:35 +0000 | [diff] [blame] | 498 | mfspr r11, SPRN_SPRG_THREAD |
| 499 | stw r10, DAR(r11) |
| 500 | mfspr r10, SPRN_DSISR |
| 501 | stw r10, DSISR(r11) |
Christophe Leroy | 74fabca | 2018-11-29 14:07:24 +0000 | [diff] [blame] | 502 | mfspr r10,SPRN_M_TW |
Joakim Tjernlund | 0a2ab51 | 2009-11-20 00:21:06 +0000 | [diff] [blame] | 503 | b DARFixed /* Go back to normal TLB handling */ |
| 504 | |
| 505 | /* special handling for r10,r11 since these are modified already */ |
LEROY Christophe | 92625d4 | 2014-08-29 11:14:37 +0200 | [diff] [blame] | 506 | 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */ |
LEROY Christophe | 111e32b | 2014-08-29 11:14:39 +0200 | [diff] [blame] | 507 | add r10, r10, r11 /* add it */ |
| 508 | mfctr r11 /* restore r11 */ |
| 509 | b 151b |
LEROY Christophe | 92625d4 | 2014-08-29 11:14:37 +0200 | [diff] [blame] | 510 | 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */ |
LEROY Christophe | 111e32b | 2014-08-29 11:14:39 +0200 | [diff] [blame] | 511 | add r10, r10, r11 /* add it */ |
Joakim Tjernlund | 0a2ab51 | 2009-11-20 00:21:06 +0000 | [diff] [blame] | 512 | mfctr r11 /* restore r11 */ |
| 513 | b 151b |
Joakim Tjernlund | 0a2ab51 | 2009-11-20 00:21:06 +0000 | [diff] [blame] | 514 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 515 | /* |
| 516 | * This is where the main kernel code starts. |
| 517 | */ |
| 518 | start_here: |
| 519 | /* ptr to current */ |
| 520 | lis r2,init_task@h |
| 521 | ori r2,r2,init_task@l |
| 522 | |
| 523 | /* ptr to phys current thread */ |
| 524 | tophys(r4,r2) |
| 525 | addi r4,r4,THREAD /* init task's THREAD */ |
Benjamin Herrenschmidt | ee43eb7 | 2009-07-14 20:52:54 +0000 | [diff] [blame] | 526 | mtspr SPRN_SPRG_THREAD,r4 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 527 | |
| 528 | /* stack */ |
| 529 | lis r1,init_thread_union@ha |
| 530 | addi r1,r1,init_thread_union@l |
Christophe Leroy | 3bbd234 | 2019-08-21 10:20:51 +0000 | [diff] [blame] | 531 | lis r0, STACK_END_MAGIC@h |
| 532 | ori r0, r0, STACK_END_MAGIC@l |
| 533 | stw r0, 0(r1) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 534 | li r0,0 |
Nicholas Piggin | 90f1b43 | 2022-11-27 22:49:40 +1000 | [diff] [blame] | 535 | stwu r0,THREAD_SIZE-STACK_FRAME_MIN_SIZE(r1) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 536 | |
Christophe Leroy | 8c8c10b | 2018-07-13 13:10:47 +0000 | [diff] [blame] | 537 | lis r6, swapper_pg_dir@ha |
| 538 | tophys(r6,r6) |
Christophe Leroy | 6a8f911 | 2018-11-29 14:07:15 +0000 | [diff] [blame] | 539 | mtspr SPRN_M_TWB, r6 |
Christophe Leroy | 8c8c10b | 2018-07-13 13:10:47 +0000 | [diff] [blame] | 540 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 541 | bl early_init /* We have to do this with MMU on */ |
| 542 | |
| 543 | /* |
| 544 | * Decide what sort of machine this is and initialize the MMU. |
| 545 | */ |
Christophe Leroy | 2edb16e | 2019-04-26 16:23:34 +0000 | [diff] [blame] | 546 | #ifdef CONFIG_KASAN |
| 547 | bl kasan_early_init |
| 548 | #endif |
Scott Wood | 6dece0eb | 2011-07-25 11:29:33 +0000 | [diff] [blame] | 549 | li r3,0 |
| 550 | mr r4,r31 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 551 | bl machine_init |
| 552 | bl MMU_init |
| 553 | |
| 554 | /* |
| 555 | * Go back to running unmapped so we can load up new values |
| 556 | * and change to using our exception vectors. |
| 557 | * On the 8xx, all we have to do is invalidate the TLB to clear |
| 558 | * the old 8M byte TLB mappings and load the page table base register. |
| 559 | */ |
| 560 | /* The right way to do this would be to track it down through |
| 561 | * init's THREAD like the context switch code does, but this is |
| 562 | * easier......until someone changes init's static structures. |
| 563 | */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 564 | lis r4,2f@h |
| 565 | ori r4,r4,2f@l |
| 566 | tophys(r4,r4) |
| 567 | li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) |
| 568 | mtspr SPRN_SRR0,r4 |
| 569 | mtspr SPRN_SRR1,r3 |
| 570 | rfi |
| 571 | /* Load up the kernel context */ |
| 572 | 2: |
Christophe Leroy | 136a9a0 | 2020-05-19 05:49:14 +0000 | [diff] [blame] | 573 | #ifdef CONFIG_PIN_TLB_IMMR |
| 574 | lis r0, MD_TWAM@h |
| 575 | oris r0, r0, 0x1f00 |
| 576 | mtspr SPRN_MD_CTR, r0 |
| 577 | LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE | MD_EVALID) |
| 578 | tlbie r0 |
| 579 | mtspr SPRN_MD_EPN, r0 |
| 580 | LOAD_REG_IMMEDIATE(r0, MD_SVALID | MD_PS512K | MD_GUARDED) |
| 581 | mtspr SPRN_MD_TWC, r0 |
| 582 | mfspr r0, SPRN_IMMR |
| 583 | rlwinm r0, r0, 0, 0xfff80000 |
| 584 | ori r0, r0, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | \ |
| 585 | _PAGE_NO_CACHE | _PAGE_PRESENT |
| 586 | mtspr SPRN_MD_RPN, r0 |
| 587 | lis r0, (MD_TWAM | MD_RSV4I)@h |
| 588 | mtspr SPRN_MD_CTR, r0 |
| 589 | #endif |
Christophe Leroy | 1a736d9 | 2024-08-20 19:23:48 +0200 | [diff] [blame] | 590 | #ifndef CONFIG_PIN_TLB_TEXT |
| 591 | li r0, 0 |
| 592 | mtspr SPRN_MI_CTR, r0 |
| 593 | #endif |
Christophe Leroy | 684c166 | 2020-05-19 05:49:15 +0000 | [diff] [blame] | 594 | #if !defined(CONFIG_PIN_TLB_DATA) && !defined(CONFIG_PIN_TLB_IMMR) |
| 595 | lis r0, MD_TWAM@h |
| 596 | mtspr SPRN_MD_CTR, r0 |
| 597 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 598 | tlbia /* Clear all TLB entries */ |
| 599 | sync /* wait for tlbia/tlbie to finish */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 600 | |
| 601 | /* set up the PTE pointers for the Abatron bdiGDB. |
| 602 | */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 603 | lis r5, abatron_pteptrs@h |
| 604 | ori r5, r5, abatron_pteptrs@l |
Christophe Leroy | e4ccb1d | 2018-05-24 11:02:06 +0000 | [diff] [blame] | 605 | stw r5, 0xf0(0) /* Must match your Abatron config file */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 606 | tophys(r5,r5) |
Christophe Leroy | fb0bdec | 2019-01-09 20:30:07 +0000 | [diff] [blame] | 607 | lis r6, swapper_pg_dir@h |
| 608 | ori r6, r6, swapper_pg_dir@l |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 609 | stw r6, 0(r5) |
| 610 | |
| 611 | /* Now turn on the MMU for real! */ |
| 612 | li r4,MSR_KERNEL |
| 613 | lis r3,start_kernel@h |
| 614 | ori r3,r3,start_kernel@l |
| 615 | mtspr SPRN_SRR0,r3 |
| 616 | mtspr SPRN_SRR1,r4 |
| 617 | rfi /* enable MMU and jump to start_kernel */ |
| 618 | |
| 619 | /* Set up the initial MMU state so we can do the first level of |
| 620 | * kernel initialization. This maps the first 8 MBytes of memory 1:1 |
| 621 | * virtual to physical. Also, set the cache mode since that is defined |
| 622 | * by TLB entries and perform any additional mapping (like of the IMMR). |
| 623 | * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, |
Christophe Leroy | f86ef74 | 2016-05-17 09:02:43 +0200 | [diff] [blame] | 624 | * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 625 | * these mappings is mapped by page tables. |
| 626 | */ |
Christophe Leroy | 2da37761 | 2022-11-14 23:27:44 +0530 | [diff] [blame] | 627 | SYM_FUNC_START_LOCAL(initial_mmu) |
Christophe Leroy | 6264dbb | 2016-05-17 09:02:49 +0200 | [diff] [blame] | 628 | li r8, 0 |
| 629 | mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */ |
Christophe Leroy | d3efcd3 | 2020-05-19 05:49:07 +0000 | [diff] [blame] | 630 | lis r10, MD_TWAM@h |
Christophe Leroy | 6264dbb | 2016-05-17 09:02:49 +0200 | [diff] [blame] | 631 | mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */ |
| 632 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 633 | tlbia /* Invalidate all TLB entries */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 634 | |
LEROY Christophe | 5b2753f | 2015-04-22 12:06:45 +0200 | [diff] [blame] | 635 | lis r8, MI_APG_INIT@h /* Set protection modes */ |
| 636 | ori r8, r8, MI_APG_INIT@l |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 637 | mtspr SPRN_MI_AP, r8 |
LEROY Christophe | 5b2753f | 2015-04-22 12:06:45 +0200 | [diff] [blame] | 638 | lis r8, MD_APG_INIT@h |
| 639 | ori r8, r8, MD_APG_INIT@l |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 640 | mtspr SPRN_MD_AP, r8 |
| 641 | |
Christophe Leroy | 684c166 | 2020-05-19 05:49:15 +0000 | [diff] [blame] | 642 | /* Map the lower RAM (up to 32 Mbytes) into the ITLB and DTLB */ |
Christophe Leroy | e4470bd | 2019-02-13 16:06:21 +0000 | [diff] [blame] | 643 | lis r8, MI_RSV4I@h |
| 644 | ori r8, r8, 0x1c00 |
Christophe Leroy | 684c166 | 2020-05-19 05:49:15 +0000 | [diff] [blame] | 645 | oris r12, r10, MD_RSV4I@h |
| 646 | ori r12, r12, 0x1c00 |
Christophe Leroy | e4470bd | 2019-02-13 16:06:21 +0000 | [diff] [blame] | 647 | li r9, 4 /* up to 4 pages of 8M */ |
| 648 | mtctr r9 |
| 649 | lis r9, KERNELBASE@h /* Create vaddr for TLB */ |
Christophe Leroy | 33fe43c | 2020-10-12 08:54:33 +0000 | [diff] [blame] | 650 | li r10, MI_PS8MEG | _PMD_ACCESSED | MI_SVALID |
Christophe Leroy | e4470bd | 2019-02-13 16:06:21 +0000 | [diff] [blame] | 651 | li r11, MI_BOOTINIT /* Create RPN for address 0 */ |
Christophe Leroy | e4470bd | 2019-02-13 16:06:21 +0000 | [diff] [blame] | 652 | 1: |
Christophe Leroy | e4470bd | 2019-02-13 16:06:21 +0000 | [diff] [blame] | 653 | mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ |
| 654 | addi r8, r8, 0x100 |
Christophe Leroy | e4470bd | 2019-02-13 16:06:21 +0000 | [diff] [blame] | 655 | ori r0, r9, MI_EVALID /* Mark it valid */ |
| 656 | mtspr SPRN_MI_EPN, r0 |
| 657 | mtspr SPRN_MI_TWC, r10 |
| 658 | mtspr SPRN_MI_RPN, r11 /* Store TLB entry */ |
Christophe Leroy | 684c166 | 2020-05-19 05:49:15 +0000 | [diff] [blame] | 659 | mtspr SPRN_MD_CTR, r12 |
| 660 | addi r12, r12, 0x100 |
| 661 | mtspr SPRN_MD_EPN, r0 |
| 662 | mtspr SPRN_MD_TWC, r10 |
| 663 | mtspr SPRN_MD_RPN, r11 |
Christophe Leroy | e4470bd | 2019-02-13 16:06:21 +0000 | [diff] [blame] | 664 | addis r9, r9, 0x80 |
| 665 | addis r11, r11, 0x80 |
| 666 | |
Christophe Leroy | 684c166 | 2020-05-19 05:49:15 +0000 | [diff] [blame] | 667 | bdnz 1b |
Christophe Leroy | e4470bd | 2019-02-13 16:06:21 +0000 | [diff] [blame] | 668 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 669 | /* Since the cache is enabled according to the information we |
| 670 | * just loaded into the TLB, invalidate and enable the caches here. |
| 671 | * We should probably check/set other modes....later. |
| 672 | */ |
| 673 | lis r8, IDC_INVALL@h |
| 674 | mtspr SPRN_IC_CST, r8 |
| 675 | mtspr SPRN_DC_CST, r8 |
| 676 | lis r8, IDC_ENABLE@h |
| 677 | mtspr SPRN_IC_CST, r8 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 678 | mtspr SPRN_DC_CST, r8 |
Christophe Leroy | 75b8247 | 2016-12-15 13:42:18 +0100 | [diff] [blame] | 679 | /* Disable debug mode entry on breakpoints */ |
Christophe Leroy | 4ad8622 | 2016-11-29 09:52:15 +0100 | [diff] [blame] | 680 | mfspr r8, SPRN_DER |
Christophe Leroy | cd99ddb | 2018-01-12 13:45:23 +0100 | [diff] [blame] | 681 | #ifdef CONFIG_PERF_EVENTS |
Christophe Leroy | 75b8247 | 2016-12-15 13:42:18 +0100 | [diff] [blame] | 682 | rlwinm r8, r8, 0, ~0xc |
| 683 | #else |
Christophe Leroy | 4ad8622 | 2016-11-29 09:52:15 +0100 | [diff] [blame] | 684 | rlwinm r8, r8, 0, ~0x8 |
Christophe Leroy | 75b8247 | 2016-12-15 13:42:18 +0100 | [diff] [blame] | 685 | #endif |
Christophe Leroy | 4ad8622 | 2016-11-29 09:52:15 +0100 | [diff] [blame] | 686 | mtspr SPRN_DER, r8 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 687 | blr |
Christophe Leroy | 2da37761 | 2022-11-14 23:27:44 +0530 | [diff] [blame] | 688 | SYM_FUNC_END(initial_mmu) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 689 | |
Christophe Leroy | 1a736d9 | 2024-08-20 19:23:48 +0200 | [diff] [blame] | 690 | #ifdef CONFIG_PIN_TLB |
Christophe Leroy | f76c8f6 | 2020-05-19 05:49:13 +0000 | [diff] [blame] | 691 | _GLOBAL(mmu_pin_tlb) |
| 692 | lis r9, (1f - PAGE_OFFSET)@h |
| 693 | ori r9, r9, (1f - PAGE_OFFSET)@l |
| 694 | mfmsr r10 |
| 695 | mflr r11 |
| 696 | li r12, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI) |
| 697 | rlwinm r0, r10, 0, ~MSR_RI |
| 698 | rlwinm r0, r0, 0, ~MSR_EE |
| 699 | mtmsr r0 |
| 700 | isync |
| 701 | .align 4 |
| 702 | mtspr SPRN_SRR0, r9 |
| 703 | mtspr SPRN_SRR1, r12 |
| 704 | rfi |
| 705 | 1: |
| 706 | li r5, 0 |
| 707 | lis r6, MD_TWAM@h |
| 708 | mtspr SPRN_MI_CTR, r5 |
| 709 | mtspr SPRN_MD_CTR, r6 |
| 710 | tlbia |
| 711 | |
Christophe Leroy | 1a736d9 | 2024-08-20 19:23:48 +0200 | [diff] [blame] | 712 | #ifdef CONFIG_PIN_TLB_TEXT |
Christophe Leroy | f76c8f6 | 2020-05-19 05:49:13 +0000 | [diff] [blame] | 713 | LOAD_REG_IMMEDIATE(r5, 28 << 8) |
| 714 | LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET) |
Christophe Leroy | 33fe43c | 2020-10-12 08:54:33 +0000 | [diff] [blame] | 715 | LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED) |
Christophe Leroy | f76c8f6 | 2020-05-19 05:49:13 +0000 | [diff] [blame] | 716 | LOAD_REG_IMMEDIATE(r8, 0xf0 | _PAGE_RO | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT) |
| 717 | LOAD_REG_ADDR(r9, _sinittext) |
| 718 | li r0, 4 |
| 719 | mtctr r0 |
| 720 | |
| 721 | 2: ori r0, r6, MI_EVALID |
| 722 | mtspr SPRN_MI_CTR, r5 |
| 723 | mtspr SPRN_MI_EPN, r0 |
| 724 | mtspr SPRN_MI_TWC, r7 |
| 725 | mtspr SPRN_MI_RPN, r8 |
| 726 | addi r5, r5, 0x100 |
| 727 | addis r6, r6, SZ_8M@h |
| 728 | addis r8, r8, SZ_8M@h |
| 729 | cmplw r6, r9 |
| 730 | bdnzt lt, 2b |
| 731 | lis r0, MI_RSV4I@h |
| 732 | mtspr SPRN_MI_CTR, r0 |
Christophe Leroy | 1a736d9 | 2024-08-20 19:23:48 +0200 | [diff] [blame] | 733 | #endif |
Christophe Leroy | bccc589 | 2020-11-24 15:24:55 +0000 | [diff] [blame] | 734 | |
Christophe Leroy | f76c8f6 | 2020-05-19 05:49:13 +0000 | [diff] [blame] | 735 | LOAD_REG_IMMEDIATE(r5, 28 << 8 | MD_TWAM) |
| 736 | #ifdef CONFIG_PIN_TLB_DATA |
| 737 | LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET) |
Christophe Leroy | 33fe43c | 2020-10-12 08:54:33 +0000 | [diff] [blame] | 738 | LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED) |
Christophe Leroy | 1e35eba | 2021-11-15 09:08:36 +0100 | [diff] [blame] | 739 | li r8, 0 |
Christophe Leroy | f76c8f6 | 2020-05-19 05:49:13 +0000 | [diff] [blame] | 740 | #ifdef CONFIG_PIN_TLB_IMMR |
| 741 | li r0, 3 |
| 742 | #else |
| 743 | li r0, 4 |
| 744 | #endif |
| 745 | mtctr r0 |
| 746 | cmpwi r4, 0 |
| 747 | beq 4f |
Christophe Leroy | f76c8f6 | 2020-05-19 05:49:13 +0000 | [diff] [blame] | 748 | LOAD_REG_ADDR(r9, _sinittext) |
| 749 | |
| 750 | 2: ori r0, r6, MD_EVALID |
Christophe Leroy | 1e35eba | 2021-11-15 09:08:36 +0100 | [diff] [blame] | 751 | ori r12, r8, 0xf0 | _PAGE_RO | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT |
Christophe Leroy | f76c8f6 | 2020-05-19 05:49:13 +0000 | [diff] [blame] | 752 | mtspr SPRN_MD_CTR, r5 |
| 753 | mtspr SPRN_MD_EPN, r0 |
| 754 | mtspr SPRN_MD_TWC, r7 |
Christophe Leroy | 1e35eba | 2021-11-15 09:08:36 +0100 | [diff] [blame] | 755 | mtspr SPRN_MD_RPN, r12 |
Christophe Leroy | f76c8f6 | 2020-05-19 05:49:13 +0000 | [diff] [blame] | 756 | addi r5, r5, 0x100 |
| 757 | addis r6, r6, SZ_8M@h |
| 758 | addis r8, r8, SZ_8M@h |
| 759 | cmplw r6, r9 |
| 760 | bdnzt lt, 2b |
Christophe Leroy | 1e35eba | 2021-11-15 09:08:36 +0100 | [diff] [blame] | 761 | 4: |
Christophe Leroy | f76c8f6 | 2020-05-19 05:49:13 +0000 | [diff] [blame] | 762 | 2: ori r0, r6, MD_EVALID |
Christophe Leroy | 1e35eba | 2021-11-15 09:08:36 +0100 | [diff] [blame] | 763 | ori r12, r8, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT |
Christophe Leroy | f76c8f6 | 2020-05-19 05:49:13 +0000 | [diff] [blame] | 764 | mtspr SPRN_MD_CTR, r5 |
| 765 | mtspr SPRN_MD_EPN, r0 |
| 766 | mtspr SPRN_MD_TWC, r7 |
Christophe Leroy | 1e35eba | 2021-11-15 09:08:36 +0100 | [diff] [blame] | 767 | mtspr SPRN_MD_RPN, r12 |
Christophe Leroy | f76c8f6 | 2020-05-19 05:49:13 +0000 | [diff] [blame] | 768 | addi r5, r5, 0x100 |
| 769 | addis r6, r6, SZ_8M@h |
| 770 | addis r8, r8, SZ_8M@h |
| 771 | cmplw r6, r3 |
| 772 | bdnzt lt, 2b |
| 773 | #endif |
| 774 | #ifdef CONFIG_PIN_TLB_IMMR |
| 775 | LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE | MD_EVALID) |
Christophe Leroy | 33fe43c | 2020-10-12 08:54:33 +0000 | [diff] [blame] | 776 | LOAD_REG_IMMEDIATE(r7, MD_SVALID | MD_PS512K | MD_GUARDED | _PMD_ACCESSED) |
Christophe Leroy | f76c8f6 | 2020-05-19 05:49:13 +0000 | [diff] [blame] | 777 | mfspr r8, SPRN_IMMR |
| 778 | rlwinm r8, r8, 0, 0xfff80000 |
| 779 | ori r8, r8, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | \ |
| 780 | _PAGE_NO_CACHE | _PAGE_PRESENT |
| 781 | mtspr SPRN_MD_CTR, r5 |
| 782 | mtspr SPRN_MD_EPN, r0 |
| 783 | mtspr SPRN_MD_TWC, r7 |
| 784 | mtspr SPRN_MD_RPN, r8 |
| 785 | #endif |
| 786 | #if defined(CONFIG_PIN_TLB_IMMR) || defined(CONFIG_PIN_TLB_DATA) |
| 787 | lis r0, (MD_RSV4I | MD_TWAM)@h |
Christophe Leroy | 1e35eba | 2021-11-15 09:08:36 +0100 | [diff] [blame] | 788 | mtspr SPRN_MD_CTR, r0 |
Christophe Leroy | f76c8f6 | 2020-05-19 05:49:13 +0000 | [diff] [blame] | 789 | #endif |
| 790 | mtspr SPRN_SRR1, r10 |
| 791 | mtspr SPRN_SRR0, r11 |
| 792 | rfi |
Christophe Leroy | 1a736d9 | 2024-08-20 19:23:48 +0200 | [diff] [blame] | 793 | #endif |