Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Definitions for the new Marvell Yukon / SysKonenct driver. |
| 3 | */ |
| 4 | #ifndef _SKGE_H |
| 5 | #define _SKGE_H |
| 6 | |
| 7 | /* PCI config registers */ |
| 8 | #define PCI_DEV_REG1 0x40 |
| 9 | #define PCI_DEV_REG2 0x44 |
David S. Miller | a31488c | 2005-07-05 14:24:35 -0700 | [diff] [blame] | 10 | #define PCI_REV_DESC 0x4 |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 11 | |
| 12 | #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ |
| 13 | PCI_STATUS_SIG_SYSTEM_ERROR | \ |
| 14 | PCI_STATUS_REC_MASTER_ABORT | \ |
| 15 | PCI_STATUS_REC_TARGET_ABORT | \ |
| 16 | PCI_STATUS_PARITY) |
| 17 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 18 | enum csr_regs { |
| 19 | B0_RAP = 0x0000, |
| 20 | B0_CTST = 0x0004, |
| 21 | B0_LED = 0x0006, |
| 22 | B0_POWER_CTRL = 0x0007, |
| 23 | B0_ISRC = 0x0008, |
| 24 | B0_IMSK = 0x000c, |
| 25 | B0_HWE_ISRC = 0x0010, |
| 26 | B0_HWE_IMSK = 0x0014, |
| 27 | B0_SP_ISRC = 0x0018, |
| 28 | B0_XM1_IMSK = 0x0020, |
| 29 | B0_XM1_ISRC = 0x0028, |
| 30 | B0_XM1_PHY_ADDR = 0x0030, |
| 31 | B0_XM1_PHY_DATA = 0x0034, |
| 32 | B0_XM2_IMSK = 0x0040, |
| 33 | B0_XM2_ISRC = 0x0048, |
| 34 | B0_XM2_PHY_ADDR = 0x0050, |
| 35 | B0_XM2_PHY_DATA = 0x0054, |
| 36 | B0_R1_CSR = 0x0060, |
| 37 | B0_R2_CSR = 0x0064, |
| 38 | B0_XS1_CSR = 0x0068, |
| 39 | B0_XA1_CSR = 0x006c, |
| 40 | B0_XS2_CSR = 0x0070, |
| 41 | B0_XA2_CSR = 0x0074, |
| 42 | |
| 43 | B2_MAC_1 = 0x0100, |
| 44 | B2_MAC_2 = 0x0108, |
| 45 | B2_MAC_3 = 0x0110, |
| 46 | B2_CONN_TYP = 0x0118, |
| 47 | B2_PMD_TYP = 0x0119, |
| 48 | B2_MAC_CFG = 0x011a, |
| 49 | B2_CHIP_ID = 0x011b, |
| 50 | B2_E_0 = 0x011c, |
| 51 | B2_E_1 = 0x011d, |
| 52 | B2_E_2 = 0x011e, |
| 53 | B2_E_3 = 0x011f, |
| 54 | B2_FAR = 0x0120, |
| 55 | B2_FDP = 0x0124, |
| 56 | B2_LD_CTRL = 0x0128, |
| 57 | B2_LD_TEST = 0x0129, |
| 58 | B2_TI_INI = 0x0130, |
| 59 | B2_TI_VAL = 0x0134, |
| 60 | B2_TI_CTRL = 0x0138, |
| 61 | B2_TI_TEST = 0x0139, |
| 62 | B2_IRQM_INI = 0x0140, |
| 63 | B2_IRQM_VAL = 0x0144, |
| 64 | B2_IRQM_CTRL = 0x0148, |
| 65 | B2_IRQM_TEST = 0x0149, |
| 66 | B2_IRQM_MSK = 0x014c, |
| 67 | B2_IRQM_HWE_MSK = 0x0150, |
| 68 | B2_TST_CTRL1 = 0x0158, |
| 69 | B2_TST_CTRL2 = 0x0159, |
| 70 | B2_GP_IO = 0x015c, |
| 71 | B2_I2C_CTRL = 0x0160, |
| 72 | B2_I2C_DATA = 0x0164, |
| 73 | B2_I2C_IRQ = 0x0168, |
| 74 | B2_I2C_SW = 0x016c, |
| 75 | B2_BSC_INI = 0x0170, |
| 76 | B2_BSC_VAL = 0x0174, |
| 77 | B2_BSC_CTRL = 0x0178, |
| 78 | B2_BSC_STAT = 0x0179, |
| 79 | B2_BSC_TST = 0x017a, |
| 80 | |
| 81 | B3_RAM_ADDR = 0x0180, |
| 82 | B3_RAM_DATA_LO = 0x0184, |
| 83 | B3_RAM_DATA_HI = 0x0188, |
| 84 | B3_RI_WTO_R1 = 0x0190, |
| 85 | B3_RI_WTO_XA1 = 0x0191, |
| 86 | B3_RI_WTO_XS1 = 0x0192, |
| 87 | B3_RI_RTO_R1 = 0x0193, |
| 88 | B3_RI_RTO_XA1 = 0x0194, |
| 89 | B3_RI_RTO_XS1 = 0x0195, |
| 90 | B3_RI_WTO_R2 = 0x0196, |
| 91 | B3_RI_WTO_XA2 = 0x0197, |
| 92 | B3_RI_WTO_XS2 = 0x0198, |
| 93 | B3_RI_RTO_R2 = 0x0199, |
| 94 | B3_RI_RTO_XA2 = 0x019a, |
| 95 | B3_RI_RTO_XS2 = 0x019b, |
| 96 | B3_RI_TO_VAL = 0x019c, |
| 97 | B3_RI_CTRL = 0x01a0, |
| 98 | B3_RI_TEST = 0x01a2, |
| 99 | B3_MA_TOINI_RX1 = 0x01b0, |
| 100 | B3_MA_TOINI_RX2 = 0x01b1, |
| 101 | B3_MA_TOINI_TX1 = 0x01b2, |
| 102 | B3_MA_TOINI_TX2 = 0x01b3, |
| 103 | B3_MA_TOVAL_RX1 = 0x01b4, |
| 104 | B3_MA_TOVAL_RX2 = 0x01b5, |
| 105 | B3_MA_TOVAL_TX1 = 0x01b6, |
| 106 | B3_MA_TOVAL_TX2 = 0x01b7, |
| 107 | B3_MA_TO_CTRL = 0x01b8, |
| 108 | B3_MA_TO_TEST = 0x01ba, |
| 109 | B3_MA_RCINI_RX1 = 0x01c0, |
| 110 | B3_MA_RCINI_RX2 = 0x01c1, |
| 111 | B3_MA_RCINI_TX1 = 0x01c2, |
| 112 | B3_MA_RCINI_TX2 = 0x01c3, |
| 113 | B3_MA_RCVAL_RX1 = 0x01c4, |
| 114 | B3_MA_RCVAL_RX2 = 0x01c5, |
| 115 | B3_MA_RCVAL_TX1 = 0x01c6, |
| 116 | B3_MA_RCVAL_TX2 = 0x01c7, |
| 117 | B3_MA_RC_CTRL = 0x01c8, |
| 118 | B3_MA_RC_TEST = 0x01ca, |
| 119 | B3_PA_TOINI_RX1 = 0x01d0, |
| 120 | B3_PA_TOINI_RX2 = 0x01d4, |
| 121 | B3_PA_TOINI_TX1 = 0x01d8, |
| 122 | B3_PA_TOINI_TX2 = 0x01dc, |
| 123 | B3_PA_TOVAL_RX1 = 0x01e0, |
| 124 | B3_PA_TOVAL_RX2 = 0x01e4, |
| 125 | B3_PA_TOVAL_TX1 = 0x01e8, |
| 126 | B3_PA_TOVAL_TX2 = 0x01ec, |
| 127 | B3_PA_CTRL = 0x01f0, |
| 128 | B3_PA_TEST = 0x01f2, |
| 129 | }; |
| 130 | |
| 131 | /* B0_CTST 16 bit Control/Status register */ |
| 132 | enum { |
| 133 | CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */ |
| 134 | CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */ |
| 135 | CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */ |
| 136 | CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */ |
| 137 | CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */ |
| 138 | CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */ |
| 139 | CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */ |
| 140 | CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */ |
| 141 | CS_STOP_DONE = 1<<5, /* Stop Master is finished */ |
| 142 | CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */ |
| 143 | CS_MRST_CLR = 1<<3, /* Clear Master reset */ |
| 144 | CS_MRST_SET = 1<<2, /* Set Master reset */ |
| 145 | CS_RST_CLR = 1<<1, /* Clear Software reset */ |
| 146 | CS_RST_SET = 1, /* Set Software reset */ |
| 147 | |
| 148 | /* B0_LED 8 Bit LED register */ |
| 149 | /* Bit 7.. 2: reserved */ |
| 150 | LED_STAT_ON = 1<<1, /* Status LED on */ |
| 151 | LED_STAT_OFF = 1, /* Status LED off */ |
| 152 | |
| 153 | /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ |
| 154 | PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */ |
| 155 | PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */ |
| 156 | PC_VCC_ENA = 1<<5, /* Switch VCC Enable */ |
| 157 | PC_VCC_DIS = 1<<4, /* Switch VCC Disable */ |
| 158 | PC_VAUX_ON = 1<<3, /* Switch VAUX On */ |
| 159 | PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */ |
| 160 | PC_VCC_ON = 1<<1, /* Switch VCC On */ |
| 161 | PC_VCC_OFF = 1<<0, /* Switch VCC Off */ |
| 162 | }; |
| 163 | |
| 164 | /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ |
| 165 | enum { |
| 166 | IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */ |
| 167 | IS_HW_ERR = 1<<31, /* Interrupt HW Error */ |
| 168 | /* Bit 30: reserved */ |
| 169 | IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */ |
| 170 | IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */ |
| 171 | IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */ |
| 172 | IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */ |
| 173 | IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */ |
| 174 | IS_IRQ_SW = 1<<24, /* SW forced IRQ */ |
| 175 | IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */ |
| 176 | /* IRQ from PHY (YUKON only) */ |
| 177 | IS_TIMINT = 1<<22, /* IRQ from Timer */ |
| 178 | IS_MAC1 = 1<<21, /* IRQ from MAC 1 */ |
| 179 | IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */ |
| 180 | IS_MAC2 = 1<<19, /* IRQ from MAC 2 */ |
| 181 | IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */ |
| 182 | /* Receive Queue 1 */ |
| 183 | IS_R1_B = 1<<17, /* Q_R1 End of Buffer */ |
| 184 | IS_R1_F = 1<<16, /* Q_R1 End of Frame */ |
| 185 | IS_R1_C = 1<<15, /* Q_R1 Encoding Error */ |
| 186 | /* Receive Queue 2 */ |
| 187 | IS_R2_B = 1<<14, /* Q_R2 End of Buffer */ |
| 188 | IS_R2_F = 1<<13, /* Q_R2 End of Frame */ |
| 189 | IS_R2_C = 1<<12, /* Q_R2 Encoding Error */ |
| 190 | /* Synchronous Transmit Queue 1 */ |
| 191 | IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */ |
| 192 | IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */ |
| 193 | IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */ |
| 194 | /* Asynchronous Transmit Queue 1 */ |
| 195 | IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */ |
| 196 | IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */ |
| 197 | IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */ |
| 198 | /* Synchronous Transmit Queue 2 */ |
| 199 | IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */ |
| 200 | IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */ |
| 201 | IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */ |
| 202 | /* Asynchronous Transmit Queue 2 */ |
| 203 | IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */ |
| 204 | IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */ |
| 205 | IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */ |
| 206 | |
Stephen Hemminger | d25f5a6 | 2005-06-27 11:33:14 -0700 | [diff] [blame] | 207 | IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1, |
| 208 | IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2, |
| 209 | |
| 210 | IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1, |
| 211 | IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2, |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 212 | }; |
| 213 | |
| 214 | |
| 215 | /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ |
| 216 | enum { |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 217 | IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */ |
| 218 | IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */ |
| 219 | IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */ |
| 220 | IS_IRQ_STAT = 1<<10, /* IRQ status exception */ |
| 221 | IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */ |
| 222 | IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */ |
| 223 | IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */ |
| 224 | IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */ |
| 225 | IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */ |
| 226 | IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */ |
| 227 | IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */ |
| 228 | IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */ |
| 229 | IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */ |
| 230 | IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */ |
Stephen Hemminger | 050ec18a | 2005-08-16 14:00:54 -0700 | [diff] [blame] | 231 | |
| 232 | IS_ERR_MSK = IS_IRQ_MST_ERR | IS_IRQ_STAT |
| 233 | | IS_NO_STAT_M1 | IS_NO_STAT_M2 |
| 234 | | IS_RAM_RD_PAR | IS_RAM_WR_PAR |
| 235 | | IS_M1_PAR_ERR | IS_M2_PAR_ERR |
| 236 | | IS_R1_PAR_ERR | IS_R2_PAR_ERR, |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 237 | }; |
| 238 | |
| 239 | /* B2_TST_CTRL1 8 bit Test Control Register 1 */ |
| 240 | enum { |
| 241 | TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */ |
| 242 | TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */ |
| 243 | TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */ |
| 244 | TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */ |
| 245 | TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */ |
| 246 | TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */ |
| 247 | TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */ |
| 248 | TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */ |
| 249 | }; |
| 250 | |
| 251 | /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ |
| 252 | enum { |
| 253 | CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */ |
| 254 | /* Bit 3.. 2: reserved */ |
| 255 | CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */ |
| 256 | CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/ |
| 257 | }; |
| 258 | |
| 259 | /* B2_CHIP_ID 8 bit Chip Identification Number */ |
| 260 | enum { |
| 261 | CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */ |
| 262 | CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */ |
| 263 | CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */ |
| 264 | CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */ |
| 265 | CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */ |
| 266 | CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */ |
| 267 | CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */ |
| 268 | |
| 269 | CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */ |
| 270 | CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */ |
| 271 | }; |
| 272 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 273 | /* B2_TI_CTRL 8 bit Timer control */ |
| 274 | /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ |
| 275 | enum { |
| 276 | TIM_START = 1<<2, /* Start Timer */ |
| 277 | TIM_STOP = 1<<1, /* Stop Timer */ |
| 278 | TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */ |
| 279 | }; |
| 280 | |
| 281 | /* B2_TI_TEST 8 Bit Timer Test */ |
| 282 | /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ |
| 283 | /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ |
| 284 | enum { |
| 285 | TIM_T_ON = 1<<2, /* Test mode on */ |
| 286 | TIM_T_OFF = 1<<1, /* Test mode off */ |
| 287 | TIM_T_STEP = 1<<0, /* Test step */ |
| 288 | }; |
| 289 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 290 | /* B2_GP_IO 32 bit General Purpose I/O Register */ |
| 291 | enum { |
| 292 | GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */ |
| 293 | GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */ |
| 294 | GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */ |
| 295 | GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */ |
| 296 | GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */ |
| 297 | GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */ |
| 298 | GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */ |
| 299 | GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */ |
| 300 | GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */ |
| 301 | GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */ |
| 302 | |
| 303 | GP_IO_9 = 1<<9, /* IO_9 pin */ |
| 304 | GP_IO_8 = 1<<8, /* IO_8 pin */ |
| 305 | GP_IO_7 = 1<<7, /* IO_7 pin */ |
| 306 | GP_IO_6 = 1<<6, /* IO_6 pin */ |
| 307 | GP_IO_5 = 1<<5, /* IO_5 pin */ |
| 308 | GP_IO_4 = 1<<4, /* IO_4 pin */ |
| 309 | GP_IO_3 = 1<<3, /* IO_3 pin */ |
| 310 | GP_IO_2 = 1<<2, /* IO_2 pin */ |
| 311 | GP_IO_1 = 1<<1, /* IO_1 pin */ |
| 312 | GP_IO_0 = 1<<0, /* IO_0 pin */ |
| 313 | }; |
| 314 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 315 | /* Descriptor Bit Definition */ |
| 316 | /* TxCtrl Transmit Buffer Control Field */ |
| 317 | /* RxCtrl Receive Buffer Control Field */ |
| 318 | enum { |
| 319 | BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */ |
| 320 | BMU_STF = 1<<30, /* Start of Frame */ |
| 321 | BMU_EOF = 1<<29, /* End of Frame */ |
| 322 | BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */ |
| 323 | BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */ |
| 324 | /* TxCtrl specific bits */ |
| 325 | BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */ |
| 326 | BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */ |
| 327 | BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */ |
| 328 | /* RxCtrl specific bits */ |
| 329 | BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */ |
| 330 | BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */ |
| 331 | BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */ |
| 332 | /* Bit 23..16: BMU Check Opcodes */ |
| 333 | BMU_CHECK = 0x55<<16, /* Default BMU check */ |
| 334 | BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */ |
| 335 | BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */ |
| 336 | BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */ |
| 337 | }; |
| 338 | |
| 339 | /* B2_BSC_CTRL 8 bit Blink Source Counter Control */ |
| 340 | enum { |
| 341 | BSC_START = 1<<1, /* Start Blink Source Counter */ |
| 342 | BSC_STOP = 1<<0, /* Stop Blink Source Counter */ |
| 343 | }; |
| 344 | |
| 345 | /* B2_BSC_STAT 8 bit Blink Source Counter Status */ |
| 346 | enum { |
| 347 | BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */ |
| 348 | }; |
| 349 | |
| 350 | /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */ |
| 351 | enum { |
| 352 | BSC_T_ON = 1<<2, /* Test mode on */ |
| 353 | BSC_T_OFF = 1<<1, /* Test mode off */ |
| 354 | BSC_T_STEP = 1<<0, /* Test step */ |
| 355 | }; |
| 356 | |
| 357 | /* B3_RAM_ADDR 32 bit RAM Address, to read or write */ |
| 358 | /* Bit 31..19: reserved */ |
| 359 | #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ |
| 360 | /* RAM Interface Registers */ |
| 361 | |
| 362 | /* B3_RI_CTRL 16 bit RAM Iface Control Register */ |
| 363 | enum { |
| 364 | RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */ |
| 365 | RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/ |
| 366 | |
| 367 | RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */ |
| 368 | RI_RST_SET = 1<<0, /* Set RAM Interface Reset */ |
| 369 | }; |
| 370 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 371 | /* MAC Arbiter Registers */ |
| 372 | /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */ |
| 373 | enum { |
| 374 | MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */ |
| 375 | MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */ |
| 376 | MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */ |
| 377 | MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */ |
| 378 | |
| 379 | }; |
| 380 | |
| 381 | /* Timeout values */ |
| 382 | #define SK_MAC_TO_53 72 /* MAC arbiter timeout */ |
| 383 | #define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */ |
| 384 | #define SK_PKT_TO_MAX 0xffff /* Maximum value */ |
| 385 | #define SK_RI_TO_53 36 /* RAM interface timeout */ |
| 386 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 387 | /* Packet Arbiter Registers */ |
| 388 | /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */ |
| 389 | enum { |
| 390 | PA_CLR_TO_TX2 = 1<<13, /* Clear IRQ Packet Timeout TX2 */ |
| 391 | PA_CLR_TO_TX1 = 1<<12, /* Clear IRQ Packet Timeout TX1 */ |
| 392 | PA_CLR_TO_RX2 = 1<<11, /* Clear IRQ Packet Timeout RX2 */ |
| 393 | PA_CLR_TO_RX1 = 1<<10, /* Clear IRQ Packet Timeout RX1 */ |
| 394 | PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */ |
| 395 | PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */ |
| 396 | PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */ |
| 397 | PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */ |
| 398 | PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */ |
| 399 | PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */ |
| 400 | PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */ |
| 401 | PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */ |
| 402 | PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */ |
| 403 | PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */ |
| 404 | }; |
| 405 | |
| 406 | #define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\ |
| 407 | PA_ENA_TO_TX1 | PA_ENA_TO_TX2) |
| 408 | |
| 409 | |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 410 | /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 411 | /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ |
| 412 | /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ |
| 413 | /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ |
| 414 | /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ |
| 415 | |
| 416 | #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */ |
| 417 | |
| 418 | /* TXA_CTRL 8 bit Tx Arbiter Control Register */ |
| 419 | enum { |
| 420 | TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */ |
| 421 | TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */ |
| 422 | TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */ |
| 423 | TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */ |
| 424 | TXA_START_RC = 1<<3, /* Start sync Rate Control */ |
| 425 | TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */ |
| 426 | TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */ |
| 427 | TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */ |
| 428 | }; |
| 429 | |
| 430 | /* |
| 431 | * Bank 4 - 5 |
| 432 | */ |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 433 | /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 434 | enum { |
| 435 | TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/ |
| 436 | TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */ |
| 437 | TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */ |
| 438 | TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */ |
| 439 | TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */ |
| 440 | TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */ |
| 441 | TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */ |
| 442 | }; |
| 443 | |
| 444 | |
| 445 | enum { |
| 446 | B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */ |
| 447 | B7_CFG_SPC = 0x0380,/* copy of the Configuration register */ |
| 448 | B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */ |
| 449 | B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */ |
| 450 | B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */ |
| 451 | B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */ |
| 452 | B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */ |
| 453 | B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */ |
| 454 | B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */ |
| 455 | }; |
| 456 | |
| 457 | /* Queue Register Offsets, use Q_ADDR() to access */ |
| 458 | enum { |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 459 | B8_Q_REGS = 0x0400, /* base of Queue registers */ |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 460 | Q_D = 0x00, /* 8*32 bit Current Descriptor */ |
| 461 | Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */ |
| 462 | Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */ |
| 463 | Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */ |
| 464 | Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */ |
| 465 | Q_BC = 0x30, /* 32 bit Current Byte Counter */ |
| 466 | Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */ |
| 467 | Q_F = 0x38, /* 32 bit Flag Register */ |
| 468 | Q_T1 = 0x3c, /* 32 bit Test Register 1 */ |
| 469 | Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */ |
| 470 | Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */ |
| 471 | Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */ |
| 472 | Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */ |
| 473 | Q_T2 = 0x40, /* 32 bit Test Register 2 */ |
| 474 | Q_T3 = 0x44, /* 32 bit Test Register 3 */ |
| 475 | |
| 476 | /* Yukon-2 */ |
| 477 | Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */ |
| 478 | Q_WM = 0x40, /* 16 bit FIFO Watermark */ |
| 479 | Q_AL = 0x42, /* 8 bit FIFO Alignment */ |
| 480 | Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */ |
| 481 | Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */ |
| 482 | Q_RP = 0x48, /* 8 bit FIFO Read Pointer */ |
| 483 | Q_RL = 0x4a, /* 8 bit FIFO Read Level */ |
| 484 | Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */ |
| 485 | Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */ |
| 486 | Q_WL = 0x4e, /* 8 bit FIFO Write Level */ |
| 487 | Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */ |
| 488 | }; |
| 489 | #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) |
| 490 | |
| 491 | /* RAM Buffer Register Offsets */ |
| 492 | enum { |
| 493 | |
| 494 | RB_START = 0x00,/* 32 bit RAM Buffer Start Address */ |
| 495 | RB_END = 0x04,/* 32 bit RAM Buffer End Address */ |
| 496 | RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */ |
| 497 | RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */ |
| 498 | RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */ |
| 499 | RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */ |
| 500 | RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */ |
| 501 | RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */ |
| 502 | /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */ |
| 503 | RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */ |
| 504 | RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */ |
| 505 | RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ |
| 506 | RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */ |
| 507 | RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */ |
| 508 | }; |
| 509 | |
| 510 | /* Receive and Transmit Queues */ |
| 511 | enum { |
| 512 | Q_R1 = 0x0000, /* Receive Queue 1 */ |
| 513 | Q_R2 = 0x0080, /* Receive Queue 2 */ |
| 514 | Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */ |
| 515 | Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */ |
| 516 | Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */ |
| 517 | Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */ |
| 518 | }; |
| 519 | |
| 520 | /* Different MAC Types */ |
| 521 | enum { |
| 522 | SK_MAC_XMAC = 0, /* Xaqti XMAC II */ |
| 523 | SK_MAC_GMAC = 1, /* Marvell GMAC */ |
| 524 | }; |
| 525 | |
| 526 | /* Different PHY Types */ |
| 527 | enum { |
| 528 | SK_PHY_XMAC = 0,/* integrated in XMAC II */ |
| 529 | SK_PHY_BCOM = 1,/* Broadcom BCM5400 */ |
| 530 | SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/ |
| 531 | SK_PHY_NAT = 3,/* National DP83891 [not supported] */ |
| 532 | SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */ |
| 533 | SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */ |
| 534 | }; |
| 535 | |
| 536 | /* PHY addresses (bits 12..8 of PHY address reg) */ |
| 537 | enum { |
| 538 | PHY_ADDR_XMAC = 0<<8, |
| 539 | PHY_ADDR_BCOM = 1<<8, |
Stephen Hemminger | b18f209 | 2005-06-27 11:33:08 -0700 | [diff] [blame] | 540 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 541 | /* GPHY address (bits 15..11 of SMI control reg) */ |
| 542 | PHY_ADDR_MARV = 0, |
| 543 | }; |
| 544 | |
| 545 | #define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs)) |
| 546 | |
| 547 | /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */ |
| 548 | enum { |
| 549 | RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */ |
| 550 | RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */ |
| 551 | |
| 552 | RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */ |
| 553 | RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */ |
| 554 | RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */ |
| 555 | RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/ |
| 556 | RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */ |
| 557 | RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */ |
| 558 | RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/ |
| 559 | RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */ |
| 560 | RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */ |
| 561 | |
| 562 | RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */ |
| 563 | RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */ |
| 564 | RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */ |
| 565 | RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */ |
| 566 | |
| 567 | LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */ |
| 568 | LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */ |
| 569 | LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */ |
| 570 | LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */ |
| 571 | LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */ |
| 572 | }; |
| 573 | |
| 574 | /* Receive and Transmit MAC FIFO Registers (GENESIS only) */ |
| 575 | /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */ |
| 576 | enum { |
| 577 | MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */ |
| 578 | MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */ |
| 579 | MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */ |
| 580 | MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */ |
| 581 | MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */ |
| 582 | MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */ |
| 583 | MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */ |
| 584 | MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */ |
| 585 | MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */ |
| 586 | MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */ |
| 587 | MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */ |
| 588 | MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */ |
| 589 | MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */ |
| 590 | MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */ |
| 591 | #define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT |
| 592 | }; |
| 593 | |
| 594 | /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */ |
| 595 | enum { |
| 596 | MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */ |
| 597 | /* Bit 14: reserved */ |
| 598 | MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */ |
| 599 | MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */ |
| 600 | |
| 601 | MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */ |
| 602 | MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */ |
| 603 | |
| 604 | MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */ |
| 605 | MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */ |
| 606 | MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */ |
| 607 | MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */ |
| 608 | }; |
| 609 | |
| 610 | #define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH) |
| 611 | |
| 612 | /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */ |
| 613 | /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */ |
| 614 | enum { |
| 615 | MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */ |
| 616 | MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */ |
| 617 | MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */ |
| 618 | MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */ |
| 619 | MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */ |
| 620 | MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */ |
| 621 | MFF_PC_INC = 1<<0, /* Packet Counter Increment */ |
| 622 | }; |
| 623 | |
| 624 | /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */ |
| 625 | /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */ |
| 626 | enum { |
| 627 | MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */ |
| 628 | MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */ |
| 629 | MFF_WP_INC = 1<<4, /* Write Pointer Increm */ |
| 630 | |
| 631 | MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */ |
| 632 | MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */ |
| 633 | MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */ |
| 634 | }; |
| 635 | |
| 636 | /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */ |
| 637 | /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */ |
| 638 | enum { |
| 639 | MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */ |
| 640 | MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */ |
| 641 | MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */ |
| 642 | MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */ |
| 643 | }; |
| 644 | |
| 645 | |
| 646 | /* Link LED Counter Registers (GENESIS only) */ |
| 647 | |
| 648 | /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */ |
| 649 | /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */ |
| 650 | /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */ |
| 651 | enum { |
| 652 | LED_START = 1<<2, /* Start Timer */ |
| 653 | LED_STOP = 1<<1, /* Stop Timer */ |
| 654 | LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */ |
| 655 | }; |
| 656 | |
| 657 | /* RX_LED_TST 8 bit Receive LED Cnt Test Register */ |
| 658 | /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */ |
| 659 | /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */ |
| 660 | enum { |
| 661 | LED_T_ON = 1<<2, /* LED Counter Test mode On */ |
| 662 | LED_T_OFF = 1<<1, /* LED Counter Test mode Off */ |
| 663 | LED_T_STEP = 1<<0, /* LED Counter Step */ |
| 664 | }; |
| 665 | |
| 666 | /* LNK_LED_REG 8 bit Link LED Register */ |
| 667 | enum { |
| 668 | LED_BLK_ON = 1<<5, /* Link LED Blinking On */ |
| 669 | LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */ |
| 670 | LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */ |
| 671 | LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */ |
| 672 | LED_ON = 1<<1, /* switch LED on */ |
| 673 | LED_OFF = 1<<0, /* switch LED off */ |
| 674 | }; |
| 675 | |
| 676 | /* Receive GMAC FIFO (YUKON and Yukon-2) */ |
| 677 | enum { |
| 678 | RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */ |
| 679 | RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */ |
| 680 | RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */ |
| 681 | RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */ |
| 682 | RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */ |
| 683 | RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */ |
| 684 | |
| 685 | RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */ |
| 686 | RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */ |
| 687 | |
| 688 | RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */ |
| 689 | |
| 690 | RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */ |
| 691 | |
| 692 | RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */ |
| 693 | }; |
| 694 | |
| 695 | |
| 696 | /* TXA_TEST 8 bit Tx Arbiter Test Register */ |
| 697 | enum { |
| 698 | TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */ |
| 699 | TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */ |
| 700 | TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */ |
| 701 | TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */ |
| 702 | TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */ |
| 703 | TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */ |
| 704 | }; |
| 705 | |
| 706 | /* TXA_STAT 8 bit Tx Arbiter Status Register */ |
| 707 | enum { |
| 708 | TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */ |
| 709 | }; |
| 710 | |
| 711 | |
| 712 | /* Q_BC 32 bit Current Byte Counter */ |
| 713 | |
| 714 | /* BMU Control Status Registers */ |
| 715 | /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ |
| 716 | /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ |
| 717 | /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ |
| 718 | /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ |
| 719 | /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ |
| 720 | /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ |
| 721 | /* Q_CSR 32 bit BMU Control/Status Register */ |
| 722 | |
| 723 | enum { |
| 724 | CSR_SV_IDLE = 1<<24, /* BMU SM Idle */ |
| 725 | |
| 726 | CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */ |
| 727 | CSR_DESC_SET = 1<<20, /* Set Reset for Descr */ |
| 728 | CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */ |
| 729 | CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */ |
| 730 | CSR_HPI_RUN = 1<<17, /* Release HPI SM */ |
| 731 | CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */ |
| 732 | CSR_SV_RUN = 1<<15, /* Release Supervisor SM */ |
| 733 | CSR_SV_RST = 1<<14, /* Reset Supervisor SM */ |
| 734 | CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */ |
| 735 | CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */ |
| 736 | CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */ |
| 737 | CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */ |
| 738 | CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */ |
| 739 | CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */ |
| 740 | CSR_ENA_POL = 1<<7, /* Enable Descr Polling */ |
| 741 | CSR_DIS_POL = 1<<6, /* Disable Descr Polling */ |
| 742 | CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */ |
| 743 | CSR_START = 1<<4, /* Start Rx/Tx Queue */ |
| 744 | CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */ |
| 745 | CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */ |
| 746 | CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */ |
| 747 | CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */ |
| 748 | }; |
| 749 | |
| 750 | #define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\ |
| 751 | CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\ |
| 752 | CSR_TRANS_RST) |
| 753 | #define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\ |
| 754 | CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\ |
| 755 | CSR_TRANS_RUN) |
| 756 | |
| 757 | /* Q_F 32 bit Flag Register */ |
| 758 | enum { |
| 759 | F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */ |
| 760 | F_EMPTY = 1<<27, /* Tx FIFO: empty flag */ |
| 761 | F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */ |
| 762 | F_WM_REACHED = 1<<25, /* Watermark reached */ |
| 763 | |
| 764 | F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */ |
| 765 | F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */ |
| 766 | }; |
| 767 | |
| 768 | /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ |
| 769 | /* RB_START 32 bit RAM Buffer Start Address */ |
| 770 | /* RB_END 32 bit RAM Buffer End Address */ |
| 771 | /* RB_WP 32 bit RAM Buffer Write Pointer */ |
| 772 | /* RB_RP 32 bit RAM Buffer Read Pointer */ |
| 773 | /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ |
| 774 | /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ |
| 775 | /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ |
| 776 | /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ |
| 777 | /* RB_PC 32 bit RAM Buffer Packet Counter */ |
| 778 | /* RB_LEV 32 bit RAM Buffer Level Register */ |
| 779 | |
| 780 | #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ |
| 781 | /* RB_TST2 8 bit RAM Buffer Test Register 2 */ |
| 782 | /* RB_TST1 8 bit RAM Buffer Test Register 1 */ |
| 783 | |
| 784 | /* RB_CTRL 8 bit RAM Buffer Control Register */ |
| 785 | enum { |
| 786 | RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */ |
| 787 | RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */ |
| 788 | RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */ |
| 789 | RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */ |
| 790 | RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */ |
| 791 | RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */ |
| 792 | }; |
| 793 | |
| 794 | /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */ |
| 795 | enum { |
| 796 | TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */ |
| 797 | TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */ |
| 798 | TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */ |
| 799 | TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */ |
| 800 | TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */ |
| 801 | TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */ |
| 802 | TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */ |
| 803 | TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */ |
| 804 | |
| 805 | TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */ |
| 806 | TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */ |
| 807 | TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */ |
| 808 | |
| 809 | TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */ |
| 810 | TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */ |
| 811 | TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */ |
| 812 | TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */ |
| 813 | }; |
| 814 | |
| 815 | /* Counter and Timer constants, for a host clock of 62.5 MHz */ |
| 816 | #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */ |
| 817 | #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */ |
| 818 | |
| 819 | #define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */ |
| 820 | |
| 821 | #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */ |
| 822 | /* 215 ms at 78.12 MHz */ |
| 823 | |
| 824 | #define SK_FACT_62 100 /* is given in percent */ |
| 825 | #define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */ |
| 826 | #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */ |
| 827 | |
| 828 | |
| 829 | /* Transmit GMAC FIFO (YUKON only) */ |
| 830 | enum { |
| 831 | TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */ |
| 832 | TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ |
| 833 | TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */ |
| 834 | |
| 835 | TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */ |
| 836 | TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ |
| 837 | TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */ |
| 838 | |
| 839 | TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */ |
| 840 | TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */ |
| 841 | TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */ |
| 842 | |
| 843 | /* Descriptor Poll Timer Registers */ |
| 844 | B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */ |
| 845 | B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */ |
| 846 | B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */ |
| 847 | |
| 848 | B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */ |
| 849 | |
| 850 | /* Time Stamp Timer Registers (YUKON only) */ |
| 851 | GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */ |
| 852 | GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */ |
| 853 | GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */ |
| 854 | }; |
| 855 | |
| 856 | /* Status BMU Registers (Yukon-2 only)*/ |
| 857 | enum { |
| 858 | STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */ |
| 859 | STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */ |
| 860 | /* 0x0e85 - 0x0e86: reserved */ |
| 861 | STAT_LIST_ADDR_LO = 0x0e88,/* 32 bit Status List Start Addr (low) */ |
| 862 | STAT_LIST_ADDR_HI = 0x0e8c,/* 32 bit Status List Start Addr (high) */ |
| 863 | STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */ |
| 864 | STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */ |
| 865 | STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */ |
| 866 | STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */ |
| 867 | STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */ |
| 868 | STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */ |
| 869 | |
| 870 | /* FIFO Control/Status Registers (Yukon-2 only)*/ |
| 871 | STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */ |
| 872 | STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */ |
| 873 | STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */ |
| 874 | STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */ |
| 875 | STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */ |
| 876 | STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */ |
| 877 | STAT_FIFO_ISR_WM = 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */ |
| 878 | |
| 879 | /* Level and ISR Timer Registers (Yukon-2 only)*/ |
| 880 | STAT_LEV_TIMER_INI = 0x0eb0,/* 32 bit Level Timer Init. Value Reg */ |
| 881 | STAT_LEV_TIMER_CNT = 0x0eb4,/* 32 bit Level Timer Counter Reg */ |
| 882 | STAT_LEV_TIMER_CTRL = 0x0eb8,/* 8 bit Level Timer Control Reg */ |
| 883 | STAT_LEV_TIMER_TEST = 0x0eb9,/* 8 bit Level Timer Test Reg */ |
| 884 | STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */ |
| 885 | STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */ |
| 886 | STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */ |
| 887 | STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */ |
| 888 | STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */ |
| 889 | STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */ |
| 890 | STAT_ISR_TIMER_CTRL = 0x0ed8,/* 8 bit ISR Timer Control Reg */ |
| 891 | STAT_ISR_TIMER_TEST = 0x0ed9,/* 8 bit ISR Timer Test Reg */ |
| 892 | |
| 893 | ST_LAST_IDX_MASK = 0x007f,/* Last Index Mask */ |
| 894 | ST_TXRP_IDX_MASK = 0x0fff,/* Tx Report Index Mask */ |
| 895 | ST_TXTH_IDX_MASK = 0x0fff,/* Tx Threshold Index Mask */ |
| 896 | ST_WM_IDX_MASK = 0x3f,/* FIFO Watermark Index Mask */ |
| 897 | }; |
| 898 | |
| 899 | enum { |
| 900 | LINKLED_OFF = 0x01, |
| 901 | LINKLED_ON = 0x02, |
| 902 | LINKLED_LINKSYNC_OFF = 0x04, |
| 903 | LINKLED_LINKSYNC_ON = 0x08, |
| 904 | LINKLED_BLINK_OFF = 0x10, |
| 905 | LINKLED_BLINK_ON = 0x20, |
| 906 | }; |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 907 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 908 | /* GMAC and GPHY Control Registers (YUKON only) */ |
| 909 | enum { |
| 910 | GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ |
| 911 | GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */ |
| 912 | GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */ |
| 913 | GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */ |
| 914 | GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */ |
| 915 | |
| 916 | /* Wake-up Frame Pattern Match Control Registers (YUKON only) */ |
| 917 | |
| 918 | WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */ |
| 919 | |
| 920 | WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */ |
| 921 | WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */ |
| 922 | WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */ |
| 923 | WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */ |
| 924 | WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */ |
| 925 | WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */ |
| 926 | WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */ |
| 927 | |
| 928 | /* WOL Pattern Length Registers (YUKON only) */ |
| 929 | |
| 930 | WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */ |
| 931 | WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */ |
| 932 | |
| 933 | /* WOL Pattern Counter Registers (YUKON only) */ |
| 934 | |
| 935 | WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */ |
| 936 | WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */ |
| 937 | }; |
| 938 | |
| 939 | enum { |
| 940 | WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */ |
| 941 | WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */ |
| 942 | }; |
| 943 | |
| 944 | enum { |
| 945 | BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */ |
| 946 | BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */ |
| 947 | BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */ |
| 948 | BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */ |
| 949 | }; |
| 950 | |
| 951 | /* |
| 952 | * Receive Frame Status Encoding |
| 953 | */ |
| 954 | enum { |
| 955 | XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */ |
Stephen Hemminger | 383181a | 2005-09-19 15:37:16 -0700 | [diff] [blame] | 956 | XMR_FS_LEN_SHIFT = 18, |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 957 | XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/ |
| 958 | XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/ |
| 959 | XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */ |
| 960 | XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */ |
| 961 | XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */ |
| 962 | |
| 963 | XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */ |
| 964 | XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */ |
| 965 | XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */ |
| 966 | XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */ |
| 967 | XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */ |
| 968 | XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */ |
| 969 | XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */ |
| 970 | XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */ |
| 971 | XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */ |
| 972 | XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */ |
| 973 | XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */ |
| 974 | XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */ |
| 975 | |
| 976 | /* |
| 977 | * XMR_FS_ERR will be set if |
| 978 | * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT, |
| 979 | * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR |
| 980 | * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue |
| 981 | * XMR_FS_ERR unless the corresponding bit in the Receive Command |
| 982 | * Register is set. |
| 983 | */ |
| 984 | }; |
| 985 | |
| 986 | /* |
| 987 | ,* XMAC-PHY Registers, indirect addressed over the XMAC |
| 988 | */ |
| 989 | enum { |
| 990 | PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */ |
| 991 | PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */ |
| 992 | PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */ |
| 993 | PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */ |
| 994 | PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ |
| 995 | PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */ |
| 996 | PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ |
| 997 | PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */ |
| 998 | PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ |
| 999 | |
| 1000 | PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */ |
| 1001 | PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */ |
| 1002 | }; |
| 1003 | /* |
| 1004 | * Broadcom-PHY Registers, indirect addressed over XMAC |
| 1005 | */ |
| 1006 | enum { |
| 1007 | PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */ |
| 1008 | PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */ |
| 1009 | PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */ |
| 1010 | PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */ |
| 1011 | PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ |
| 1012 | PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */ |
| 1013 | PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ |
| 1014 | PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */ |
| 1015 | PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ |
| 1016 | /* Broadcom-specific registers */ |
| 1017 | PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */ |
| 1018 | PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */ |
| 1019 | PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */ |
| 1020 | PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */ |
| 1021 | PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */ |
| 1022 | PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */ |
| 1023 | PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */ |
| 1024 | PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */ |
| 1025 | |
| 1026 | PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */ |
| 1027 | PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */ |
| 1028 | PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */ |
| 1029 | PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */ |
| 1030 | }; |
| 1031 | |
| 1032 | /* |
| 1033 | * Marvel-PHY Registers, indirect addressed over GMAC |
| 1034 | */ |
| 1035 | enum { |
| 1036 | PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */ |
| 1037 | PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */ |
| 1038 | PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */ |
| 1039 | PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */ |
| 1040 | PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ |
| 1041 | PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */ |
| 1042 | PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ |
| 1043 | PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */ |
| 1044 | PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ |
| 1045 | /* Marvel-specific registers */ |
| 1046 | PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */ |
| 1047 | PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */ |
| 1048 | PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */ |
| 1049 | PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */ |
| 1050 | PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */ |
| 1051 | PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */ |
| 1052 | PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */ |
| 1053 | PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */ |
| 1054 | PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */ |
| 1055 | PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */ |
| 1056 | PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */ |
| 1057 | PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */ |
| 1058 | PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */ |
| 1059 | PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */ |
| 1060 | PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */ |
| 1061 | PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */ |
| 1062 | PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */ |
| 1063 | PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */ |
| 1064 | |
| 1065 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ |
| 1066 | PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */ |
| 1067 | PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */ |
| 1068 | PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */ |
| 1069 | PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */ |
| 1070 | PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */ |
| 1071 | }; |
| 1072 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1073 | enum { |
| 1074 | PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */ |
| 1075 | PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */ |
| 1076 | PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */ |
| 1077 | PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */ |
| 1078 | PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */ |
| 1079 | PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */ |
| 1080 | PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */ |
| 1081 | PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */ |
| 1082 | PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */ |
| 1083 | PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */ |
| 1084 | }; |
| 1085 | |
| 1086 | enum { |
| 1087 | PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */ |
| 1088 | PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */ |
| 1089 | PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */ |
| 1090 | }; |
| 1091 | |
| 1092 | enum { |
| 1093 | PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */ |
| 1094 | |
| 1095 | PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */ |
| 1096 | PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */ |
| 1097 | PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */ |
| 1098 | PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */ |
| 1099 | PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */ |
| 1100 | PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */ |
| 1101 | PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */ |
| 1102 | }; |
| 1103 | |
| 1104 | enum { |
| 1105 | PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */ |
| 1106 | PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */ |
| 1107 | PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */ |
| 1108 | }; |
| 1109 | |
| 1110 | /* different Broadcom PHY Ids */ |
| 1111 | enum { |
| 1112 | PHY_BCOM_ID1_A1 = 0x6041, |
| 1113 | PHY_BCOM_ID1_B2 = 0x6043, |
| 1114 | PHY_BCOM_ID1_C0 = 0x6044, |
| 1115 | PHY_BCOM_ID1_C5 = 0x6047, |
| 1116 | }; |
| 1117 | |
| 1118 | /* different Marvell PHY Ids */ |
| 1119 | enum { |
| 1120 | PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */ |
| 1121 | PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */ |
| 1122 | PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */ |
| 1123 | PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */ |
| 1124 | PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */ |
| 1125 | }; |
| 1126 | |
Stephen Hemminger | b18f209 | 2005-06-27 11:33:08 -0700 | [diff] [blame] | 1127 | /* Advertisement register bits */ |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1128 | enum { |
| 1129 | PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */ |
Stephen Hemminger | b18f209 | 2005-06-27 11:33:08 -0700 | [diff] [blame] | 1130 | PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */ |
| 1131 | PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */ |
| 1132 | |
| 1133 | PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */ |
| 1134 | PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */ |
| 1135 | PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */ |
| 1136 | PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */ |
| 1137 | PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */ |
| 1138 | PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */ |
| 1139 | PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */ |
| 1140 | PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */ |
| 1141 | PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/ |
| 1142 | PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA, |
| 1143 | PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL | |
| 1144 | PHY_AN_100HALF | PHY_AN_100FULL, |
| 1145 | }; |
| 1146 | |
| 1147 | /* Xmac Specific */ |
| 1148 | enum { |
| 1149 | PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */ |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1150 | PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */ |
| 1151 | PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */ |
| 1152 | |
| 1153 | PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */ |
| 1154 | PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */ |
| 1155 | PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */ |
| 1156 | }; |
| 1157 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1158 | /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */ |
| 1159 | enum { |
| 1160 | PHY_X_P_NO_PAUSE = 0<<7,/* Bit 8..7: no Pause Mode */ |
| 1161 | PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */ |
| 1162 | PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */ |
| 1163 | PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */ |
| 1164 | }; |
| 1165 | |
| 1166 | |
| 1167 | /* Broadcom-Specific */ |
| 1168 | /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ |
| 1169 | enum { |
| 1170 | PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */ |
| 1171 | PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */ |
| 1172 | PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */ |
| 1173 | PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */ |
| 1174 | PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */ |
| 1175 | PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */ |
| 1176 | }; |
| 1177 | |
| 1178 | /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ |
| 1179 | /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ |
| 1180 | enum { |
| 1181 | PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */ |
| 1182 | PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */ |
| 1183 | PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */ |
| 1184 | PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */ |
| 1185 | PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */ |
| 1186 | PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */ |
| 1187 | /* Bit 9..8: reserved */ |
| 1188 | PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */ |
| 1189 | }; |
| 1190 | |
| 1191 | /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/ |
| 1192 | enum { |
| 1193 | PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */ |
| 1194 | PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */ |
| 1195 | PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */ |
| 1196 | PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */ |
| 1197 | }; |
| 1198 | |
| 1199 | /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/ |
| 1200 | enum { |
| 1201 | PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */ |
| 1202 | PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */ |
| 1203 | PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */ |
| 1204 | PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */ |
| 1205 | PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */ |
| 1206 | PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */ |
| 1207 | PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */ |
| 1208 | PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */ |
| 1209 | PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */ |
| 1210 | PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */ |
| 1211 | PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */ |
| 1212 | PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */ |
| 1213 | PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */ |
| 1214 | PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */ |
| 1215 | PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */ |
| 1216 | PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */ |
| 1217 | }; |
| 1218 | |
| 1219 | /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/ |
| 1220 | enum { |
| 1221 | PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */ |
| 1222 | PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */ |
| 1223 | PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */ |
| 1224 | PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */ |
| 1225 | PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */ |
| 1226 | PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */ |
| 1227 | PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */ |
| 1228 | PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */ |
| 1229 | PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */ |
| 1230 | PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */ |
| 1231 | PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */ |
| 1232 | PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */ |
| 1233 | PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */ |
| 1234 | PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */ |
| 1235 | }; |
| 1236 | |
Stephen Hemminger | 45bada6 | 2005-06-27 11:33:12 -0700 | [diff] [blame] | 1237 | /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ |
| 1238 | /* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ |
| 1239 | enum { |
| 1240 | PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */ |
| 1241 | |
| 1242 | PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */ |
| 1243 | PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */ |
| 1244 | }; |
| 1245 | |
| 1246 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1247 | /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/ |
| 1248 | enum { |
| 1249 | PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */ |
| 1250 | |
| 1251 | /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/ |
| 1252 | PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */ |
| 1253 | PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */ |
| 1254 | |
| 1255 | /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/ |
| 1256 | PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */ |
| 1257 | PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */ |
| 1258 | PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */ |
| 1259 | /* Bit 11: reserved */ |
| 1260 | PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */ |
| 1261 | /* Bit 9.. 8: reserved */ |
| 1262 | PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */ |
| 1263 | /* Bit 6: reserved */ |
| 1264 | PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */ |
| 1265 | /* Bit 4: reserved */ |
| 1266 | PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */ |
| 1267 | }; |
| 1268 | |
| 1269 | /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/ |
| 1270 | enum { |
| 1271 | PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */ |
| 1272 | PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */ |
| 1273 | PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */ |
| 1274 | PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */ |
| 1275 | PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */ |
| 1276 | PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */ |
| 1277 | PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */ |
| 1278 | PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */ |
| 1279 | PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */ |
| 1280 | PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */ |
| 1281 | PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */ |
| 1282 | PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */ |
| 1283 | PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */ |
| 1284 | PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */ |
| 1285 | }; |
| 1286 | #define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT) |
| 1287 | |
| 1288 | /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/ |
| 1289 | /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ |
| 1290 | enum { |
| 1291 | PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */ |
| 1292 | PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */ |
| 1293 | PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */ |
| 1294 | PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */ |
| 1295 | PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */ |
| 1296 | PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */ |
| 1297 | PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */ |
| 1298 | PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */ |
| 1299 | PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */ |
| 1300 | PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */ |
| 1301 | PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */ |
| 1302 | PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */ |
| 1303 | PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */ |
| 1304 | PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */ |
| 1305 | PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */ |
| 1306 | }; |
Stephen Hemminger | 45bada6 | 2005-06-27 11:33:12 -0700 | [diff] [blame] | 1307 | #define PHY_B_DEF_MSK \ |
| 1308 | (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \ |
| 1309 | PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE)) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1310 | |
| 1311 | /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */ |
| 1312 | enum { |
| 1313 | PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */ |
| 1314 | PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */ |
| 1315 | PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */ |
| 1316 | PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */ |
| 1317 | }; |
| 1318 | /* |
| 1319 | * Resolved Duplex mode and Capabilities (Aux Status Summary Reg) |
| 1320 | */ |
| 1321 | enum { |
| 1322 | PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */ |
| 1323 | PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */ |
| 1324 | }; |
| 1325 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1326 | /** Marvell-Specific */ |
| 1327 | enum { |
| 1328 | PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */ |
| 1329 | PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */ |
| 1330 | PHY_M_AN_RF = 1<<13, /* Remote Fault */ |
| 1331 | |
| 1332 | PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */ |
| 1333 | PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */ |
| 1334 | PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */ |
| 1335 | PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */ |
| 1336 | PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */ |
| 1337 | PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */ |
| 1338 | PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */ |
| 1339 | PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */ |
| 1340 | }; |
| 1341 | |
| 1342 | /* special defines for FIBER (88E1011S only) */ |
| 1343 | enum { |
| 1344 | PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */ |
| 1345 | PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */ |
| 1346 | PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */ |
| 1347 | PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */ |
| 1348 | }; |
| 1349 | |
| 1350 | /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ |
| 1351 | enum { |
| 1352 | PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */ |
| 1353 | PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */ |
| 1354 | PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */ |
| 1355 | PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */ |
| 1356 | }; |
| 1357 | |
| 1358 | /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ |
| 1359 | enum { |
| 1360 | PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */ |
| 1361 | PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */ |
| 1362 | PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */ |
| 1363 | PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */ |
| 1364 | PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */ |
| 1365 | PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */ |
| 1366 | }; |
| 1367 | |
| 1368 | /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ |
| 1369 | enum { |
| 1370 | PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */ |
| 1371 | PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */ |
| 1372 | PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */ |
| 1373 | PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */ |
| 1374 | PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */ |
| 1375 | PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */ |
| 1376 | PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */ |
| 1377 | PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */ |
| 1378 | PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */ |
| 1379 | PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */ |
| 1380 | PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */ |
| 1381 | PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */ |
| 1382 | }; |
| 1383 | |
| 1384 | enum { |
| 1385 | PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */ |
| 1386 | PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */ |
| 1387 | }; |
| 1388 | |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 1389 | #define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1390 | |
| 1391 | enum { |
| 1392 | PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */ |
| 1393 | PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */ |
| 1394 | PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */ |
| 1395 | }; |
| 1396 | |
| 1397 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ |
| 1398 | enum { |
| 1399 | PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */ |
| 1400 | PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */ |
| 1401 | PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */ |
| 1402 | PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */ |
| 1403 | PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */ |
| 1404 | |
| 1405 | PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */ |
| 1406 | PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */ |
| 1407 | |
| 1408 | PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */ |
| 1409 | PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */ |
| 1410 | }; |
| 1411 | |
| 1412 | /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ |
| 1413 | enum { |
| 1414 | PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */ |
| 1415 | PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */ |
| 1416 | PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */ |
| 1417 | PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */ |
| 1418 | PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */ |
| 1419 | PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */ |
| 1420 | PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */ |
| 1421 | PHY_M_PS_LINK_UP = 1<<10, /* Link Up */ |
| 1422 | PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */ |
| 1423 | PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */ |
| 1424 | PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */ |
| 1425 | PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */ |
| 1426 | PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */ |
| 1427 | PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */ |
| 1428 | PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */ |
| 1429 | PHY_M_PS_JABBER = 1<<0, /* Jabber */ |
| 1430 | }; |
| 1431 | |
| 1432 | #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) |
| 1433 | |
| 1434 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ |
| 1435 | enum { |
| 1436 | PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */ |
| 1437 | PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ |
| 1438 | }; |
| 1439 | |
| 1440 | enum { |
| 1441 | PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */ |
| 1442 | PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */ |
| 1443 | PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */ |
| 1444 | PHY_M_IS_AN_PR = 1<<12, /* Page Received */ |
| 1445 | PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */ |
| 1446 | PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */ |
| 1447 | PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */ |
| 1448 | PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */ |
| 1449 | PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */ |
| 1450 | PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */ |
| 1451 | PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */ |
| 1452 | PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */ |
| 1453 | |
| 1454 | PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */ |
| 1455 | PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */ |
| 1456 | PHY_M_IS_JABBER = 1<<0, /* Jabber */ |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1457 | |
Stephen Hemminger | 4cde06e | 2005-07-22 16:26:09 -0700 | [diff] [blame] | 1458 | PHY_M_IS_DEF_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE | |
| 1459 | PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR, |
| 1460 | |
| 1461 | PHY_M_IS_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL, |
| 1462 | }; |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1463 | |
| 1464 | /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ |
| 1465 | enum { |
| 1466 | PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */ |
| 1467 | PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */ |
| 1468 | |
| 1469 | PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */ |
| 1470 | PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */ |
| 1471 | /* (88E1011 only) */ |
| 1472 | PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */ |
| 1473 | /* (88E1011 only) */ |
| 1474 | PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */ |
| 1475 | /* (88E1111 only) */ |
| 1476 | PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */ |
| 1477 | /* !!! Errata in spec. (1 = disable) */ |
| 1478 | PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/ |
| 1479 | PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */ |
| 1480 | PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */ |
| 1481 | PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */ |
| 1482 | PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */ |
| 1483 | PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */}; |
| 1484 | |
| 1485 | #define PHY_M_EC_M_DSC(x) ((x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */ |
| 1486 | #define PHY_M_EC_S_DSC(x) ((x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */ |
| 1487 | #define PHY_M_EC_MAC_S(x) ((x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */ |
| 1488 | |
| 1489 | #define PHY_M_EC_M_DSC_2(x) ((x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */ |
| 1490 | /* 100=5x; 101=6x; 110=7x; 111=8x */ |
| 1491 | enum { |
| 1492 | MAC_TX_CLK_0_MHZ = 2, |
| 1493 | MAC_TX_CLK_2_5_MHZ = 6, |
| 1494 | MAC_TX_CLK_25_MHZ = 7, |
| 1495 | }; |
| 1496 | |
| 1497 | /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ |
| 1498 | enum { |
| 1499 | PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */ |
| 1500 | PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */ |
| 1501 | PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */ |
| 1502 | PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */ |
| 1503 | PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */ |
| 1504 | PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */ |
| 1505 | PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */ |
| 1506 | /* (88E1111 only) */ |
| 1507 | }; |
| 1508 | |
| 1509 | enum { |
| 1510 | PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */ |
| 1511 | /* (88E1011 only) */ |
| 1512 | PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */ |
| 1513 | PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */ |
| 1514 | PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */ |
| 1515 | PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */ |
| 1516 | PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */ |
| 1517 | }; |
| 1518 | |
Stephen Hemminger | 2c66851 | 2005-07-22 16:26:07 -0700 | [diff] [blame] | 1519 | #define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1520 | |
| 1521 | enum { |
| 1522 | PULS_NO_STR = 0,/* no pulse stretching */ |
| 1523 | PULS_21MS = 1,/* 21 ms to 42 ms */ |
| 1524 | PULS_42MS = 2,/* 42 ms to 84 ms */ |
| 1525 | PULS_84MS = 3,/* 84 ms to 170 ms */ |
| 1526 | PULS_170MS = 4,/* 170 ms to 340 ms */ |
| 1527 | PULS_340MS = 5,/* 340 ms to 670 ms */ |
| 1528 | PULS_670MS = 6,/* 670 ms to 1.3 s */ |
| 1529 | PULS_1300MS = 7,/* 1.3 s to 2.7 s */ |
| 1530 | }; |
| 1531 | |
Stephen Hemminger | 2c66851 | 2005-07-22 16:26:07 -0700 | [diff] [blame] | 1532 | #define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1533 | |
| 1534 | enum { |
| 1535 | BLINK_42MS = 0,/* 42 ms */ |
| 1536 | BLINK_84MS = 1,/* 84 ms */ |
| 1537 | BLINK_170MS = 2,/* 170 ms */ |
| 1538 | BLINK_340MS = 3,/* 340 ms */ |
| 1539 | BLINK_670MS = 4,/* 670 ms */ |
| 1540 | }; |
| 1541 | |
| 1542 | /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ |
| 1543 | #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */ |
| 1544 | /* Bit 13..12: reserved */ |
| 1545 | #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */ |
| 1546 | #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */ |
| 1547 | #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */ |
| 1548 | #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */ |
| 1549 | #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */ |
| 1550 | #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */ |
| 1551 | |
| 1552 | enum { |
| 1553 | MO_LED_NORM = 0, |
| 1554 | MO_LED_BLINK = 1, |
| 1555 | MO_LED_OFF = 2, |
| 1556 | MO_LED_ON = 3, |
| 1557 | }; |
| 1558 | |
| 1559 | /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ |
| 1560 | enum { |
| 1561 | PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */ |
| 1562 | PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */ |
| 1563 | PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */ |
| 1564 | PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */ |
| 1565 | PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */ |
| 1566 | }; |
| 1567 | |
| 1568 | /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ |
| 1569 | enum { |
| 1570 | PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */ |
| 1571 | PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */ |
| 1572 | PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */ |
| 1573 | PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */ |
| 1574 | PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */ |
| 1575 | PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */ |
| 1576 | PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */ |
| 1577 | /* (88E1111 only) */ |
| 1578 | /* Bit 9.. 4: reserved (88E1011 only) */ |
| 1579 | PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */ |
| 1580 | PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */ |
| 1581 | PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ |
| 1582 | }; |
| 1583 | |
| 1584 | /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/ |
| 1585 | enum { |
| 1586 | PHY_M_CABD_ENA_TEST = 1<<15, /* Enable Test (Page 0) */ |
| 1587 | PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */ |
| 1588 | /* (88E1111 only) */ |
| 1589 | PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */ |
| 1590 | PHY_M_CABD_AMPL_MSK = 0x1f<<8,/* Bit 12.. 8: Amplitude Mask */ |
| 1591 | /* (88E1111 only) */ |
| 1592 | PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */ |
| 1593 | }; |
| 1594 | |
| 1595 | /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */ |
| 1596 | enum { |
| 1597 | CABD_STAT_NORMAL= 0, |
| 1598 | CABD_STAT_SHORT = 1, |
| 1599 | CABD_STAT_OPEN = 2, |
| 1600 | CABD_STAT_FAIL = 3, |
| 1601 | }; |
| 1602 | |
| 1603 | /* for 10/100 Fast Ethernet PHY (88E3082 only) */ |
| 1604 | /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ |
| 1605 | /* Bit 15..12: reserved (used internally) */ |
| 1606 | enum { |
| 1607 | PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */ |
| 1608 | PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */ |
| 1609 | PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */ |
| 1610 | }; |
| 1611 | |
Stephen Hemminger | 2c66851 | 2005-07-22 16:26:07 -0700 | [diff] [blame] | 1612 | #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK) |
| 1613 | #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK) |
| 1614 | #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1615 | |
| 1616 | enum { |
| 1617 | LED_PAR_CTRL_COLX = 0x00, |
| 1618 | LED_PAR_CTRL_ERROR = 0x01, |
| 1619 | LED_PAR_CTRL_DUPLEX = 0x02, |
| 1620 | LED_PAR_CTRL_DP_COL = 0x03, |
| 1621 | LED_PAR_CTRL_SPEED = 0x04, |
| 1622 | LED_PAR_CTRL_LINK = 0x05, |
| 1623 | LED_PAR_CTRL_TX = 0x06, |
| 1624 | LED_PAR_CTRL_RX = 0x07, |
| 1625 | LED_PAR_CTRL_ACT = 0x08, |
| 1626 | LED_PAR_CTRL_LNK_RX = 0x09, |
| 1627 | LED_PAR_CTRL_LNK_AC = 0x0a, |
| 1628 | LED_PAR_CTRL_ACT_BL = 0x0b, |
| 1629 | LED_PAR_CTRL_TX_BL = 0x0c, |
| 1630 | LED_PAR_CTRL_RX_BL = 0x0d, |
| 1631 | LED_PAR_CTRL_COL_BL = 0x0e, |
| 1632 | LED_PAR_CTRL_INACT = 0x0f |
| 1633 | }; |
| 1634 | |
| 1635 | /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ |
| 1636 | enum { |
| 1637 | PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */ |
| 1638 | PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */ |
| 1639 | PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */ |
| 1640 | }; |
| 1641 | |
| 1642 | /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ |
| 1643 | /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ |
| 1644 | enum { |
| 1645 | PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */ |
| 1646 | PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */ |
| 1647 | PHY_M_MAC_MD_COPPER = 5,/* Copper only */ |
| 1648 | PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */ |
| 1649 | }; |
Stephen Hemminger | 2c66851 | 2005-07-22 16:26:07 -0700 | [diff] [blame] | 1650 | #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1651 | |
| 1652 | /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ |
| 1653 | enum { |
| 1654 | PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */ |
| 1655 | PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */ |
| 1656 | PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */ |
| 1657 | PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ |
| 1658 | }; |
| 1659 | |
Stephen Hemminger | 2c66851 | 2005-07-22 16:26:07 -0700 | [diff] [blame] | 1660 | #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK) |
| 1661 | #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK) |
| 1662 | #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK) |
| 1663 | #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1664 | |
| 1665 | /* GMAC registers */ |
| 1666 | /* Port Registers */ |
| 1667 | enum { |
| 1668 | GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */ |
| 1669 | GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */ |
| 1670 | GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */ |
| 1671 | GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */ |
| 1672 | GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */ |
| 1673 | GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */ |
| 1674 | GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */ |
| 1675 | /* Source Address Registers */ |
| 1676 | GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */ |
| 1677 | GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */ |
| 1678 | GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */ |
| 1679 | GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */ |
| 1680 | GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */ |
| 1681 | GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */ |
| 1682 | |
| 1683 | /* Multicast Address Hash Registers */ |
| 1684 | GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */ |
| 1685 | GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */ |
| 1686 | GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */ |
| 1687 | GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */ |
| 1688 | |
| 1689 | /* Interrupt Source Registers */ |
| 1690 | GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */ |
| 1691 | GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */ |
| 1692 | GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */ |
| 1693 | |
| 1694 | /* Interrupt Mask Registers */ |
| 1695 | GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */ |
| 1696 | GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */ |
| 1697 | GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */ |
| 1698 | |
| 1699 | /* Serial Management Interface (SMI) Registers */ |
| 1700 | GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */ |
| 1701 | GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */ |
| 1702 | GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */ |
| 1703 | }; |
| 1704 | |
| 1705 | /* MIB Counters */ |
| 1706 | #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ |
| 1707 | #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ |
| 1708 | |
| 1709 | /* |
| 1710 | * MIB Counters base address definitions (low word) - |
| 1711 | * use offset 4 for access to high word (32 bit r/o) |
| 1712 | */ |
| 1713 | enum { |
| 1714 | GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */ |
| 1715 | GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */ |
| 1716 | GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */ |
| 1717 | GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */ |
| 1718 | GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */ |
| 1719 | /* GM_MIB_CNT_BASE + 40: reserved */ |
| 1720 | GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */ |
| 1721 | GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */ |
| 1722 | GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */ |
| 1723 | GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */ |
| 1724 | GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */ |
| 1725 | GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */ |
| 1726 | GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */ |
| 1727 | GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */ |
| 1728 | GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */ |
| 1729 | GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */ |
| 1730 | GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */ |
| 1731 | GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */ |
| 1732 | GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */ |
| 1733 | GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */ |
| 1734 | GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */ |
| 1735 | /* GM_MIB_CNT_BASE + 168: reserved */ |
| 1736 | GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */ |
| 1737 | /* GM_MIB_CNT_BASE + 184: reserved */ |
| 1738 | GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */ |
| 1739 | GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */ |
| 1740 | GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */ |
| 1741 | GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */ |
| 1742 | GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */ |
| 1743 | GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */ |
| 1744 | GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */ |
| 1745 | GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */ |
| 1746 | GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */ |
| 1747 | GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */ |
| 1748 | GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */ |
| 1749 | GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */ |
| 1750 | GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */ |
| 1751 | |
| 1752 | GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */ |
| 1753 | GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */ |
| 1754 | GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */ |
| 1755 | GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */ |
| 1756 | GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */ |
| 1757 | GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */ |
| 1758 | }; |
| 1759 | |
| 1760 | /* GMAC Bit Definitions */ |
| 1761 | /* GM_GP_STAT 16 bit r/o General Purpose Status Register */ |
| 1762 | enum { |
| 1763 | GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */ |
| 1764 | GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */ |
| 1765 | GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */ |
| 1766 | GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */ |
| 1767 | GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */ |
| 1768 | GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */ |
| 1769 | GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */ |
| 1770 | GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */ |
| 1771 | |
| 1772 | GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */ |
| 1773 | GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */ |
| 1774 | GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */ |
| 1775 | GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */ |
| 1776 | GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */ |
| 1777 | }; |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 1778 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1779 | /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ |
| 1780 | enum { |
| 1781 | GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */ |
| 1782 | GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */ |
| 1783 | GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */ |
| 1784 | GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */ |
| 1785 | GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */ |
| 1786 | GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */ |
| 1787 | GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */ |
| 1788 | GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */ |
| 1789 | GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */ |
| 1790 | GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */ |
| 1791 | GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */ |
| 1792 | GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */ |
| 1793 | GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */ |
| 1794 | GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */ |
| 1795 | GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */ |
| 1796 | }; |
| 1797 | |
| 1798 | #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) |
| 1799 | #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS) |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 1800 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1801 | /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ |
| 1802 | enum { |
| 1803 | GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */ |
| 1804 | GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */ |
| 1805 | GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */ |
| 1806 | GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */ |
| 1807 | }; |
| 1808 | |
| 1809 | #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK) |
| 1810 | #define TX_COL_DEF 0x04 |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 1811 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1812 | /* GM_RX_CTRL 16 bit r/w Receive Control Register */ |
| 1813 | enum { |
| 1814 | GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */ |
| 1815 | GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */ |
| 1816 | GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */ |
| 1817 | GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */ |
| 1818 | }; |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 1819 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1820 | /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ |
| 1821 | enum { |
| 1822 | GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */ |
| 1823 | GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */ |
| 1824 | GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */ |
| 1825 | |
| 1826 | TX_JAM_LEN_DEF = 0x03, |
| 1827 | TX_JAM_IPG_DEF = 0x0b, |
| 1828 | TX_IPG_JAM_DEF = 0x1c, |
| 1829 | }; |
| 1830 | |
| 1831 | #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK) |
| 1832 | #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK) |
| 1833 | #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK) |
| 1834 | |
| 1835 | |
| 1836 | /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ |
| 1837 | enum { |
| 1838 | GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */ |
| 1839 | GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */ |
| 1840 | GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */ |
| 1841 | GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */ |
| 1842 | GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ |
| 1843 | }; |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 1844 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1845 | #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK) |
| 1846 | #define DATA_BLIND_DEF 0x04 |
| 1847 | |
| 1848 | #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK) |
| 1849 | #define IPG_DATA_DEF 0x1e |
| 1850 | |
| 1851 | /* GM_SMI_CTRL 16 bit r/w SMI Control Register */ |
| 1852 | enum { |
| 1853 | GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */ |
| 1854 | GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */ |
| 1855 | GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/ |
| 1856 | GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */ |
| 1857 | GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */ |
| 1858 | }; |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 1859 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1860 | #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK) |
| 1861 | #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK) |
| 1862 | |
| 1863 | /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ |
| 1864 | enum { |
| 1865 | GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */ |
| 1866 | GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */ |
| 1867 | }; |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 1868 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1869 | /* Receive Frame Status Encoding */ |
| 1870 | enum { |
| 1871 | GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */ |
Stephen Hemminger | 383181a | 2005-09-19 15:37:16 -0700 | [diff] [blame] | 1872 | GMR_FS_LEN_SHIFT = 16, |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1873 | GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */ |
| 1874 | GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */ |
| 1875 | GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */ |
| 1876 | GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */ |
| 1877 | GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */ |
| 1878 | GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */ |
| 1879 | GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */ |
| 1880 | GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */ |
| 1881 | GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */ |
| 1882 | GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */ |
| 1883 | GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */ |
| 1884 | |
| 1885 | GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */ |
| 1886 | GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */ |
| 1887 | |
| 1888 | /* |
| 1889 | * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR) |
| 1890 | */ |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 1891 | GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR | |
| 1892 | GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1893 | GMR_FS_JABBER, |
| 1894 | /* Rx GMAC FIFO Flush Mask (default) */ |
| 1895 | RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR | |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 1896 | GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 1897 | GMR_FS_JABBER, |
| 1898 | }; |
| 1899 | |
| 1900 | /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ |
| 1901 | enum { |
| 1902 | GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */ |
| 1903 | GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */ |
| 1904 | GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */ |
| 1905 | |
| 1906 | GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */ |
| 1907 | GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */ |
| 1908 | GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */ |
| 1909 | GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */ |
| 1910 | GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */ |
| 1911 | GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */ |
| 1912 | GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */ |
| 1913 | GMF_OPER_ON = 1<<3, /* Operational Mode On */ |
| 1914 | GMF_OPER_OFF = 1<<2, /* Operational Mode Off */ |
| 1915 | GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */ |
| 1916 | GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */ |
| 1917 | |
| 1918 | RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */ |
| 1919 | }; |
| 1920 | |
| 1921 | |
| 1922 | /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ |
| 1923 | enum { |
| 1924 | GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */ |
| 1925 | GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */ |
| 1926 | GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */ |
| 1927 | |
| 1928 | GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */ |
| 1929 | GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */ |
| 1930 | GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */ |
| 1931 | }; |
| 1932 | |
| 1933 | /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ |
| 1934 | enum { |
| 1935 | GMT_ST_START = 1<<2, /* Start Time Stamp Timer */ |
| 1936 | GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */ |
| 1937 | GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */ |
| 1938 | }; |
| 1939 | |
| 1940 | /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ |
| 1941 | enum { |
| 1942 | GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */ |
| 1943 | GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */ |
| 1944 | GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */ |
| 1945 | GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */ |
| 1946 | GMC_PAUSE_ON = 1<<3, /* Pause On */ |
| 1947 | GMC_PAUSE_OFF = 1<<2, /* Pause Off */ |
| 1948 | GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */ |
| 1949 | GMC_RST_SET = 1<<0, /* Set GMAC Reset */ |
| 1950 | }; |
| 1951 | |
| 1952 | /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ |
| 1953 | enum { |
| 1954 | GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */ |
| 1955 | GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */ |
| 1956 | GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */ |
| 1957 | GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */ |
| 1958 | GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */ |
| 1959 | GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */ |
| 1960 | GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */ |
| 1961 | GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */ |
| 1962 | GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */ |
| 1963 | GPC_ANEG_0 = 1<<19, /* ANEG[0] */ |
| 1964 | GPC_ENA_XC = 1<<18, /* Enable MDI crossover */ |
| 1965 | GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */ |
| 1966 | GPC_ANEG_3 = 1<<16, /* ANEG[3] */ |
| 1967 | GPC_ANEG_2 = 1<<15, /* ANEG[2] */ |
| 1968 | GPC_ANEG_1 = 1<<14, /* ANEG[1] */ |
| 1969 | GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */ |
| 1970 | GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */ |
| 1971 | GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */ |
| 1972 | GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */ |
| 1973 | GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */ |
| 1974 | GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */ |
| 1975 | /* Bits 7..2: reserved */ |
| 1976 | GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */ |
| 1977 | GPC_RST_SET = 1<<0, /* Set GPHY Reset */ |
| 1978 | }; |
| 1979 | |
| 1980 | #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0) |
| 1981 | #define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0) |
| 1982 | #define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0) |
| 1983 | |
| 1984 | /* forced speed and duplex mode (don't mix with other ANEG bits) */ |
| 1985 | #define GPC_FRC10MBIT_HALF 0 |
| 1986 | #define GPC_FRC10MBIT_FULL GPC_ANEG_0 |
| 1987 | #define GPC_FRC100MBIT_HALF GPC_ANEG_1 |
| 1988 | #define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1) |
| 1989 | |
| 1990 | /* auto-negotiation with limited advertised speeds */ |
| 1991 | /* mix only with master/slave settings (for copper) */ |
| 1992 | #define GPC_ADV_1000_HALF GPC_ANEG_2 |
| 1993 | #define GPC_ADV_1000_FULL GPC_ANEG_3 |
| 1994 | #define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3) |
| 1995 | |
| 1996 | /* master/slave settings */ |
| 1997 | /* only for copper with 1000 Mbps */ |
| 1998 | #define GPC_FORCE_MASTER 0 |
| 1999 | #define GPC_FORCE_SLAVE GPC_ANEG_0 |
| 2000 | #define GPC_PREF_MASTER GPC_ANEG_1 |
| 2001 | #define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0) |
| 2002 | |
| 2003 | /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ |
| 2004 | /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ |
| 2005 | enum { |
| 2006 | GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */ |
| 2007 | GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */ |
| 2008 | GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */ |
| 2009 | GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */ |
| 2010 | GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */ |
| 2011 | GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */ |
| 2012 | |
Stephen Hemminger | 46a60f2 | 2005-09-09 12:54:56 -0700 | [diff] [blame] | 2013 | #define GMAC_DEF_MSK (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2014 | |
| 2015 | /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ |
| 2016 | /* Bits 15.. 2: reserved */ |
| 2017 | GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */ |
| 2018 | GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */ |
| 2019 | |
| 2020 | |
| 2021 | /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ |
| 2022 | WOL_CTL_LINK_CHG_OCC = 1<<15, |
| 2023 | WOL_CTL_MAGIC_PKT_OCC = 1<<14, |
| 2024 | WOL_CTL_PATTERN_OCC = 1<<13, |
| 2025 | WOL_CTL_CLEAR_RESULT = 1<<12, |
| 2026 | WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11, |
| 2027 | WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10, |
| 2028 | WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9, |
| 2029 | WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8, |
| 2030 | WOL_CTL_ENA_PME_ON_PATTERN = 1<<7, |
| 2031 | WOL_CTL_DIS_PME_ON_PATTERN = 1<<6, |
| 2032 | WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5, |
| 2033 | WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4, |
| 2034 | WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3, |
| 2035 | WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2, |
| 2036 | WOL_CTL_ENA_PATTERN_UNIT = 1<<1, |
| 2037 | WOL_CTL_DIS_PATTERN_UNIT = 1<<0, |
| 2038 | }; |
| 2039 | |
| 2040 | #define WOL_CTL_DEFAULT \ |
| 2041 | (WOL_CTL_DIS_PME_ON_LINK_CHG | \ |
| 2042 | WOL_CTL_DIS_PME_ON_PATTERN | \ |
| 2043 | WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ |
| 2044 | WOL_CTL_DIS_LINK_CHG_UNIT | \ |
| 2045 | WOL_CTL_DIS_PATTERN_UNIT | \ |
| 2046 | WOL_CTL_DIS_MAGIC_PKT_UNIT) |
| 2047 | |
| 2048 | /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ |
| 2049 | #define WOL_CTL_PATT_ENA(x) (1 << (x)) |
| 2050 | |
| 2051 | |
| 2052 | /* XMAC II registers */ |
| 2053 | enum { |
| 2054 | XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */ |
| 2055 | XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */ |
| 2056 | XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/ |
| 2057 | XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */ |
| 2058 | XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */ |
| 2059 | XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */ |
| 2060 | XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */ |
| 2061 | XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */ |
| 2062 | XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */ |
| 2063 | XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */ |
| 2064 | XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */ |
| 2065 | XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */ |
| 2066 | XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */ |
| 2067 | XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */ |
| 2068 | XM_ISRC = 0x0048, /* 16 bit r/o Interrupt Status Register */ |
| 2069 | XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */ |
| 2070 | XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */ |
| 2071 | XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */ |
| 2072 | XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */ |
| 2073 | XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */ |
| 2074 | XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */ |
| 2075 | XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */ |
| 2076 | XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */ |
| 2077 | XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/ |
| 2078 | XM_TX_STAT = 0x0078, /* 32 bit r/o Tx Status LIFO Register */ |
| 2079 | |
| 2080 | XM_EXM_START = 0x0080, /* r/w Start Address of the EXM Regs */ |
| 2081 | #define XM_EXM(reg) (XM_EXM_START + ((reg) << 3)) |
| 2082 | }; |
| 2083 | |
| 2084 | enum { |
| 2085 | XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */ |
| 2086 | XM_SA = 0x0108, /* NA reg r/w Station Address Register */ |
| 2087 | XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */ |
| 2088 | XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */ |
| 2089 | XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */ |
| 2090 | XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */ |
| 2091 | XM_DEV_ID = 0x0120, /* 32 bit r/o Device ID Register */ |
| 2092 | XM_MODE = 0x0124, /* 32 bit r/w Mode Register */ |
| 2093 | XM_LSA = 0x0128, /* NA reg r/o Last Source Register */ |
| 2094 | XM_TS_READ = 0x0130, /* 32 bit r/o Time Stamp Read Register */ |
| 2095 | XM_TS_LOAD = 0x0134, /* 32 bit r/o Time Stamp Load Value */ |
| 2096 | XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */ |
| 2097 | XM_RX_CNT_EV = 0x0204, /* 32 bit r/o Rx Counter Event Register */ |
| 2098 | XM_TX_CNT_EV = 0x0208, /* 32 bit r/o Tx Counter Event Register */ |
| 2099 | XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */ |
| 2100 | XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */ |
| 2101 | XM_TXF_OK = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */ |
| 2102 | XM_TXO_OK_HI = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/ |
| 2103 | XM_TXO_OK_LO = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */ |
| 2104 | XM_TXF_BC_OK = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */ |
| 2105 | XM_TXF_MC_OK = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */ |
| 2106 | XM_TXF_UC_OK = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */ |
| 2107 | XM_TXF_LONG = 0x0298, /* 32 bit r/o Tx Long Frame Counter */ |
| 2108 | XM_TXE_BURST = 0x029c, /* 32 bit r/o Tx Burst Event Counter */ |
| 2109 | XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */ |
| 2110 | XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */ |
| 2111 | XM_TXF_SNG_COL = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */ |
| 2112 | XM_TXF_MUL_COL = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */ |
| 2113 | XM_TXF_ABO_COL = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */ |
| 2114 | XM_TXF_LAT_COL = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */ |
| 2115 | XM_TXF_DEF = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */ |
| 2116 | XM_TXF_EX_DEF = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */ |
| 2117 | XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */ |
| 2118 | XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */ |
| 2119 | XM_TXP_UTIL = 0x02c8, /* 32 bit r/o Tx Utilization in % */ |
| 2120 | XM_TXF_64B = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */ |
| 2121 | XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */ |
| 2122 | XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */ |
| 2123 | XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */ |
| 2124 | XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/ |
| 2125 | XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/ |
| 2126 | XM_RXF_OK = 0x0300, /* 32 bit r/o Frames Received OK */ |
| 2127 | XM_RXO_OK_HI = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */ |
| 2128 | XM_RXO_OK_LO = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/ |
| 2129 | XM_RXF_BC_OK = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */ |
| 2130 | XM_RXF_MC_OK = 0x0310, /* 32 bit r/o Multicast Frames Received OK */ |
| 2131 | XM_RXF_UC_OK = 0x0314, /* 32 bit r/o Unicast Frames Received OK */ |
| 2132 | XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */ |
| 2133 | XM_RXF_MCTRL = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */ |
| 2134 | XM_RXF_INV_MP = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */ |
| 2135 | XM_RXF_INV_MOC = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/ |
| 2136 | XM_RXE_BURST = 0x0328, /* 32 bit r/o Rx Burst Event Counter */ |
| 2137 | XM_RXE_FMISS = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */ |
| 2138 | XM_RXF_FRA_ERR = 0x0330, /* 32 bit r/o Rx Framing Error Counter */ |
| 2139 | XM_RXE_FIFO_OV = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */ |
| 2140 | XM_RXF_JAB_PKT = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */ |
| 2141 | XM_RXE_CAR_ERR = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */ |
| 2142 | XM_RXF_LEN_ERR = 0x0340, /* 32 bit r/o Rx in Range Length Error */ |
| 2143 | XM_RXE_SYM_ERR = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */ |
| 2144 | XM_RXE_SHT_ERR = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */ |
| 2145 | XM_RXE_RUNT = 0x034c, /* 32 bit r/o Rx Runt Event Counter */ |
| 2146 | XM_RXF_LNG_ERR = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */ |
| 2147 | XM_RXF_FCS_ERR = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */ |
| 2148 | XM_RXF_CEX_ERR = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/ |
| 2149 | XM_RXP_UTIL = 0x0360, /* 32 bit r/o Rx Utilization in % */ |
| 2150 | XM_RXF_64B = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */ |
| 2151 | XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */ |
| 2152 | XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */ |
| 2153 | XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */ |
| 2154 | XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/ |
| 2155 | XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/ |
| 2156 | }; |
| 2157 | |
| 2158 | /* XM_MMU_CMD 16 bit r/w MMU Command Register */ |
| 2159 | enum { |
| 2160 | XM_MMU_PHY_RDY = 1<<12,/* Bit 12: PHY Read Ready */ |
| 2161 | XM_MMU_PHY_BUSY = 1<<11,/* Bit 11: PHY Busy */ |
| 2162 | XM_MMU_IGN_PF = 1<<10,/* Bit 10: Ignore Pause Frame */ |
| 2163 | XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */ |
| 2164 | XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */ |
| 2165 | XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */ |
| 2166 | XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */ |
| 2167 | XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */ |
| 2168 | XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */ |
| 2169 | XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */ |
| 2170 | XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */ |
| 2171 | XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */ |
| 2172 | }; |
| 2173 | |
| 2174 | |
| 2175 | /* XM_TX_CMD 16 bit r/w Transmit Command Register */ |
| 2176 | enum { |
| 2177 | XM_TX_BK2BK = 1<<6, /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/ |
| 2178 | XM_TX_ENC_BYP = 1<<5, /* Bit 5: Set Encoder in Bypass Mode */ |
| 2179 | XM_TX_SAM_LINE = 1<<4, /* Bit 4: (sc) Start utilization calculation */ |
| 2180 | XM_TX_NO_GIG_MD = 1<<3, /* Bit 3: Disable Carrier Extension */ |
| 2181 | XM_TX_NO_PRE = 1<<2, /* Bit 2: Disable Preamble Generation */ |
| 2182 | XM_TX_NO_CRC = 1<<1, /* Bit 1: Disable CRC Generation */ |
| 2183 | XM_TX_AUTO_PAD = 1<<0, /* Bit 0: Enable Automatic Padding */ |
| 2184 | }; |
| 2185 | |
| 2186 | /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */ |
| 2187 | #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */ |
| 2188 | |
| 2189 | |
| 2190 | /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */ |
| 2191 | #define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */ |
| 2192 | |
| 2193 | |
| 2194 | /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */ |
| 2195 | #define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */ |
| 2196 | |
| 2197 | |
| 2198 | /* XM_RX_CMD 16 bit r/w Receive Command Register */ |
| 2199 | enum { |
| 2200 | XM_RX_LENERR_OK = 1<<8, /* Bit 8 don't set Rx Err bit for */ |
| 2201 | /* inrange error packets */ |
| 2202 | XM_RX_BIG_PK_OK = 1<<7, /* Bit 7 don't set Rx Err bit for */ |
| 2203 | /* jumbo packets */ |
| 2204 | XM_RX_IPG_CAP = 1<<6, /* Bit 6 repl. type field with IPG */ |
| 2205 | XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */ |
| 2206 | XM_RX_STRIP_FCS = 1<<4, /* Bit 4: Enable FCS Stripping */ |
| 2207 | XM_RX_SELF_RX = 1<<3, /* Bit 3: Enable Rx of own packets */ |
| 2208 | XM_RX_SAM_LINE = 1<<2, /* Bit 2: (sc) Start utilization calculation */ |
| 2209 | XM_RX_STRIP_PAD = 1<<1, /* Bit 1: Strip pad bytes of Rx frames */ |
| 2210 | XM_RX_DIS_CEXT = 1<<0, /* Bit 0: Disable carrier ext. check */ |
| 2211 | }; |
| 2212 | |
| 2213 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2214 | /* XM_GP_PORT 32 bit r/w General Purpose Port Register */ |
| 2215 | enum { |
| 2216 | XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */ |
| 2217 | XM_GP_FRC_INT = 1<<5, /* Bit 5: (sc) Force Interrupt */ |
| 2218 | XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */ |
| 2219 | XM_GP_RES_STAT = 1<<2, /* Bit 2: (sc) Reset the statistics module */ |
| 2220 | XM_GP_INP_ASS = 1<<0, /* Bit 0: (ro) GP Input Pin asserted */ |
| 2221 | }; |
| 2222 | |
| 2223 | |
| 2224 | /* XM_IMSK 16 bit r/w Interrupt Mask Register */ |
| 2225 | /* XM_ISRC 16 bit r/o Interrupt Status Register */ |
| 2226 | enum { |
| 2227 | XM_IS_LNK_AE = 1<<14, /* Bit 14: Link Asynchronous Event */ |
| 2228 | XM_IS_TX_ABORT = 1<<13, /* Bit 13: Transmit Abort, late Col. etc */ |
| 2229 | XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */ |
| 2230 | XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */ |
| 2231 | XM_IS_LIPA_RC = 1<<10, /* Bit 10: Link Partner requests config */ |
| 2232 | XM_IS_RX_PAGE = 1<<9, /* Bit 9: Page Received */ |
| 2233 | XM_IS_TX_PAGE = 1<<8, /* Bit 8: Next Page Loaded for Transmit */ |
| 2234 | XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */ |
| 2235 | XM_IS_TSC_OV = 1<<6, /* Bit 6: Time Stamp Counter Overflow */ |
| 2236 | XM_IS_RXC_OV = 1<<5, /* Bit 5: Rx Counter Event Overflow */ |
| 2237 | XM_IS_TXC_OV = 1<<4, /* Bit 4: Tx Counter Event Overflow */ |
| 2238 | XM_IS_RXF_OV = 1<<3, /* Bit 3: Receive FIFO Overflow */ |
| 2239 | XM_IS_TXF_UR = 1<<2, /* Bit 2: Transmit FIFO Underrun */ |
| 2240 | XM_IS_TX_COMP = 1<<1, /* Bit 1: Frame Tx Complete */ |
| 2241 | XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */ |
| 2242 | }; |
| 2243 | |
| 2244 | #define XM_DEF_MSK (~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | \ |
| 2245 | XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | \ |
| 2246 | XM_IS_RXF_OV | XM_IS_TXF_UR)) |
| 2247 | |
| 2248 | |
| 2249 | /* XM_HW_CFG 16 bit r/w Hardware Config Register */ |
| 2250 | enum { |
| 2251 | XM_HW_GEN_EOP = 1<<3, /* Bit 3: generate End of Packet pulse */ |
| 2252 | XM_HW_COM4SIG = 1<<2, /* Bit 2: use Comma Detect for Sig. Det.*/ |
| 2253 | XM_HW_GMII_MD = 1<<0, /* Bit 0: GMII Interface selected */ |
| 2254 | }; |
| 2255 | |
| 2256 | |
| 2257 | /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */ |
| 2258 | /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */ |
| 2259 | #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */ |
| 2260 | |
| 2261 | /* XM_TX_THR 16 bit r/w Tx Request Threshold */ |
| 2262 | /* XM_HT_THR 16 bit r/w Host Request Threshold */ |
| 2263 | /* XM_RX_THR 16 bit r/w Rx Request Threshold */ |
| 2264 | #define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */ |
| 2265 | |
| 2266 | |
| 2267 | /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */ |
| 2268 | enum { |
| 2269 | XM_ST_VALID = (1UL<<31), /* Bit 31: Status Valid */ |
| 2270 | XM_ST_BYTE_CNT = (0x3fffL<<17), /* Bit 30..17: Tx frame Length */ |
| 2271 | XM_ST_RETRY_CNT = (0x1fL<<12), /* Bit 16..12: Retry Count */ |
| 2272 | XM_ST_EX_COL = 1<<11, /* Bit 11: Excessive Collisions */ |
| 2273 | XM_ST_EX_DEF = 1<<10, /* Bit 10: Excessive Deferral */ |
| 2274 | XM_ST_BURST = 1<<9, /* Bit 9: p. xmitted in burst md*/ |
| 2275 | XM_ST_DEFER = 1<<8, /* Bit 8: packet was defered */ |
| 2276 | XM_ST_BC = 1<<7, /* Bit 7: Broadcast packet */ |
| 2277 | XM_ST_MC = 1<<6, /* Bit 6: Multicast packet */ |
| 2278 | XM_ST_UC = 1<<5, /* Bit 5: Unicast packet */ |
| 2279 | XM_ST_TX_UR = 1<<4, /* Bit 4: FIFO Underrun occured */ |
| 2280 | XM_ST_CS_ERR = 1<<3, /* Bit 3: Carrier Sense Error */ |
| 2281 | XM_ST_LAT_COL = 1<<2, /* Bit 2: Late Collision Error */ |
| 2282 | XM_ST_MUL_COL = 1<<1, /* Bit 1: Multiple Collisions */ |
| 2283 | XM_ST_SGN_COL = 1<<0, /* Bit 0: Single Collision */ |
| 2284 | }; |
| 2285 | |
| 2286 | /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */ |
| 2287 | /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */ |
| 2288 | #define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */ |
| 2289 | |
| 2290 | |
| 2291 | /* XM_DEV_ID 32 bit r/o Device ID Register */ |
| 2292 | #define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */ |
| 2293 | #define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */ |
| 2294 | |
| 2295 | |
| 2296 | /* XM_MODE 32 bit r/w Mode Register */ |
| 2297 | enum { |
| 2298 | XM_MD_ENA_REJ = 1<<26, /* Bit 26: Enable Frame Reject */ |
| 2299 | XM_MD_SPOE_E = 1<<25, /* Bit 25: Send Pause on Edge */ |
| 2300 | /* extern generated */ |
| 2301 | XM_MD_TX_REP = 1<<24, /* Bit 24: Transmit Repeater Mode */ |
| 2302 | XM_MD_SPOFF_I = 1<<23, /* Bit 23: Send Pause on FIFO full */ |
| 2303 | /* intern generated */ |
| 2304 | XM_MD_LE_STW = 1<<22, /* Bit 22: Rx Stat Word in Little Endian */ |
| 2305 | XM_MD_TX_CONT = 1<<21, /* Bit 21: Send Continuous */ |
| 2306 | XM_MD_TX_PAUSE = 1<<20, /* Bit 20: (sc) Send Pause Frame */ |
| 2307 | XM_MD_ATS = 1<<19, /* Bit 19: Append Time Stamp */ |
| 2308 | XM_MD_SPOL_I = 1<<18, /* Bit 18: Send Pause on Low */ |
| 2309 | /* intern generated */ |
| 2310 | XM_MD_SPOH_I = 1<<17, /* Bit 17: Send Pause on High */ |
| 2311 | /* intern generated */ |
| 2312 | XM_MD_CAP = 1<<16, /* Bit 16: Check Address Pair */ |
| 2313 | XM_MD_ENA_HASH = 1<<15, /* Bit 15: Enable Hashing */ |
| 2314 | XM_MD_CSA = 1<<14, /* Bit 14: Check Station Address */ |
| 2315 | XM_MD_CAA = 1<<13, /* Bit 13: Check Address Array */ |
| 2316 | XM_MD_RX_MCTRL = 1<<12, /* Bit 12: Rx MAC Control Frame */ |
| 2317 | XM_MD_RX_RUNT = 1<<11, /* Bit 11: Rx Runt Frames */ |
| 2318 | XM_MD_RX_IRLE = 1<<10, /* Bit 10: Rx in Range Len Err Frame */ |
| 2319 | XM_MD_RX_LONG = 1<<9, /* Bit 9: Rx Long Frame */ |
| 2320 | XM_MD_RX_CRCE = 1<<8, /* Bit 8: Rx CRC Error Frame */ |
| 2321 | XM_MD_RX_ERR = 1<<7, /* Bit 7: Rx Error Frame */ |
| 2322 | XM_MD_DIS_UC = 1<<6, /* Bit 6: Disable Rx Unicast */ |
| 2323 | XM_MD_DIS_MC = 1<<5, /* Bit 5: Disable Rx Multicast */ |
| 2324 | XM_MD_DIS_BC = 1<<4, /* Bit 4: Disable Rx Broadcast */ |
| 2325 | XM_MD_ENA_PROM = 1<<3, /* Bit 3: Enable Promiscuous */ |
| 2326 | XM_MD_ENA_BE = 1<<2, /* Bit 2: Enable Big Endian */ |
| 2327 | XM_MD_FTF = 1<<1, /* Bit 1: (sc) Flush Tx FIFO */ |
| 2328 | XM_MD_FRF = 1<<0, /* Bit 0: (sc) Flush Rx FIFO */ |
| 2329 | }; |
| 2330 | |
| 2331 | #define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I) |
Stephen Hemminger | 7e676d9 | 2005-06-27 11:33:13 -0700 | [diff] [blame] | 2332 | #define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\ |
| 2333 | XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2334 | |
| 2335 | /* XM_STAT_CMD 16 bit r/w Statistics Command Register */ |
| 2336 | enum { |
| 2337 | XM_SC_SNP_RXC = 1<<5, /* Bit 5: (sc) Snap Rx Counters */ |
| 2338 | XM_SC_SNP_TXC = 1<<4, /* Bit 4: (sc) Snap Tx Counters */ |
| 2339 | XM_SC_CP_RXC = 1<<3, /* Bit 3: Copy Rx Counters Continuously */ |
| 2340 | XM_SC_CP_TXC = 1<<2, /* Bit 2: Copy Tx Counters Continuously */ |
| 2341 | XM_SC_CLR_RXC = 1<<1, /* Bit 1: (sc) Clear Rx Counters */ |
| 2342 | XM_SC_CLR_TXC = 1<<0, /* Bit 0: (sc) Clear Tx Counters */ |
| 2343 | }; |
| 2344 | |
| 2345 | |
| 2346 | /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */ |
| 2347 | /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */ |
| 2348 | enum { |
| 2349 | XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/ |
| 2350 | XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/ |
| 2351 | XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/ |
| 2352 | XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/ |
| 2353 | XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */ |
| 2354 | XMR_64B_OV = 1<<26, /* Bit 26: 64 Byte Rx Cnt Ov */ |
| 2355 | XMR_UTIL_OV = 1<<25, /* Bit 25: Rx Util Cnt Overflow */ |
| 2356 | XMR_UTIL_UR = 1<<24, /* Bit 24: Rx Util Cnt Underrun */ |
| 2357 | XMR_CEX_ERR_OV = 1<<23, /* Bit 23: CEXT Err Cnt Ov */ |
| 2358 | XMR_FCS_ERR_OV = 1<<21, /* Bit 21: Rx FCS Error Cnt Ov */ |
| 2359 | XMR_LNG_ERR_OV = 1<<20, /* Bit 20: Rx too Long Err Cnt Ov*/ |
| 2360 | XMR_RUNT_OV = 1<<19, /* Bit 19: Runt Event Cnt Ov */ |
| 2361 | XMR_SHT_ERR_OV = 1<<18, /* Bit 18: Rx Short Ev Err Cnt Ov*/ |
| 2362 | XMR_SYM_ERR_OV = 1<<17, /* Bit 17: Rx Sym Err Cnt Ov */ |
| 2363 | XMR_CAR_ERR_OV = 1<<15, /* Bit 15: Rx Carr Ev Err Cnt Ov */ |
| 2364 | XMR_JAB_PKT_OV = 1<<14, /* Bit 14: Rx Jabb Packet Cnt Ov */ |
| 2365 | XMR_FIFO_OV = 1<<13, /* Bit 13: Rx FIFO Ov Ev Cnt Ov */ |
| 2366 | XMR_FRA_ERR_OV = 1<<12, /* Bit 12: Rx Framing Err Cnt Ov */ |
| 2367 | XMR_FMISS_OV = 1<<11, /* Bit 11: Rx Missed Ev Cnt Ov */ |
| 2368 | XMR_BURST = 1<<10, /* Bit 10: Rx Burst Event Cnt Ov */ |
| 2369 | XMR_INV_MOC = 1<<9, /* Bit 9: Rx with inv. MAC OC Ov*/ |
| 2370 | XMR_INV_MP = 1<<8, /* Bit 8: Rx inv Pause Frame Ov */ |
| 2371 | XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */ |
| 2372 | XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/ |
| 2373 | XMR_UC_OK_OV = 1<<5, /* Bit 5: Rx Unicast Frame CntOv*/ |
| 2374 | XMR_MC_OK_OV = 1<<4, /* Bit 4: Rx Multicast Cnt Ov */ |
| 2375 | XMR_BC_OK_OV = 1<<3, /* Bit 3: Rx Broadcast Cnt Ov */ |
| 2376 | XMR_OK_LO_OV = 1<<2, /* Bit 2: Octets Rx OK Low CntOv*/ |
| 2377 | XMR_OK_HI_OV = 1<<1, /* Bit 1: Octets Rx OK Hi Cnt Ov*/ |
| 2378 | XMR_OK_OV = 1<<0, /* Bit 0: Frames Received Ok Ov */ |
| 2379 | }; |
| 2380 | |
| 2381 | #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV) |
| 2382 | |
| 2383 | /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */ |
| 2384 | /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */ |
| 2385 | enum { |
| 2386 | XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/ |
| 2387 | XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/ |
| 2388 | XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/ |
| 2389 | XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/ |
| 2390 | XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */ |
| 2391 | XMT_64B_OV = 1<<20, /* Bit 20: 64 Byte Tx Cnt Ov */ |
| 2392 | XMT_UTIL_OV = 1<<19, /* Bit 19: Tx Util Cnt Overflow */ |
| 2393 | XMT_UTIL_UR = 1<<18, /* Bit 18: Tx Util Cnt Underrun */ |
| 2394 | XMT_CS_ERR_OV = 1<<17, /* Bit 17: Tx Carr Sen Err Cnt Ov*/ |
| 2395 | XMT_FIFO_UR_OV = 1<<16, /* Bit 16: Tx FIFO Ur Ev Cnt Ov */ |
| 2396 | XMT_EX_DEF_OV = 1<<15, /* Bit 15: Tx Ex Deferall Cnt Ov */ |
| 2397 | XMT_DEF = 1<<14, /* Bit 14: Tx Deferred Cnt Ov */ |
| 2398 | XMT_LAT_COL_OV = 1<<13, /* Bit 13: Tx Late Col Cnt Ov */ |
| 2399 | XMT_ABO_COL_OV = 1<<12, /* Bit 12: Tx abo dueto Ex Col Ov*/ |
| 2400 | XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */ |
| 2401 | XMT_SNG_COL = 1<<10, /* Bit 10: Tx Single Col Cnt Ov */ |
| 2402 | XMT_MCTRL_OV = 1<<9, /* Bit 9: Tx MAC Ctrl Counter Ov*/ |
| 2403 | XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/ |
| 2404 | XMT_BURST = 1<<7, /* Bit 7: Tx Burst Event Cnt Ov */ |
| 2405 | XMT_LONG = 1<<6, /* Bit 6: Tx Long Frame Cnt Ov */ |
| 2406 | XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */ |
| 2407 | XMT_MC_OK_OV = 1<<4, /* Bit 4: Tx Multicast Cnt Ov */ |
| 2408 | XMT_BC_OK_OV = 1<<3, /* Bit 3: Tx Broadcast Cnt Ov */ |
| 2409 | XMT_OK_LO_OV = 1<<2, /* Bit 2: Octets Tx OK Low CntOv*/ |
| 2410 | XMT_OK_HI_OV = 1<<1, /* Bit 1: Octets Tx OK Hi Cnt Ov*/ |
| 2411 | XMT_OK_OV = 1<<0, /* Bit 0: Frames Tx Ok Ov */ |
| 2412 | }; |
| 2413 | |
| 2414 | #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV) |
| 2415 | |
| 2416 | struct skge_rx_desc { |
| 2417 | u32 control; |
| 2418 | u32 next_offset; |
| 2419 | u32 dma_lo; |
| 2420 | u32 dma_hi; |
| 2421 | u32 status; |
| 2422 | u32 timestamp; |
| 2423 | u16 csum2; |
| 2424 | u16 csum1; |
| 2425 | u16 csum2_start; |
| 2426 | u16 csum1_start; |
| 2427 | }; |
| 2428 | |
| 2429 | struct skge_tx_desc { |
| 2430 | u32 control; |
| 2431 | u32 next_offset; |
| 2432 | u32 dma_lo; |
| 2433 | u32 dma_hi; |
| 2434 | u32 status; |
| 2435 | u32 csum_offs; |
| 2436 | u16 csum_write; |
| 2437 | u16 csum_start; |
| 2438 | u32 rsvd; |
| 2439 | }; |
| 2440 | |
| 2441 | struct skge_element { |
| 2442 | struct skge_element *next; |
| 2443 | void *desc; |
| 2444 | struct sk_buff *skb; |
| 2445 | DECLARE_PCI_UNMAP_ADDR(mapaddr); |
| 2446 | DECLARE_PCI_UNMAP_LEN(maplen); |
| 2447 | }; |
| 2448 | |
| 2449 | struct skge_ring { |
| 2450 | struct skge_element *to_clean; |
| 2451 | struct skge_element *to_use; |
| 2452 | struct skge_element *start; |
| 2453 | unsigned long count; |
| 2454 | }; |
| 2455 | |
| 2456 | |
| 2457 | struct skge_hw { |
| 2458 | void __iomem *regs; |
| 2459 | struct pci_dev *pdev; |
| 2460 | u32 intr_mask; |
| 2461 | struct net_device *dev[2]; |
| 2462 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2463 | u8 chip_id; |
Stephen Hemminger | 981d037 | 2005-06-27 11:33:06 -0700 | [diff] [blame] | 2464 | u8 chip_rev; |
Stephen Hemminger | 5e1705d | 2005-08-16 14:00:58 -0700 | [diff] [blame] | 2465 | u8 copper; |
Stephen Hemminger | 981d037 | 2005-06-27 11:33:06 -0700 | [diff] [blame] | 2466 | u8 ports; |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2467 | |
| 2468 | u32 ram_size; |
| 2469 | u32 ram_offset; |
Stephen Hemminger | 5e1705d | 2005-08-16 14:00:58 -0700 | [diff] [blame] | 2470 | u16 phy_addr; |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 2471 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2472 | struct tasklet_struct ext_tasklet; |
| 2473 | spinlock_t phy_lock; |
| 2474 | }; |
| 2475 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2476 | enum { |
| 2477 | FLOW_MODE_NONE = 0, /* No Flow-Control */ |
| 2478 | FLOW_MODE_LOC_SEND = 1, /* Local station sends PAUSE */ |
| 2479 | FLOW_MODE_REM_SEND = 2, /* Symmetric or just remote */ |
| 2480 | FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */ |
| 2481 | }; |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 2482 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2483 | struct skge_port { |
| 2484 | u32 msg_enable; |
| 2485 | struct skge_hw *hw; |
| 2486 | struct net_device *netdev; |
| 2487 | int port; |
| 2488 | |
| 2489 | spinlock_t tx_lock; |
| 2490 | u32 tx_avail; |
| 2491 | struct skge_ring tx_ring; |
| 2492 | struct skge_ring rx_ring; |
| 2493 | |
| 2494 | struct net_device_stats net_stats; |
| 2495 | |
| 2496 | u8 rx_csum; |
| 2497 | u8 blink_on; |
| 2498 | u8 flow_control; |
| 2499 | u8 wol; |
| 2500 | u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */ |
| 2501 | u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */ |
| 2502 | u16 speed; /* SPEED_1000, SPEED_100, ... */ |
| 2503 | u32 advertising; |
| 2504 | |
| 2505 | void *mem; /* PCI memory for rings */ |
| 2506 | dma_addr_t dma; |
| 2507 | unsigned long mem_size; |
Stephen Hemminger | 19a33d4 | 2005-06-27 11:33:15 -0700 | [diff] [blame] | 2508 | unsigned int rx_buf_size; |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2509 | }; |
| 2510 | |
| 2511 | |
| 2512 | /* Register accessor for memory mapped device */ |
| 2513 | static inline u32 skge_read32(const struct skge_hw *hw, int reg) |
| 2514 | { |
| 2515 | return readl(hw->regs + reg); |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2516 | } |
| 2517 | |
| 2518 | static inline u16 skge_read16(const struct skge_hw *hw, int reg) |
| 2519 | { |
| 2520 | return readw(hw->regs + reg); |
| 2521 | } |
| 2522 | |
| 2523 | static inline u8 skge_read8(const struct skge_hw *hw, int reg) |
| 2524 | { |
| 2525 | return readb(hw->regs + reg); |
| 2526 | } |
| 2527 | |
| 2528 | static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val) |
| 2529 | { |
| 2530 | writel(val, hw->regs + reg); |
| 2531 | } |
| 2532 | |
| 2533 | static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val) |
| 2534 | { |
| 2535 | writew(val, hw->regs + reg); |
| 2536 | } |
| 2537 | |
| 2538 | static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val) |
| 2539 | { |
| 2540 | writeb(val, hw->regs + reg); |
| 2541 | } |
| 2542 | |
| 2543 | /* MAC Related Registers inside the device. */ |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2544 | #define SK_REG(port,reg) (((port)<<7)+(reg)) |
| 2545 | #define SK_XMAC_REG(port, reg) \ |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2546 | ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1) |
| 2547 | |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2548 | static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2549 | { |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2550 | u32 v; |
| 2551 | v = skge_read16(hw, SK_XMAC_REG(port, reg)); |
| 2552 | v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16; |
| 2553 | return v; |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2554 | } |
| 2555 | |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2556 | static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2557 | { |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2558 | return skge_read16(hw, SK_XMAC_REG(port,reg)); |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2559 | } |
| 2560 | |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2561 | static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2562 | { |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2563 | skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff); |
| 2564 | skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16); |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2565 | } |
| 2566 | |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2567 | static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2568 | { |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2569 | skge_write16(hw, SK_XMAC_REG(port,r), v); |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2570 | } |
| 2571 | |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2572 | static inline void xm_outhash(const struct skge_hw *hw, int port, int reg, |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2573 | const u8 *hash) |
| 2574 | { |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2575 | xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8)); |
| 2576 | xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8)); |
| 2577 | xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8)); |
| 2578 | xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8)); |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2579 | } |
| 2580 | |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2581 | static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg, |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2582 | const u8 *addr) |
| 2583 | { |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2584 | xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8)); |
| 2585 | xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8)); |
| 2586 | xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8)); |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2587 | } |
| 2588 | |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2589 | #define SK_GMAC_REG(port,reg) \ |
| 2590 | (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg)) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2591 | |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2592 | static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2593 | { |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2594 | return skge_read16(hw, SK_GMAC_REG(port,reg)); |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2595 | } |
| 2596 | |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2597 | static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2598 | { |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2599 | return (u32) skge_read16(hw, SK_GMAC_REG(port,reg)) |
| 2600 | | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16); |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2601 | } |
| 2602 | |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2603 | static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v) |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2604 | { |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2605 | skge_write16(hw, SK_GMAC_REG(port,r), v); |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2606 | } |
| 2607 | |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2608 | static inline void gma_set_addr(struct skge_hw *hw, int port, int reg, |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2609 | const u8 *addr) |
| 2610 | { |
Stephen Hemminger | 6b0c148 | 2005-06-27 11:33:04 -0700 | [diff] [blame] | 2611 | gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8)); |
| 2612 | gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8)); |
| 2613 | gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8)); |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2614 | } |
Stephen Hemminger | 9556606 | 2005-06-27 11:33:02 -0700 | [diff] [blame] | 2615 | |
Stephen Hemminger | baef58b | 2005-05-12 20:14:36 -0400 | [diff] [blame] | 2616 | #endif |